arch/sparc/kernel/pci.c

   1 /* pci.c: UltraSparc PCI controller support.
   2  *
   3  * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
   4  * Copyright (C) 1998, 1999 Eddie C. Dost   (ecd@skynet.be)
   5  * Copyright (C) 1999 Jakub Jelinek   (jj@ultra.linux.cz)
   6  *
   7  * OF tree based PCI bus probing taken from the PowerPC port
   8  * with minor modifications, see there for credits.
   9  */
  10
  11 #include <linux/export.h>
  12 #include <linux/kernel.h>
  13 #include <linux/string.h>
  14 #include <linux/sched.h>
  15 #include <linux/capability.h>
  16 #include <linux/errno.h>
  17 #include <linux/pci.h>
  18 #include <linux/msi.h>
  19 #include <linux/irq.h>
  20 #include <linux/init.h>
  21 #include <linux/of.h>
  22 #include <linux/of_device.h>
  23
  24 #include <asm/uaccess.h>
  25 #include <asm/pgtable.h>
  26 #include <asm/irq.h>
  27 #include <asm/prom.h>
  28 #include <asm/apb.h>
  29
  30 #include "pci_impl.h"
  31
  32 /* List of all PCI controllers found in the system. */
  33 struct pci_pbm_info *pci_pbm_root = NULL;
  34
  35 /* Each PBM found gets a unique index. */
  36 int pci_num_pbms = 0;
  37
  38 volatile int pci_poke_in_progress;
  39 volatile int pci_poke_cpu = -1;
  40 volatile int pci_poke_faulted;
  41
  42 static DEFINE_SPINLOCK(pci_poke_lock);
  43
  44 void pci_config_read8(u8 *addr, u8 *ret)
  45 {
  46         unsigned long flags;
  47         u8 byte;
  48
  49         spin_lock_irqsave(&pci_poke_lock, flags);
  50         pci_poke_cpu = smp_processor_id();
  51         pci_poke_in_progress = 1;
  52         pci_poke_faulted = 0;
  53         __asm__ __volatile__("membar #Sync\n\t"
  54                              "lduba [%1] %2, %0\n\t"
  55                              "membar #Sync"
  56                              : "=r" (byte)
  57                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
  58                              : "memory");
  59         pci_poke_in_progress = 0;
  60         pci_poke_cpu = -1;
  61         if (!pci_poke_faulted)
  62                 *ret = byte;
  63         spin_unlock_irqrestore(&pci_poke_lock, flags);
  64 }
  65
  66 void pci_config_read16(u16 *addr, u16 *ret)
  67 {
  68         unsigned long flags;
  69         u16 word;
  70
  71         spin_lock_irqsave(&pci_poke_lock, flags);
  72         pci_poke_cpu = smp_processor_id();
  73         pci_poke_in_progress = 1;
  74         pci_poke_faulted = 0;
  75         __asm__ __volatile__("membar #Sync\n\t"
  76                              "lduha [%1] %2, %0\n\t"
  77                              "membar #Sync"
  78                              : "=r" (word)
  79                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
  80                              : "memory");
  81         pci_poke_in_progress = 0;
  82         pci_poke_cpu = -1;
  83         if (!pci_poke_faulted)
  84                 *ret = word;
  85         spin_unlock_irqrestore(&pci_poke_lock, flags);
  86 }
  87
  88 void pci_config_read32(u32 *addr, u32 *ret)
  89 {
  90         unsigned long flags;
  91         u32 dword;
  92
  93         spin_lock_irqsave(&pci_poke_lock, flags);
  94         pci_poke_cpu = smp_processor_id();
  95         pci_poke_in_progress = 1;
  96         pci_poke_faulted = 0;
  97         __asm__ __volatile__("membar #Sync\n\t"
  98                              "lduwa [%1] %2, %0\n\t"
  99                              "membar #Sync"
 100                              : "=r" (dword)
 101                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
 102                              : "memory");
 103         pci_poke_in_progress = 0;
 104         pci_poke_cpu = -1;
 105         if (!pci_poke_faulted)
 106                 *ret = dword;
 107         spin_unlock_irqrestore(&pci_poke_lock, flags);
 108 }
 109
 110 void pci_config_write8(u8 *addr, u8 val)
 111 {
 112         unsigned long flags;
 113
 114         spin_lock_irqsave(&pci_poke_lock, flags);
 115         pci_poke_cpu = smp_processor_id();
 116         pci_poke_in_progress = 1;
 117         pci_poke_faulted = 0;
 118         __asm__ __volatile__("membar #Sync\n\t"
 119                              "stba %0, [%1] %2\n\t"
 120                              "membar #Sync"
 121                              : /* no outputs */
 122                              : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
 123                              : "memory");
 124         pci_poke_in_progress = 0;
 125         pci_poke_cpu = -1;
 126         spin_unlock_irqrestore(&pci_poke_lock, flags);
 127 }
 128
 129 void pci_config_write16(u16 *addr, u16 val)
 130 {
 131         unsigned long flags;
 132
 133         spin_lock_irqsave(&pci_poke_lock, flags);
 134         pci_poke_cpu = smp_processor_id();
 135         pci_poke_in_progress = 1;
 136         pci_poke_faulted = 0;
 137         __asm__ __volatile__("membar #Sync\n\t"
 138                              "stha %0, [%1] %2\n\t"
 139                              "membar #Sync"
 140                              : /* no outputs */
 141                              : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
 142                              : "memory");
 143         pci_poke_in_progress = 0;
 144         pci_poke_cpu = -1;
 145         spin_unlock_irqrestore(&pci_poke_lock, flags);
 146 }
 147
 148 void pci_config_write32(u32 *addr, u32 val)
 149 {
 150         unsigned long flags;
 151
 152         spin_lock_irqsave(&pci_poke_lock, flags);
 153         pci_poke_cpu = smp_processor_id();
 154         pci_poke_in_progress = 1;
 155         pci_poke_faulted = 0;
 156         __asm__ __volatile__("membar #Sync\n\t"
 157                              "stwa %0, [%1] %2\n\t"
 158                              "membar #Sync"
 159                              : /* no outputs */
 160                              : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
 161                              : "memory");
 162         pci_poke_in_progress = 0;
 163         pci_poke_cpu = -1;
 164         spin_unlock_irqrestore(&pci_poke_lock, flags);
 165 }
 166
 167 static int ofpci_verbose;
 168
 169 static int __init ofpci_debug(char *str)
 170 {
 171         int val = 0;
 172
 173         get_option(&str, &val);
 174         if (val)
 175                 ofpci_verbose = 1;
 176         return 1;
 177 }
 178
 179 __setup("ofpci_debug=", ofpci_debug);
 180
 181 static unsigned long pci_parse_of_flags(u32 addr0)
 182 {
 183         unsigned long flags = 0;
 184
 185         if (addr0 & 0x02000000) {
 186                 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
 187                 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
 188                 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
 189                 if (addr0 & 0x40000000)
 190                         flags |= IORESOURCE_PREFETCH
 191                                  | PCI_BASE_ADDRESS_MEM_PREFETCH;
 192         } else if (addr0 & 0x01000000)
 193                 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
 194         return flags;
 195 }
 196
 197 /* The of_device layer has translated all of the assigned-address properties
 198  * into physical address resources, we only have to figure out the register
 199  * mapping.
 200  */
 201 static void pci_parse_of_addrs(struct platform_device *op,
 202                                struct device_node *node,
 203                                struct pci_dev *dev)
 204 {
 205         struct resource *op_res;
 206         const u32 *addrs;
 207         int proplen;
 208
 209         addrs = of_get_property(node, "assigned-addresses", &proplen);
 210         if (!addrs)
 211                 return;
 212         if (ofpci_verbose)
 213                 printk("    parse addresses (%d bytes) @ %p\n",
 214                        proplen, addrs);
 215         op_res = &op->resource[0];
 216         for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) {
 217                 struct resource *res;
 218                 unsigned long flags;
 219                 int i;
 220
 221                 flags = pci_parse_of_flags(addrs[0]);
 222                 if (!flags)
 223                         continue;
 224                 i = addrs[0] & 0xff;
 225                 if (ofpci_verbose)
 226                         printk("  start: %llx, end: %llx, i: %x\n",
 227                                op_res->start, op_res->end, i);
 228
 229                 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
 230                         res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
 231                 } else if (i == dev->rom_base_reg) {
 232                         res = &dev->resource[PCI_ROM_RESOURCE];
 233                         flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE
 234                               | IORESOURCE_SIZEALIGN;
 235                 } else {
 236                         printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
 237                         continue;
 238                 }
 239                 res->start = op_res->start;
 240                 res->end = op_res->end;
 241                 res->flags = flags;
 242                 res->name = pci_name(dev);
 243         }
 244 }
 245
 246 static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
 247                                          struct device_node *node,
 248                                          struct pci_bus *bus, int devfn)
 249 {
 250         struct dev_archdata *sd;
 251         struct pci_slot *slot;
 252         struct platform_device *op;
 253         struct pci_dev *dev;
 254         const char *type;
 255         u32 class;
 256
 257         dev = pci_alloc_dev(bus);
 258         if (!dev)
 259                 return NULL;
 260
 261         sd = &dev->dev.archdata;
 262         sd->iommu = pbm->iommu;
 263         sd->stc = &pbm->stc;
 264         sd->host_controller = pbm;
 265         sd->op = op = of_find_device_by_node(node);
 266         sd->numa_node = pbm->numa_node;
 267
 268         sd = &op->dev.archdata;
 269         sd->iommu = pbm->iommu;
 270         sd->stc = &pbm->stc;
 271         sd->numa_node = pbm->numa_node;
 272
 273         if (!strcmp(node->name, "ebus"))
 274                 of_propagate_archdata(op);
 275
 276         type = of_get_property(node, "device_type", NULL);
 277         if (type == NULL)
 278                 type = "";
 279
 280         if (ofpci_verbose)
 281                 printk("    create device, devfn: %x, type: %s\n",
 282                        devfn, type);
 283
 284         dev->sysdata = node;
 285         dev->dev.parent = bus->bridge;
 286         dev->dev.bus = &pci_bus_type;
 287         dev->dev.of_node = of_node_get(node);
 288         dev->devfn = devfn;
 289         dev->multifunction = 0;         /* maybe a lie? */
 290         set_pcie_port_type(dev);
 291
 292         list_for_each_entry(slot, &dev->bus->slots, list)
 293                 if (PCI_SLOT(dev->devfn) == slot->number)
 294                         dev->slot = slot;
 295
 296         dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
 297         dev->device = of_getintprop_default(node, "device-id", 0xffff);
 298         dev->subsystem_vendor =
 299                 of_getintprop_default(node, "subsystem-vendor-id", 0);
 300         dev->subsystem_device =
 301                 of_getintprop_default(node, "subsystem-id", 0);
 302
 303         dev->cfg_size = pci_cfg_space_size(dev);
 304
 305         /* We can't actually use the firmware value, we have
 306          * to read what is in the register right now.  One
 307          * reason is that in the case of IDE interfaces the
 308          * firmware can sample the value before the the IDE
 309          * interface is programmed into native mode.
 310          */
 311         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
 312         dev->class = class >> 8;
 313         dev->revision = class & 0xff;
 314
 315         dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus),
 316                 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
 317
 318         if (ofpci_verbose)
 319                 printk("    class: 0x%x device name: %s\n",
 320                        dev->class, pci_name(dev));
 321
 322         /* I have seen IDE devices which will not respond to
 323          * the bmdma simplex check reads if bus mastering is
 324          * disabled.
 325          */
 326         if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
 327                 pci_set_master(dev);
 328
 329         dev->current_state = PCI_UNKNOWN;       /* unknown power state */
 330         dev->error_state = pci_channel_io_normal;
 331         dev->dma_mask = 0xffffffff;
 332
 333         if (!strcmp(node->name, "pci")) {
 334                 /* a PCI-PCI bridge */
 335                 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
 336                 dev->rom_base_reg = PCI_ROM_ADDRESS1;
 337         } else if (!strcmp(type, "cardbus")) {
 338                 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
 339         } else {
 340                 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
 341                 dev->rom_base_reg = PCI_ROM_ADDRESS;
 342
 343                 dev->irq = sd->op->archdata.irqs[0];
 344                 if (dev->irq == 0xffffffff)
 345                         dev->irq = PCI_IRQ_NONE;
 346         }
 347
 348         pci_parse_of_addrs(sd->op, node, dev);
 349
 350         if (ofpci_verbose)
 351                 printk("    adding to system ...\n");
 352
 353         pci_device_add(dev, bus);
 354
 355         return dev;
 356 }
 357
 358 static void apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p)
 359 {
 360         u32 idx, first, last;
 361
 362         first = 8;
 363         last = 0;
 364         for (idx = 0; idx < 8; idx++) {
 365                 if ((map & (1 << idx)) != 0) {
 366                         if (first > idx)
 367                                 first = idx;
 368                         if (last < idx)
 369                                 last = idx;
 370                 }
 371         }
 372
 373         *first_p = first;
 374         *last_p = last;
 375 }
 376
 377 /* Cook up fake bus resources for SUNW,simba PCI bridges which lack
 378  * a proper 'ranges' property.
 379  */
 380 static void apb_fake_ranges(struct pci_dev *dev,
 381                             struct pci_bus *bus,
 382                             struct pci_pbm_info *pbm)
 383 {
 384         struct pci_bus_region region;
 385         struct resource *res;
 386         u32 first, last;
 387         u8 map;
 388
 389         pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map);
 390         apb_calc_first_last(map, &first, &last);
 391         res = bus->resource[0];
 392         res->flags = IORESOURCE_IO;
 393         region.start = (first << 21);
 394         region.end = (last << 21) + ((1 << 21) - 1);
 395         pcibios_bus_to_resource(dev->bus, res, &region);
 396
 397         pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map);
 398         apb_calc_first_last(map, &first, &last);
 399         res = bus->resource[1];
 400         res->flags = IORESOURCE_MEM;
 401         region.start = (first << 29);
 402         region.end = (last << 29) + ((1 << 29) - 1);
 403         pcibios_bus_to_resource(dev->bus, res, &region);
 404 }
 405
 406 static void pci_of_scan_bus(struct pci_pbm_info *pbm,
 407                             struct device_node *node,
 408                             struct pci_bus *bus);
 409
 410 #define GET_64BIT(prop, i)      ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
 411
 412 static void of_scan_pci_bridge(struct pci_pbm_info *pbm,
 413                                struct device_node *node,
 414                                struct pci_dev *dev)
 415 {
 416         struct pci_bus *bus;
 417         const u32 *busrange, *ranges;
 418         int len, i, simba;
 419         struct pci_bus_region region;
 420         struct resource *res;
 421         unsigned int flags;
 422         u64 size;
 423
 424         if (ofpci_verbose)
 425                 printk("of_scan_pci_bridge(%s)\n", node->full_name);
 426
 427         /* parse bus-range property */
 428         busrange = of_get_property(node, "bus-range", &len);
 429         if (busrange == NULL || len != 8) {
 430                 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
 431                        node->full_name);
 432                 return;
 433         }
 434         ranges = of_get_property(node, "ranges", &len);
 435         simba = 0;
 436         if (ranges == NULL) {
 437                 const char *model = of_get_property(node, "model", NULL);
 438                 if (model && !strcmp(model, "SUNW,simba"))
 439                         simba = 1;
 440         }
 441
 442         bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
 443         if (!bus) {
 444                 printk(KERN_ERR "Failed to create pci bus for %s\n",
 445                        node->full_name);
 446                 return;
 447         }
 448
 449         bus->primary = dev->bus->number;
 450         pci_bus_insert_busn_res(bus, busrange[0], busrange[1]);
 451         bus->bridge_ctl = 0;
 452
 453         /* parse ranges property, or cook one up by hand for Simba */
 454         /* PCI #address-cells == 3 and #size-cells == 2 always */
 455         res = &dev->resource[PCI_BRIDGE_RESOURCES];
 456         for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
 457                 res->flags = 0;
 458                 bus->resource[i] = res;
 459                 ++res;
 460         }
 461         if (simba) {
 462                 apb_fake_ranges(dev, bus, pbm);
 463                 goto after_ranges;
 464         } else if (ranges == NULL) {
 465                 pci_read_bridge_bases(bus);
 466                 goto after_ranges;
 467         }
 468         i = 1;
 469         for (; len >= 32; len -= 32, ranges += 8) {
 470                 flags = pci_parse_of_flags(ranges[0]);
 471                 size = GET_64BIT(ranges, 6);
 472                 if (flags == 0 || size == 0)
 473                         continue;
 474                 if (flags & IORESOURCE_IO) {
 475                         res = bus->resource[0];
 476                         if (res->flags) {
 477                                 printk(KERN_ERR "PCI: ignoring extra I/O range"
 478                                        " for bridge %s\n", node->full_name);
 479                                 continue;
 480                         }
 481                 } else {
 482                         if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
 483                                 printk(KERN_ERR "PCI: too many memory ranges"
 484                                        " for bridge %s\n", node->full_name);
 485                                 continue;
 486                         }
 487                         res = bus->resource[i];
 488                         ++i;
 489                 }
 490
 491                 res->flags = flags;
 492                 region.start = GET_64BIT(ranges, 1);
 493                 region.end = region.start + size - 1;
 494                 pcibios_bus_to_resource(dev->bus, res, &region);
 495         }
 496 after_ranges:
 497         sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
 498                 bus->number);
 499         if (ofpci_verbose)
 500                 printk("    bus name: %s\n", bus->name);
 501
 502         pci_of_scan_bus(pbm, node, bus);
 503 }
 504
 505 static void pci_of_scan_bus(struct pci_pbm_info *pbm,
 506                             struct device_node *node,
 507                             struct pci_bus *bus)
 508 {
 509         struct device_node *child;
 510         const u32 *reg;
 511         int reglen, devfn, prev_devfn;
 512         struct pci_dev *dev;
 513
 514         if (ofpci_verbose)
 515                 printk("PCI: scan_bus[%s] bus no %d\n",
 516                        node->full_name, bus->number);
 517
 518         child = NULL;
 519         prev_devfn = -1;
 520         while ((child = of_get_next_child(node, child)) != NULL) {
 521                 if (ofpci_verbose)
 522                         printk("  * %s\n", child->full_name);
 523                 reg = of_get_property(child, "reg", &reglen);
 524                 if (reg == NULL || reglen < 20)
 525                         continue;
 526
 527                 devfn = (reg[0] >> 8) & 0xff;
 528
 529                 /* This is a workaround for some device trees
 530                  * which list PCI devices twice.  On the V100
 531                  * for example, device number 3 is listed twice.
 532                  * Once as "pm" and once again as "lomp".
 533                  */
 534                 if (devfn == prev_devfn)
 535                         continue;
 536                 prev_devfn = devfn;
 537
 538                 /* create a new pci_dev for this device */
 539                 dev = of_create_pci_dev(pbm, child, bus, devfn);
 540                 if (!dev)
 541                         continue;
 542                 if (ofpci_verbose)
 543                         printk("PCI: dev header type: %x\n",
 544                                dev->hdr_type);
 545
 546                 if (pci_is_bridge(dev))
 547                         of_scan_pci_bridge(pbm, child, dev);
 548         }
 549 }
 550
 551 static ssize_t
 552 show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf)
 553 {
 554         struct pci_dev *pdev;
 555         struct device_node *dp;
 556
 557         pdev = to_pci_dev(dev);
 558         dp = pdev->dev.of_node;
 559
 560         return snprintf (buf, PAGE_SIZE, "%s\n", dp->full_name);
 561 }
 562
 563 static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL);
 564
 565 static void pci_bus_register_of_sysfs(struct pci_bus *bus)
 566 {
 567         struct pci_dev *dev;
 568         struct pci_bus *child_bus;
 569         int err;
 570
 571         list_for_each_entry(dev, &bus->devices, bus_list) {
 572                 /* we don't really care if we can create this file or
 573                  * not, but we need to assign the result of the call
 574                  * or the world will fall under alien invasion and
 575                  * everybody will be frozen on a spaceship ready to be
 576                  * eaten on alpha centauri by some green and jelly
 577                  * humanoid.
 578                  */
 579                 err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr);
 580                 (void) err;
 581         }
 582         list_for_each_entry(child_bus, &bus->children, node)
 583                 pci_bus_register_of_sysfs(child_bus);
 584 }
 585
 586 struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm,
 587                                  struct device *parent)
 588 {
 589         LIST_HEAD(resources);
 590         struct device_node *node = pbm->op->dev.of_node;
 591         struct pci_bus *bus;
 592
 593         printk("PCI: Scanning PBM %s\n", node->full_name);
 594
 595         pci_add_resource_offset(&resources, &pbm->io_space,
 596                                 pbm->io_space.start);
 597         pci_add_resource_offset(&resources, &pbm->mem_space,
 598                                 pbm->mem_space.start);
 599         pbm->busn.start = pbm->pci_first_busno;
 600         pbm->busn.end   = pbm->pci_last_busno;
 601         pbm->busn.flags = IORESOURCE_BUS;
 602         pci_add_resource(&resources, &pbm->busn);
 603         bus = pci_create_root_bus(parent, pbm->pci_first_busno, pbm->pci_ops,
 604                                   pbm, &resources);
 605         if (!bus) {
 606                 printk(KERN_ERR "Failed to create bus for %s\n",
 607                        node->full_name);
 608                 pci_free_resource_list(&resources);
 609                 return NULL;
 610         }
 611
 612         pci_of_scan_bus(pbm, node, bus);
 613         pci_bus_add_devices(bus);
 614         pci_bus_register_of_sysfs(bus);
 615
 616         return bus;
 617 }
 618
 619 void pcibios_fixup_bus(struct pci_bus *pbus)
 620 {
 621 }
 622
 623 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
 624                                 resource_size_t size, resource_size_t align)
 625 {
 626         return res->start;
 627 }
 628
 629 int pcibios_enable_device(struct pci_dev *dev, int mask)
 630 {
 631         u16 cmd, oldcmd;
 632         int i;
 633
 634         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 635         oldcmd = cmd;
 636
 637         for (i = 0; i < PCI_NUM_RESOURCES; i++) {
 638                 struct resource *res = &dev->resource[i];
 639
 640                 /* Only set up the requested stuff */
 641                 if (!(mask & (1<<i)))
 642                         continue;
 643
 644                 if (res->flags & IORESOURCE_IO)
 645                         cmd |= PCI_COMMAND_IO;
 646                 if (res->flags & IORESOURCE_MEM)
 647                         cmd |= PCI_COMMAND_MEMORY;
 648         }
 649
 650         if (cmd != oldcmd) {
 651                 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
 652                        pci_name(dev), cmd);
 653                 /* Enable the appropriate bits in the PCI command register.  */
 654                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 655         }
 656         return 0;
 657 }
 658
 659 /* Platform support for /proc/bus/pci/X/Y mmap()s. */
 660
 661 /* If the user uses a host-bridge as the PCI device, he may use
 662  * this to perform a raw mmap() of the I/O or MEM space behind
 663  * that controller.
 664  *
 665  * This can be useful for execution of x86 PCI bios initialization code
 666  * on a PCI card, like the xfree86 int10 stuff does.
 667  */
 668 static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma,
 669                                       enum pci_mmap_state mmap_state)
 670 {
 671         struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
 672         unsigned long space_size, user_offset, user_size;
 673
 674         if (mmap_state == pci_mmap_io) {
 675                 space_size = resource_size(&pbm->io_space);
 676         } else {
 677                 space_size = resource_size(&pbm->mem_space);
 678         }
 679
 680         /* Make sure the request is in range. */
 681         user_offset = vma->vm_pgoff << PAGE_SHIFT;
 682         user_size = vma->vm_end - vma->vm_start;
 683
 684         if (user_offset >= space_size ||
 685             (user_offset + user_size) > space_size)
 686                 return -EINVAL;
 687
 688         if (mmap_state == pci_mmap_io) {
 689                 vma->vm_pgoff = (pbm->io_space.start +
 690                                  user_offset) >> PAGE_SHIFT;
 691         } else {
 692                 vma->vm_pgoff = (pbm->mem_space.start +
 693                                  user_offset) >> PAGE_SHIFT;
 694         }
 695
 696         return 0;
 697 }
 698
 699 /* Adjust vm_pgoff of VMA such that it is the physical page offset
 700  * corresponding to the 32-bit pci bus offset for DEV requested by the user.
 701  *
 702  * Basically, the user finds the base address for his device which he wishes
 703  * to mmap.  They read the 32-bit value from the config space base register,
 704  * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
 705  * offset parameter of mmap on /proc/bus/pci/XXX for that device.
 706  *
 707  * Returns negative error code on failure, zero on success.
 708  */
 709 static int __pci_mmap_make_offset(struct pci_dev *pdev,
 710                                   struct vm_area_struct *vma,
 711                                   enum pci_mmap_state mmap_state)
 712 {
 713         unsigned long user_paddr, user_size;
 714         int i, err;
 715
 716         /* First compute the physical address in vma->vm_pgoff,
 717          * making sure the user offset is within range in the
 718          * appropriate PCI space.
 719          */
 720         err = __pci_mmap_make_offset_bus(pdev, vma, mmap_state);
 721         if (err)
 722                 return err;
 723
 724         /* If this is a mapping on a host bridge, any address
 725          * is OK.
 726          */
 727         if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
 728                 return err;
 729
 730         /* Otherwise make sure it's in the range for one of the
 731          * device's resources.
 732          */
 733         user_paddr = vma->vm_pgoff << PAGE_SHIFT;
 734         user_size = vma->vm_end - vma->vm_start;
 735
 736         for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
 737                 struct resource *rp = &pdev->resource[i];
 738                 resource_size_t aligned_end;
 739
 740                 /* Active? */
 741                 if (!rp->flags)
 742                         continue;
 743
 744                 /* Same type? */
 745                 if (i == PCI_ROM_RESOURCE) {
 746                         if (mmap_state != pci_mmap_mem)
 747                                 continue;
 748                 } else {
 749                         if ((mmap_state == pci_mmap_io &&
 750                              (rp->flags & IORESOURCE_IO) == 0) ||
 751                             (mmap_state == pci_mmap_mem &&
 752                              (rp->flags & IORESOURCE_MEM) == 0))
 753                                 continue;
 754                 }
 755
 756                 /* Align the resource end to the next page address.
 757                  * PAGE_SIZE intentionally added instead of (PAGE_SIZE - 1),
 758                  * because actually we need the address of the next byte
 759                  * after rp->end.
 760                  */
 761                 aligned_end = (rp->end + PAGE_SIZE) & PAGE_MASK;
 762
 763                 if ((rp->start <= user_paddr) &&
 764                     (user_paddr + user_size) <= aligned_end)
 765                         break;
 766         }
 767
 768         if (i > PCI_ROM_RESOURCE)
 769                 return -EINVAL;
 770
 771         return 0;
 772 }
 773
 774 /* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
 775  * device mapping.
 776  */
 777 static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
 778                                              enum pci_mmap_state mmap_state)
 779 {
 780         /* Our io_remap_pfn_range takes care of this, do nothing.  */
 781 }
 782
 783 /* Perform the actual remap of the pages for a PCI device mapping, as appropriate
 784  * for this architecture.  The region in the process to map is described by vm_start
 785  * and vm_end members of VMA, the base physical address is found in vm_pgoff.
 786  * The pci device structure is provided so that architectures may make mapping
 787  * decisions on a per-device or per-bus basis.
 788  *
 789  * Returns a negative error code on failure, zero on success.
 790  */
 791 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
 792                         enum pci_mmap_state mmap_state,
 793                         int write_combine)
 794 {
 795         int ret;
 796
 797         ret = __pci_mmap_make_offset(dev, vma, mmap_state);
 798         if (ret < 0)
 799                 return ret;
 800
 801         __pci_mmap_set_pgprot(dev, vma, mmap_state);
 802
 803         vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
 804         ret = io_remap_pfn_range(vma, vma->vm_start,
 805                                  vma->vm_pgoff,
 806                                  vma->vm_end - vma->vm_start,
 807                                  vma->vm_page_prot);
 808         if (ret)
 809                 return ret;
 810
 811         return 0;
 812 }
 813
 814 #ifdef CONFIG_NUMA
 815 int pcibus_to_node(struct pci_bus *pbus)
 816 {
 817         struct pci_pbm_info *pbm = pbus->sysdata;
 818
 819         return pbm->numa_node;
 820 }
 821 EXPORT_SYMBOL(pcibus_to_node);
 822 #endif
 823
 824 /* Return the domain number for this pci bus */
 825
 826 int pci_domain_nr(struct pci_bus *pbus)
 827 {
 828         struct pci_pbm_info *pbm = pbus->sysdata;
 829         int ret;
 830
 831         if (!pbm) {
 832                 ret = -ENXIO;
 833         } else {
 834                 ret = pbm->index;
 835         }
 836
 837         return ret;
 838 }
 839 EXPORT_SYMBOL(pci_domain_nr);
 840
 841 #ifdef CONFIG_PCI_MSI
 842 int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
 843 {
 844         struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
 845         unsigned int irq;
 846
 847         if (!pbm->setup_msi_irq)
 848                 return -EINVAL;
 849
 850         return pbm->setup_msi_irq(&irq, pdev, desc);
 851 }
 852
 853 void arch_teardown_msi_irq(unsigned int irq)
 854 {
 855         struct msi_desc *entry = irq_get_msi_desc(irq);
 856         struct pci_dev *pdev = entry->dev;
 857         struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
 858
 859         if (pbm->teardown_msi_irq)
 860                 pbm->teardown_msi_irq(irq, pdev);
 861 }
 862 #endif /* !(CONFIG_PCI_MSI) */
 863
 864 static void ali_sound_dma_hack(struct pci_dev *pdev, int set_bit)
 865 {
 866         struct pci_dev *ali_isa_bridge;
 867         u8 val;
 868
 869         /* ALI sound chips generate 31-bits of DMA, a special register
 870          * determines what bit 31 is emitted as.
 871          */
 872         ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL,
 873                                          PCI_DEVICE_ID_AL_M1533,
 874                                          NULL);
 875
 876         pci_read_config_byte(ali_isa_bridge, 0x7e, &val);
 877         if (set_bit)
 878                 val |= 0x01;
 879         else
 880                 val &= ~0x01;
 881         pci_write_config_byte(ali_isa_bridge, 0x7e, val);
 882         pci_dev_put(ali_isa_bridge);
 883 }
 884
 885 int pci64_dma_supported(struct pci_dev *pdev, u64 device_mask)
 886 {
 887         u64 dma_addr_mask;
 888
 889         if (pdev == NULL) {
 890                 dma_addr_mask = 0xffffffff;
 891         } else {
 892                 struct iommu *iommu = pdev->dev.archdata.iommu;
 893
 894                 dma_addr_mask = iommu->dma_addr_mask;
 895
 896                 if (pdev->vendor == PCI_VENDOR_ID_AL &&
 897                     pdev->device == PCI_DEVICE_ID_AL_M5451 &&
 898                     device_mask == 0x7fffffff) {
 899                         ali_sound_dma_hack(pdev,
 900                                            (dma_addr_mask & 0x80000000) != 0);
 901                         return 1;
 902                 }
 903         }
 904
 905         if (device_mask >= (1UL << 32UL))
 906                 return 0;
 907
 908         return (device_mask & dma_addr_mask) == dma_addr_mask;
 909 }
 910
 911 void pci_resource_to_user(const struct pci_dev *pdev, int bar,
 912                           const struct resource *rp, resource_size_t *start,
 913                           resource_size_t *end)
 914 {
 915         struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
 916         unsigned long offset;
 917
 918         if (rp->flags & IORESOURCE_IO)
 919                 offset = pbm->io_space.start;
 920         else
 921                 offset = pbm->mem_space.start;
 922
 923         *start = rp->start - offset;
 924         *end = rp->end - offset;
 925 }
 926
 927 void pcibios_set_master(struct pci_dev *dev)
 928 {
 929         /* No special bus mastering setup handling */
 930 }
 931
 932 static int __init pcibios_init(void)
 933 {
 934         pci_dfl_cache_line_size = 64 >> 2;
 935         return 0;
 936 }
 937 subsys_initcall(pcibios_init);
 938
 939 #ifdef CONFIG_SYSFS
 940 static void pci_bus_slot_names(struct device_node *node, struct pci_bus *bus)
 941 {
 942         const struct pci_slot_names {
 943                 u32     slot_mask;
 944                 char    names[0];
 945         } *prop;
 946         const char *sp;
 947         int len, i;
 948         u32 mask;
 949
 950         prop = of_get_property(node, "slot-names", &len);
 951         if (!prop)
 952                 return;
 953
 954         mask = prop->slot_mask;
 955         sp = prop->names;
 956
 957         if (ofpci_verbose)
 958                 printk("PCI: Making slots for [%s] mask[0x%02x]\n",
 959                        node->full_name, mask);
 960
 961         i = 0;
 962         while (mask) {
 963                 struct pci_slot *pci_slot;
 964                 u32 this_bit = 1 << i;
 965
 966                 if (!(mask & this_bit)) {
 967                         i++;
 968                         continue;
 969                 }
 970
 971                 if (ofpci_verbose)
 972                         printk("PCI: Making slot [%s]\n", sp);
 973
 974                 pci_slot = pci_create_slot(bus, i, sp, NULL);
 975                 if (IS_ERR(pci_slot))
 976                         printk(KERN_ERR "PCI: pci_create_slot returned %ld\n",
 977                                PTR_ERR(pci_slot));
 978
 979                 sp += strlen(sp) + 1;
 980                 mask &= ~this_bit;
 981                 i++;
 982         }
 983 }
 984
 985 static int __init of_pci_slot_init(void)
 986 {
 987         struct pci_bus *pbus = NULL;
 988
 989         while ((pbus = pci_find_next_bus(pbus)) != NULL) {
 990                 struct device_node *node;
 991
 992                 if (pbus->self) {
 993                         /* PCI->PCI bridge */
 994                         node = pbus->self->dev.of_node;
 995                 } else {
 996                         struct pci_pbm_info *pbm = pbus->sysdata;
 997
 998                         /* Host PCI controller */
 999                         node = pbm->op->dev.of_node;
1000                 }
1001
1002                 pci_bus_slot_names(node, pbus);
1003         }
1004
1005         return 0;
1006 }
1007 device_initcall(of_pci_slot_init);
1008 #endif