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Merge branch 'ras-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-focal-kernel.git] / arch / sparc / kernel / pci_schizo.c
1 // SPDX-License-Identifier: GPL-2.0
2 /* pci_schizo.c: SCHIZO/TOMATILLO specific PCI controller support.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2007, 2008 David S. Miller (davem@davemloft.net)
5 */
6
7 #include <linux/kernel.h>
8 #include <linux/types.h>
9 #include <linux/pci.h>
10 #include <linux/init.h>
11 #include <linux/slab.h>
12 #include <linux/export.h>
13 #include <linux/interrupt.h>
14 #include <linux/of_device.h>
15
16 #include <asm/iommu.h>
17 #include <asm/irq.h>
18 #include <asm/pstate.h>
19 #include <asm/prom.h>
20 #include <asm/upa.h>
21
22 #include "pci_impl.h"
23 #include "iommu_common.h"
24
25 #define DRIVER_NAME "schizo"
26 #define PFX DRIVER_NAME ": "
27
28 /* This is a convention that at least Excalibur and Merlin
29 * follow. I suppose the SCHIZO used in Starcat and friends
30 * will do similar.
31 *
32 * The only way I could see this changing is if the newlink
33 * block requires more space in Schizo's address space than
34 * they predicted, thus requiring an address space reorg when
35 * the newer Schizo is taped out.
36 */
37
38 /* Streaming buffer control register. */
39 #define SCHIZO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */
40 #define SCHIZO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */
41 #define SCHIZO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */
42 #define SCHIZO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */
43 #define SCHIZO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */
44
45 /* IOMMU control register. */
46 #define SCHIZO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */
47 #define SCHIZO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */
48 #define SCHIZO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */
49 #define SCHIZO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */
50 #define SCHIZO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */
51 #define SCHIZO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */
52 #define SCHIZO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
53 #define SCHIZO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
54 #define SCHIZO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
55 #define SCHIZO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
56 #define SCHIZO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
57 #define SCHIZO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */
58 #define SCHIZO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */
59 #define SCHIZO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */
60 #define SCHIZO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */
61 #define SCHIZO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */
62 #define SCHIZO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */
63 #define SCHIZO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */
64
65 /* Schizo config space address format is nearly identical to
66 * that of PSYCHO:
67 *
68 * 32 24 23 16 15 11 10 8 7 2 1 0
69 * ---------------------------------------------------------
70 * |0 0 0 0 0 0 0 0 0| bus | device | function | reg | 0 0 |
71 * ---------------------------------------------------------
72 */
73 #define SCHIZO_CONFIG_BASE(PBM) ((PBM)->config_space)
74 #define SCHIZO_CONFIG_ENCODE(BUS, DEVFN, REG) \
75 (((unsigned long)(BUS) << 16) | \
76 ((unsigned long)(DEVFN) << 8) | \
77 ((unsigned long)(REG)))
78
79 static void *schizo_pci_config_mkaddr(struct pci_pbm_info *pbm,
80 unsigned char bus,
81 unsigned int devfn,
82 int where)
83 {
84 if (!pbm)
85 return NULL;
86 bus -= pbm->pci_first_busno;
87 return (void *)
88 (SCHIZO_CONFIG_BASE(pbm) |
89 SCHIZO_CONFIG_ENCODE(bus, devfn, where));
90 }
91
92 /* SCHIZO error handling support. */
93 enum schizo_error_type {
94 UE_ERR, CE_ERR, PCI_ERR, SAFARI_ERR
95 };
96
97 static DEFINE_SPINLOCK(stc_buf_lock);
98 static unsigned long stc_error_buf[128];
99 static unsigned long stc_tag_buf[16];
100 static unsigned long stc_line_buf[16];
101
102 #define SCHIZO_UE_INO 0x30 /* Uncorrectable ECC error */
103 #define SCHIZO_CE_INO 0x31 /* Correctable ECC error */
104 #define SCHIZO_PCIERR_A_INO 0x32 /* PBM A PCI bus error */
105 #define SCHIZO_PCIERR_B_INO 0x33 /* PBM B PCI bus error */
106 #define SCHIZO_SERR_INO 0x34 /* Safari interface error */
107
108 #define SCHIZO_STC_ERR 0xb800UL /* --> 0xba00 */
109 #define SCHIZO_STC_TAG 0xba00UL /* --> 0xba80 */
110 #define SCHIZO_STC_LINE 0xbb00UL /* --> 0xbb80 */
111
112 #define SCHIZO_STCERR_WRITE 0x2UL
113 #define SCHIZO_STCERR_READ 0x1UL
114
115 #define SCHIZO_STCTAG_PPN 0x3fffffff00000000UL
116 #define SCHIZO_STCTAG_VPN 0x00000000ffffe000UL
117 #define SCHIZO_STCTAG_VALID 0x8000000000000000UL
118 #define SCHIZO_STCTAG_READ 0x4000000000000000UL
119
120 #define SCHIZO_STCLINE_LINDX 0x0000000007800000UL
121 #define SCHIZO_STCLINE_SPTR 0x000000000007e000UL
122 #define SCHIZO_STCLINE_LADDR 0x0000000000001fc0UL
123 #define SCHIZO_STCLINE_EPTR 0x000000000000003fUL
124 #define SCHIZO_STCLINE_VALID 0x0000000000600000UL
125 #define SCHIZO_STCLINE_FOFN 0x0000000000180000UL
126
127 static void __schizo_check_stc_error_pbm(struct pci_pbm_info *pbm,
128 enum schizo_error_type type)
129 {
130 struct strbuf *strbuf = &pbm->stc;
131 unsigned long regbase = pbm->pbm_regs;
132 unsigned long err_base, tag_base, line_base;
133 u64 control;
134 int i;
135
136 err_base = regbase + SCHIZO_STC_ERR;
137 tag_base = regbase + SCHIZO_STC_TAG;
138 line_base = regbase + SCHIZO_STC_LINE;
139
140 spin_lock(&stc_buf_lock);
141
142 /* This is __REALLY__ dangerous. When we put the
143 * streaming buffer into diagnostic mode to probe
144 * it's tags and error status, we _must_ clear all
145 * of the line tag valid bits before re-enabling
146 * the streaming buffer. If any dirty data lives
147 * in the STC when we do this, we will end up
148 * invalidating it before it has a chance to reach
149 * main memory.
150 */
151 control = upa_readq(strbuf->strbuf_control);
152 upa_writeq((control | SCHIZO_STRBUF_CTRL_DENAB),
153 strbuf->strbuf_control);
154 for (i = 0; i < 128; i++) {
155 unsigned long val;
156
157 val = upa_readq(err_base + (i * 8UL));
158 upa_writeq(0UL, err_base + (i * 8UL));
159 stc_error_buf[i] = val;
160 }
161 for (i = 0; i < 16; i++) {
162 stc_tag_buf[i] = upa_readq(tag_base + (i * 8UL));
163 stc_line_buf[i] = upa_readq(line_base + (i * 8UL));
164 upa_writeq(0UL, tag_base + (i * 8UL));
165 upa_writeq(0UL, line_base + (i * 8UL));
166 }
167
168 /* OK, state is logged, exit diagnostic mode. */
169 upa_writeq(control, strbuf->strbuf_control);
170
171 for (i = 0; i < 16; i++) {
172 int j, saw_error, first, last;
173
174 saw_error = 0;
175 first = i * 8;
176 last = first + 8;
177 for (j = first; j < last; j++) {
178 unsigned long errval = stc_error_buf[j];
179 if (errval != 0) {
180 saw_error++;
181 printk("%s: STC_ERR(%d)[wr(%d)rd(%d)]\n",
182 pbm->name,
183 j,
184 (errval & SCHIZO_STCERR_WRITE) ? 1 : 0,
185 (errval & SCHIZO_STCERR_READ) ? 1 : 0);
186 }
187 }
188 if (saw_error != 0) {
189 unsigned long tagval = stc_tag_buf[i];
190 unsigned long lineval = stc_line_buf[i];
191 printk("%s: STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)R(%d)]\n",
192 pbm->name,
193 i,
194 ((tagval & SCHIZO_STCTAG_PPN) >> 19UL),
195 (tagval & SCHIZO_STCTAG_VPN),
196 ((tagval & SCHIZO_STCTAG_VALID) ? 1 : 0),
197 ((tagval & SCHIZO_STCTAG_READ) ? 1 : 0));
198
199 /* XXX Should spit out per-bank error information... -DaveM */
200 printk("%s: STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)"
201 "V(%d)FOFN(%d)]\n",
202 pbm->name,
203 i,
204 ((lineval & SCHIZO_STCLINE_LINDX) >> 23UL),
205 ((lineval & SCHIZO_STCLINE_SPTR) >> 13UL),
206 ((lineval & SCHIZO_STCLINE_LADDR) >> 6UL),
207 ((lineval & SCHIZO_STCLINE_EPTR) >> 0UL),
208 ((lineval & SCHIZO_STCLINE_VALID) ? 1 : 0),
209 ((lineval & SCHIZO_STCLINE_FOFN) ? 1 : 0));
210 }
211 }
212
213 spin_unlock(&stc_buf_lock);
214 }
215
216 /* IOMMU is per-PBM in Schizo, so interrogate both for anonymous
217 * controller level errors.
218 */
219
220 #define SCHIZO_IOMMU_TAG 0xa580UL
221 #define SCHIZO_IOMMU_DATA 0xa600UL
222
223 #define SCHIZO_IOMMU_TAG_CTXT 0x0000001ffe000000UL
224 #define SCHIZO_IOMMU_TAG_ERRSTS 0x0000000001800000UL
225 #define SCHIZO_IOMMU_TAG_ERR 0x0000000000400000UL
226 #define SCHIZO_IOMMU_TAG_WRITE 0x0000000000200000UL
227 #define SCHIZO_IOMMU_TAG_STREAM 0x0000000000100000UL
228 #define SCHIZO_IOMMU_TAG_SIZE 0x0000000000080000UL
229 #define SCHIZO_IOMMU_TAG_VPAGE 0x000000000007ffffUL
230
231 #define SCHIZO_IOMMU_DATA_VALID 0x0000000100000000UL
232 #define SCHIZO_IOMMU_DATA_CACHE 0x0000000040000000UL
233 #define SCHIZO_IOMMU_DATA_PPAGE 0x000000003fffffffUL
234
235 static void schizo_check_iommu_error_pbm(struct pci_pbm_info *pbm,
236 enum schizo_error_type type)
237 {
238 struct iommu *iommu = pbm->iommu;
239 unsigned long iommu_tag[16];
240 unsigned long iommu_data[16];
241 unsigned long flags;
242 u64 control;
243 int i;
244
245 spin_lock_irqsave(&iommu->lock, flags);
246 control = upa_readq(iommu->iommu_control);
247 if (control & SCHIZO_IOMMU_CTRL_XLTEERR) {
248 unsigned long base;
249 char *type_string;
250
251 /* Clear the error encountered bit. */
252 control &= ~SCHIZO_IOMMU_CTRL_XLTEERR;
253 upa_writeq(control, iommu->iommu_control);
254
255 switch((control & SCHIZO_IOMMU_CTRL_XLTESTAT) >> 25UL) {
256 case 0:
257 type_string = "Protection Error";
258 break;
259 case 1:
260 type_string = "Invalid Error";
261 break;
262 case 2:
263 type_string = "TimeOut Error";
264 break;
265 case 3:
266 default:
267 type_string = "ECC Error";
268 break;
269 }
270 printk("%s: IOMMU Error, type[%s]\n",
271 pbm->name, type_string);
272
273 /* Put the IOMMU into diagnostic mode and probe
274 * it's TLB for entries with error status.
275 *
276 * It is very possible for another DVMA to occur
277 * while we do this probe, and corrupt the system
278 * further. But we are so screwed at this point
279 * that we are likely to crash hard anyways, so
280 * get as much diagnostic information to the
281 * console as we can.
282 */
283 upa_writeq(control | SCHIZO_IOMMU_CTRL_DENAB,
284 iommu->iommu_control);
285
286 base = pbm->pbm_regs;
287
288 for (i = 0; i < 16; i++) {
289 iommu_tag[i] =
290 upa_readq(base + SCHIZO_IOMMU_TAG + (i * 8UL));
291 iommu_data[i] =
292 upa_readq(base + SCHIZO_IOMMU_DATA + (i * 8UL));
293
294 /* Now clear out the entry. */
295 upa_writeq(0, base + SCHIZO_IOMMU_TAG + (i * 8UL));
296 upa_writeq(0, base + SCHIZO_IOMMU_DATA + (i * 8UL));
297 }
298
299 /* Leave diagnostic mode. */
300 upa_writeq(control, iommu->iommu_control);
301
302 for (i = 0; i < 16; i++) {
303 unsigned long tag, data;
304
305 tag = iommu_tag[i];
306 if (!(tag & SCHIZO_IOMMU_TAG_ERR))
307 continue;
308
309 data = iommu_data[i];
310 switch((tag & SCHIZO_IOMMU_TAG_ERRSTS) >> 23UL) {
311 case 0:
312 type_string = "Protection Error";
313 break;
314 case 1:
315 type_string = "Invalid Error";
316 break;
317 case 2:
318 type_string = "TimeOut Error";
319 break;
320 case 3:
321 default:
322 type_string = "ECC Error";
323 break;
324 }
325 printk("%s: IOMMU TAG(%d)[error(%s) ctx(%x) wr(%d) str(%d) "
326 "sz(%dK) vpg(%08lx)]\n",
327 pbm->name, i, type_string,
328 (int)((tag & SCHIZO_IOMMU_TAG_CTXT) >> 25UL),
329 ((tag & SCHIZO_IOMMU_TAG_WRITE) ? 1 : 0),
330 ((tag & SCHIZO_IOMMU_TAG_STREAM) ? 1 : 0),
331 ((tag & SCHIZO_IOMMU_TAG_SIZE) ? 64 : 8),
332 (tag & SCHIZO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT);
333 printk("%s: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n",
334 pbm->name, i,
335 ((data & SCHIZO_IOMMU_DATA_VALID) ? 1 : 0),
336 ((data & SCHIZO_IOMMU_DATA_CACHE) ? 1 : 0),
337 (data & SCHIZO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT);
338 }
339 }
340 if (pbm->stc.strbuf_enabled)
341 __schizo_check_stc_error_pbm(pbm, type);
342 spin_unlock_irqrestore(&iommu->lock, flags);
343 }
344
345 static void schizo_check_iommu_error(struct pci_pbm_info *pbm,
346 enum schizo_error_type type)
347 {
348 schizo_check_iommu_error_pbm(pbm, type);
349 if (pbm->sibling)
350 schizo_check_iommu_error_pbm(pbm->sibling, type);
351 }
352
353 /* Uncorrectable ECC error status gathering. */
354 #define SCHIZO_UE_AFSR 0x10030UL
355 #define SCHIZO_UE_AFAR 0x10038UL
356
357 #define SCHIZO_UEAFSR_PPIO 0x8000000000000000UL /* Safari */
358 #define SCHIZO_UEAFSR_PDRD 0x4000000000000000UL /* Safari/Tomatillo */
359 #define SCHIZO_UEAFSR_PDWR 0x2000000000000000UL /* Safari */
360 #define SCHIZO_UEAFSR_SPIO 0x1000000000000000UL /* Safari */
361 #define SCHIZO_UEAFSR_SDMA 0x0800000000000000UL /* Safari/Tomatillo */
362 #define SCHIZO_UEAFSR_ERRPNDG 0x0300000000000000UL /* Safari */
363 #define SCHIZO_UEAFSR_BMSK 0x000003ff00000000UL /* Safari */
364 #define SCHIZO_UEAFSR_QOFF 0x00000000c0000000UL /* Safari/Tomatillo */
365 #define SCHIZO_UEAFSR_AID 0x000000001f000000UL /* Safari/Tomatillo */
366 #define SCHIZO_UEAFSR_PARTIAL 0x0000000000800000UL /* Safari */
367 #define SCHIZO_UEAFSR_OWNEDIN 0x0000000000400000UL /* Safari */
368 #define SCHIZO_UEAFSR_MTAGSYND 0x00000000000f0000UL /* Safari */
369 #define SCHIZO_UEAFSR_MTAG 0x000000000000e000UL /* Safari */
370 #define SCHIZO_UEAFSR_ECCSYND 0x00000000000001ffUL /* Safari */
371
372 static irqreturn_t schizo_ue_intr(int irq, void *dev_id)
373 {
374 struct pci_pbm_info *pbm = dev_id;
375 unsigned long afsr_reg = pbm->controller_regs + SCHIZO_UE_AFSR;
376 unsigned long afar_reg = pbm->controller_regs + SCHIZO_UE_AFAR;
377 unsigned long afsr, afar, error_bits;
378 int reported, limit;
379
380 /* Latch uncorrectable error status. */
381 afar = upa_readq(afar_reg);
382
383 /* If either of the error pending bits are set in the
384 * AFSR, the error status is being actively updated by
385 * the hardware and we must re-read to get a clean value.
386 */
387 limit = 1000;
388 do {
389 afsr = upa_readq(afsr_reg);
390 } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit);
391
392 /* Clear the primary/secondary error status bits. */
393 error_bits = afsr &
394 (SCHIZO_UEAFSR_PPIO | SCHIZO_UEAFSR_PDRD | SCHIZO_UEAFSR_PDWR |
395 SCHIZO_UEAFSR_SPIO | SCHIZO_UEAFSR_SDMA);
396 if (!error_bits)
397 return IRQ_NONE;
398 upa_writeq(error_bits, afsr_reg);
399
400 /* Log the error. */
401 printk("%s: Uncorrectable Error, primary error type[%s]\n",
402 pbm->name,
403 (((error_bits & SCHIZO_UEAFSR_PPIO) ?
404 "PIO" :
405 ((error_bits & SCHIZO_UEAFSR_PDRD) ?
406 "DMA Read" :
407 ((error_bits & SCHIZO_UEAFSR_PDWR) ?
408 "DMA Write" : "???")))));
409 printk("%s: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n",
410 pbm->name,
411 (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL,
412 (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL,
413 (afsr & SCHIZO_UEAFSR_AID) >> 24UL);
414 printk("%s: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n",
415 pbm->name,
416 (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0,
417 (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0,
418 (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL,
419 (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL,
420 (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL);
421 printk("%s: UE AFAR [%016lx]\n", pbm->name, afar);
422 printk("%s: UE Secondary errors [", pbm->name);
423 reported = 0;
424 if (afsr & SCHIZO_UEAFSR_SPIO) {
425 reported++;
426 printk("(PIO)");
427 }
428 if (afsr & SCHIZO_UEAFSR_SDMA) {
429 reported++;
430 printk("(DMA)");
431 }
432 if (!reported)
433 printk("(none)");
434 printk("]\n");
435
436 /* Interrogate IOMMU for error status. */
437 schizo_check_iommu_error(pbm, UE_ERR);
438
439 return IRQ_HANDLED;
440 }
441
442 #define SCHIZO_CE_AFSR 0x10040UL
443 #define SCHIZO_CE_AFAR 0x10048UL
444
445 #define SCHIZO_CEAFSR_PPIO 0x8000000000000000UL
446 #define SCHIZO_CEAFSR_PDRD 0x4000000000000000UL
447 #define SCHIZO_CEAFSR_PDWR 0x2000000000000000UL
448 #define SCHIZO_CEAFSR_SPIO 0x1000000000000000UL
449 #define SCHIZO_CEAFSR_SDMA 0x0800000000000000UL
450 #define SCHIZO_CEAFSR_ERRPNDG 0x0300000000000000UL
451 #define SCHIZO_CEAFSR_BMSK 0x000003ff00000000UL
452 #define SCHIZO_CEAFSR_QOFF 0x00000000c0000000UL
453 #define SCHIZO_CEAFSR_AID 0x000000001f000000UL
454 #define SCHIZO_CEAFSR_PARTIAL 0x0000000000800000UL
455 #define SCHIZO_CEAFSR_OWNEDIN 0x0000000000400000UL
456 #define SCHIZO_CEAFSR_MTAGSYND 0x00000000000f0000UL
457 #define SCHIZO_CEAFSR_MTAG 0x000000000000e000UL
458 #define SCHIZO_CEAFSR_ECCSYND 0x00000000000001ffUL
459
460 static irqreturn_t schizo_ce_intr(int irq, void *dev_id)
461 {
462 struct pci_pbm_info *pbm = dev_id;
463 unsigned long afsr_reg = pbm->controller_regs + SCHIZO_CE_AFSR;
464 unsigned long afar_reg = pbm->controller_regs + SCHIZO_CE_AFAR;
465 unsigned long afsr, afar, error_bits;
466 int reported, limit;
467
468 /* Latch error status. */
469 afar = upa_readq(afar_reg);
470
471 /* If either of the error pending bits are set in the
472 * AFSR, the error status is being actively updated by
473 * the hardware and we must re-read to get a clean value.
474 */
475 limit = 1000;
476 do {
477 afsr = upa_readq(afsr_reg);
478 } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit);
479
480 /* Clear primary/secondary error status bits. */
481 error_bits = afsr &
482 (SCHIZO_CEAFSR_PPIO | SCHIZO_CEAFSR_PDRD | SCHIZO_CEAFSR_PDWR |
483 SCHIZO_CEAFSR_SPIO | SCHIZO_CEAFSR_SDMA);
484 if (!error_bits)
485 return IRQ_NONE;
486 upa_writeq(error_bits, afsr_reg);
487
488 /* Log the error. */
489 printk("%s: Correctable Error, primary error type[%s]\n",
490 pbm->name,
491 (((error_bits & SCHIZO_CEAFSR_PPIO) ?
492 "PIO" :
493 ((error_bits & SCHIZO_CEAFSR_PDRD) ?
494 "DMA Read" :
495 ((error_bits & SCHIZO_CEAFSR_PDWR) ?
496 "DMA Write" : "???")))));
497
498 /* XXX Use syndrome and afar to print out module string just like
499 * XXX UDB CE trap handler does... -DaveM
500 */
501 printk("%s: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n",
502 pbm->name,
503 (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL,
504 (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL,
505 (afsr & SCHIZO_UEAFSR_AID) >> 24UL);
506 printk("%s: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n",
507 pbm->name,
508 (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0,
509 (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0,
510 (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL,
511 (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL,
512 (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL);
513 printk("%s: CE AFAR [%016lx]\n", pbm->name, afar);
514 printk("%s: CE Secondary errors [", pbm->name);
515 reported = 0;
516 if (afsr & SCHIZO_CEAFSR_SPIO) {
517 reported++;
518 printk("(PIO)");
519 }
520 if (afsr & SCHIZO_CEAFSR_SDMA) {
521 reported++;
522 printk("(DMA)");
523 }
524 if (!reported)
525 printk("(none)");
526 printk("]\n");
527
528 return IRQ_HANDLED;
529 }
530
531 #define SCHIZO_PCI_AFSR 0x2010UL
532 #define SCHIZO_PCI_AFAR 0x2018UL
533
534 #define SCHIZO_PCIAFSR_PMA 0x8000000000000000UL /* Schizo/Tomatillo */
535 #define SCHIZO_PCIAFSR_PTA 0x4000000000000000UL /* Schizo/Tomatillo */
536 #define SCHIZO_PCIAFSR_PRTRY 0x2000000000000000UL /* Schizo/Tomatillo */
537 #define SCHIZO_PCIAFSR_PPERR 0x1000000000000000UL /* Schizo/Tomatillo */
538 #define SCHIZO_PCIAFSR_PTTO 0x0800000000000000UL /* Schizo/Tomatillo */
539 #define SCHIZO_PCIAFSR_PUNUS 0x0400000000000000UL /* Schizo */
540 #define SCHIZO_PCIAFSR_SMA 0x0200000000000000UL /* Schizo/Tomatillo */
541 #define SCHIZO_PCIAFSR_STA 0x0100000000000000UL /* Schizo/Tomatillo */
542 #define SCHIZO_PCIAFSR_SRTRY 0x0080000000000000UL /* Schizo/Tomatillo */
543 #define SCHIZO_PCIAFSR_SPERR 0x0040000000000000UL /* Schizo/Tomatillo */
544 #define SCHIZO_PCIAFSR_STTO 0x0020000000000000UL /* Schizo/Tomatillo */
545 #define SCHIZO_PCIAFSR_SUNUS 0x0010000000000000UL /* Schizo */
546 #define SCHIZO_PCIAFSR_BMSK 0x000003ff00000000UL /* Schizo/Tomatillo */
547 #define SCHIZO_PCIAFSR_BLK 0x0000000080000000UL /* Schizo/Tomatillo */
548 #define SCHIZO_PCIAFSR_CFG 0x0000000040000000UL /* Schizo/Tomatillo */
549 #define SCHIZO_PCIAFSR_MEM 0x0000000020000000UL /* Schizo/Tomatillo */
550 #define SCHIZO_PCIAFSR_IO 0x0000000010000000UL /* Schizo/Tomatillo */
551
552 #define SCHIZO_PCI_CTRL (0x2000UL)
553 #define SCHIZO_PCICTRL_BUS_UNUS (1UL << 63UL) /* Safari */
554 #define SCHIZO_PCICTRL_DTO_INT (1UL << 61UL) /* Tomatillo */
555 #define SCHIZO_PCICTRL_ARB_PRIO (0x1ff << 52UL) /* Tomatillo */
556 #define SCHIZO_PCICTRL_ESLCK (1UL << 51UL) /* Safari */
557 #define SCHIZO_PCICTRL_ERRSLOT (7UL << 48UL) /* Safari */
558 #define SCHIZO_PCICTRL_TTO_ERR (1UL << 38UL) /* Safari/Tomatillo */
559 #define SCHIZO_PCICTRL_RTRY_ERR (1UL << 37UL) /* Safari/Tomatillo */
560 #define SCHIZO_PCICTRL_DTO_ERR (1UL << 36UL) /* Safari/Tomatillo */
561 #define SCHIZO_PCICTRL_SBH_ERR (1UL << 35UL) /* Safari */
562 #define SCHIZO_PCICTRL_SERR (1UL << 34UL) /* Safari/Tomatillo */
563 #define SCHIZO_PCICTRL_PCISPD (1UL << 33UL) /* Safari */
564 #define SCHIZO_PCICTRL_MRM_PREF (1UL << 30UL) /* Tomatillo */
565 #define SCHIZO_PCICTRL_RDO_PREF (1UL << 29UL) /* Tomatillo */
566 #define SCHIZO_PCICTRL_RDL_PREF (1UL << 28UL) /* Tomatillo */
567 #define SCHIZO_PCICTRL_PTO (3UL << 24UL) /* Safari/Tomatillo */
568 #define SCHIZO_PCICTRL_PTO_SHIFT 24UL
569 #define SCHIZO_PCICTRL_TRWSW (7UL << 21UL) /* Tomatillo */
570 #define SCHIZO_PCICTRL_F_TGT_A (1UL << 20UL) /* Tomatillo */
571 #define SCHIZO_PCICTRL_S_DTO_INT (1UL << 19UL) /* Safari */
572 #define SCHIZO_PCICTRL_F_TGT_RT (1UL << 19UL) /* Tomatillo */
573 #define SCHIZO_PCICTRL_SBH_INT (1UL << 18UL) /* Safari */
574 #define SCHIZO_PCICTRL_T_DTO_INT (1UL << 18UL) /* Tomatillo */
575 #define SCHIZO_PCICTRL_EEN (1UL << 17UL) /* Safari/Tomatillo */
576 #define SCHIZO_PCICTRL_PARK (1UL << 16UL) /* Safari/Tomatillo */
577 #define SCHIZO_PCICTRL_PCIRST (1UL << 8UL) /* Safari */
578 #define SCHIZO_PCICTRL_ARB_S (0x3fUL << 0UL) /* Safari */
579 #define SCHIZO_PCICTRL_ARB_T (0xffUL << 0UL) /* Tomatillo */
580
581 static irqreturn_t schizo_pcierr_intr_other(struct pci_pbm_info *pbm)
582 {
583 unsigned long csr_reg, csr, csr_error_bits;
584 irqreturn_t ret = IRQ_NONE;
585 u32 stat;
586
587 csr_reg = pbm->pbm_regs + SCHIZO_PCI_CTRL;
588 csr = upa_readq(csr_reg);
589 csr_error_bits =
590 csr & (SCHIZO_PCICTRL_BUS_UNUS |
591 SCHIZO_PCICTRL_TTO_ERR |
592 SCHIZO_PCICTRL_RTRY_ERR |
593 SCHIZO_PCICTRL_DTO_ERR |
594 SCHIZO_PCICTRL_SBH_ERR |
595 SCHIZO_PCICTRL_SERR);
596 if (csr_error_bits) {
597 /* Clear the errors. */
598 upa_writeq(csr, csr_reg);
599
600 /* Log 'em. */
601 if (csr_error_bits & SCHIZO_PCICTRL_BUS_UNUS)
602 printk("%s: Bus unusable error asserted.\n",
603 pbm->name);
604 if (csr_error_bits & SCHIZO_PCICTRL_TTO_ERR)
605 printk("%s: PCI TRDY# timeout error asserted.\n",
606 pbm->name);
607 if (csr_error_bits & SCHIZO_PCICTRL_RTRY_ERR)
608 printk("%s: PCI excessive retry error asserted.\n",
609 pbm->name);
610 if (csr_error_bits & SCHIZO_PCICTRL_DTO_ERR)
611 printk("%s: PCI discard timeout error asserted.\n",
612 pbm->name);
613 if (csr_error_bits & SCHIZO_PCICTRL_SBH_ERR)
614 printk("%s: PCI streaming byte hole error asserted.\n",
615 pbm->name);
616 if (csr_error_bits & SCHIZO_PCICTRL_SERR)
617 printk("%s: PCI SERR signal asserted.\n",
618 pbm->name);
619 ret = IRQ_HANDLED;
620 }
621 pbm->pci_ops->read(pbm->pci_bus, 0, PCI_STATUS, 2, &stat);
622 if (stat & (PCI_STATUS_PARITY |
623 PCI_STATUS_SIG_TARGET_ABORT |
624 PCI_STATUS_REC_TARGET_ABORT |
625 PCI_STATUS_REC_MASTER_ABORT |
626 PCI_STATUS_SIG_SYSTEM_ERROR)) {
627 printk("%s: PCI bus error, PCI_STATUS[%04x]\n",
628 pbm->name, stat);
629 pbm->pci_ops->write(pbm->pci_bus, 0, PCI_STATUS, 2, 0xffff);
630 ret = IRQ_HANDLED;
631 }
632 return ret;
633 }
634
635 static irqreturn_t schizo_pcierr_intr(int irq, void *dev_id)
636 {
637 struct pci_pbm_info *pbm = dev_id;
638 unsigned long afsr_reg, afar_reg, base;
639 unsigned long afsr, afar, error_bits;
640 int reported;
641
642 base = pbm->pbm_regs;
643
644 afsr_reg = base + SCHIZO_PCI_AFSR;
645 afar_reg = base + SCHIZO_PCI_AFAR;
646
647 /* Latch error status. */
648 afar = upa_readq(afar_reg);
649 afsr = upa_readq(afsr_reg);
650
651 /* Clear primary/secondary error status bits. */
652 error_bits = afsr &
653 (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
654 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
655 SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |
656 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
657 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
658 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS);
659 if (!error_bits)
660 return schizo_pcierr_intr_other(pbm);
661 upa_writeq(error_bits, afsr_reg);
662
663 /* Log the error. */
664 printk("%s: PCI Error, primary error type[%s]\n",
665 pbm->name,
666 (((error_bits & SCHIZO_PCIAFSR_PMA) ?
667 "Master Abort" :
668 ((error_bits & SCHIZO_PCIAFSR_PTA) ?
669 "Target Abort" :
670 ((error_bits & SCHIZO_PCIAFSR_PRTRY) ?
671 "Excessive Retries" :
672 ((error_bits & SCHIZO_PCIAFSR_PPERR) ?
673 "Parity Error" :
674 ((error_bits & SCHIZO_PCIAFSR_PTTO) ?
675 "Timeout" :
676 ((error_bits & SCHIZO_PCIAFSR_PUNUS) ?
677 "Bus Unusable" : "???"))))))));
678 printk("%s: bytemask[%04lx] was_block(%d) space(%s)\n",
679 pbm->name,
680 (afsr & SCHIZO_PCIAFSR_BMSK) >> 32UL,
681 (afsr & SCHIZO_PCIAFSR_BLK) ? 1 : 0,
682 ((afsr & SCHIZO_PCIAFSR_CFG) ?
683 "Config" :
684 ((afsr & SCHIZO_PCIAFSR_MEM) ?
685 "Memory" :
686 ((afsr & SCHIZO_PCIAFSR_IO) ?
687 "I/O" : "???"))));
688 printk("%s: PCI AFAR [%016lx]\n",
689 pbm->name, afar);
690 printk("%s: PCI Secondary errors [",
691 pbm->name);
692 reported = 0;
693 if (afsr & SCHIZO_PCIAFSR_SMA) {
694 reported++;
695 printk("(Master Abort)");
696 }
697 if (afsr & SCHIZO_PCIAFSR_STA) {
698 reported++;
699 printk("(Target Abort)");
700 }
701 if (afsr & SCHIZO_PCIAFSR_SRTRY) {
702 reported++;
703 printk("(Excessive Retries)");
704 }
705 if (afsr & SCHIZO_PCIAFSR_SPERR) {
706 reported++;
707 printk("(Parity Error)");
708 }
709 if (afsr & SCHIZO_PCIAFSR_STTO) {
710 reported++;
711 printk("(Timeout)");
712 }
713 if (afsr & SCHIZO_PCIAFSR_SUNUS) {
714 reported++;
715 printk("(Bus Unusable)");
716 }
717 if (!reported)
718 printk("(none)");
719 printk("]\n");
720
721 /* For the error types shown, scan PBM's PCI bus for devices
722 * which have logged that error type.
723 */
724
725 /* If we see a Target Abort, this could be the result of an
726 * IOMMU translation error of some sort. It is extremely
727 * useful to log this information as usually it indicates
728 * a bug in the IOMMU support code or a PCI device driver.
729 */
730 if (error_bits & (SCHIZO_PCIAFSR_PTA | SCHIZO_PCIAFSR_STA)) {
731 schizo_check_iommu_error(pbm, PCI_ERR);
732 pci_scan_for_target_abort(pbm, pbm->pci_bus);
733 }
734 if (error_bits & (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_SMA))
735 pci_scan_for_master_abort(pbm, pbm->pci_bus);
736
737 /* For excessive retries, PSYCHO/PBM will abort the device
738 * and there is no way to specifically check for excessive
739 * retries in the config space status registers. So what
740 * we hope is that we'll catch it via the master/target
741 * abort events.
742 */
743
744 if (error_bits & (SCHIZO_PCIAFSR_PPERR | SCHIZO_PCIAFSR_SPERR))
745 pci_scan_for_parity_error(pbm, pbm->pci_bus);
746
747 return IRQ_HANDLED;
748 }
749
750 #define SCHIZO_SAFARI_ERRLOG 0x10018UL
751
752 #define SAFARI_ERRLOG_ERROUT 0x8000000000000000UL
753
754 #define BUS_ERROR_BADCMD 0x4000000000000000UL /* Schizo/Tomatillo */
755 #define BUS_ERROR_SSMDIS 0x2000000000000000UL /* Safari */
756 #define BUS_ERROR_BADMA 0x1000000000000000UL /* Safari */
757 #define BUS_ERROR_BADMB 0x0800000000000000UL /* Safari */
758 #define BUS_ERROR_BADMC 0x0400000000000000UL /* Safari */
759 #define BUS_ERROR_SNOOP_GR 0x0000000000200000UL /* Tomatillo */
760 #define BUS_ERROR_SNOOP_PCI 0x0000000000100000UL /* Tomatillo */
761 #define BUS_ERROR_SNOOP_RD 0x0000000000080000UL /* Tomatillo */
762 #define BUS_ERROR_SNOOP_RDS 0x0000000000020000UL /* Tomatillo */
763 #define BUS_ERROR_SNOOP_RDSA 0x0000000000010000UL /* Tomatillo */
764 #define BUS_ERROR_SNOOP_OWN 0x0000000000008000UL /* Tomatillo */
765 #define BUS_ERROR_SNOOP_RDO 0x0000000000004000UL /* Tomatillo */
766 #define BUS_ERROR_CPU1PS 0x0000000000002000UL /* Safari */
767 #define BUS_ERROR_WDATA_PERR 0x0000000000002000UL /* Tomatillo */
768 #define BUS_ERROR_CPU1PB 0x0000000000001000UL /* Safari */
769 #define BUS_ERROR_CTRL_PERR 0x0000000000001000UL /* Tomatillo */
770 #define BUS_ERROR_CPU0PS 0x0000000000000800UL /* Safari */
771 #define BUS_ERROR_SNOOP_ERR 0x0000000000000800UL /* Tomatillo */
772 #define BUS_ERROR_CPU0PB 0x0000000000000400UL /* Safari */
773 #define BUS_ERROR_JBUS_ILL_B 0x0000000000000400UL /* Tomatillo */
774 #define BUS_ERROR_CIQTO 0x0000000000000200UL /* Safari */
775 #define BUS_ERROR_LPQTO 0x0000000000000100UL /* Safari */
776 #define BUS_ERROR_JBUS_ILL_C 0x0000000000000100UL /* Tomatillo */
777 #define BUS_ERROR_SFPQTO 0x0000000000000080UL /* Safari */
778 #define BUS_ERROR_UFPQTO 0x0000000000000040UL /* Safari */
779 #define BUS_ERROR_RD_PERR 0x0000000000000040UL /* Tomatillo */
780 #define BUS_ERROR_APERR 0x0000000000000020UL /* Safari/Tomatillo */
781 #define BUS_ERROR_UNMAP 0x0000000000000010UL /* Safari/Tomatillo */
782 #define BUS_ERROR_BUSERR 0x0000000000000004UL /* Safari/Tomatillo */
783 #define BUS_ERROR_TIMEOUT 0x0000000000000002UL /* Safari/Tomatillo */
784 #define BUS_ERROR_ILL 0x0000000000000001UL /* Safari */
785
786 /* We only expect UNMAP errors here. The rest of the Safari errors
787 * are marked fatal and thus cause a system reset.
788 */
789 static irqreturn_t schizo_safarierr_intr(int irq, void *dev_id)
790 {
791 struct pci_pbm_info *pbm = dev_id;
792 u64 errlog;
793
794 errlog = upa_readq(pbm->controller_regs + SCHIZO_SAFARI_ERRLOG);
795 upa_writeq(errlog & ~(SAFARI_ERRLOG_ERROUT),
796 pbm->controller_regs + SCHIZO_SAFARI_ERRLOG);
797
798 if (!(errlog & BUS_ERROR_UNMAP)) {
799 printk("%s: Unexpected Safari/JBUS error interrupt, errlog[%016llx]\n",
800 pbm->name, errlog);
801
802 return IRQ_HANDLED;
803 }
804
805 printk("%s: Safari/JBUS interrupt, UNMAPPED error, interrogating IOMMUs.\n",
806 pbm->name);
807 schizo_check_iommu_error(pbm, SAFARI_ERR);
808
809 return IRQ_HANDLED;
810 }
811
812 /* Nearly identical to PSYCHO equivalents... */
813 #define SCHIZO_ECC_CTRL 0x10020UL
814 #define SCHIZO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */
815 #define SCHIZO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */
816 #define SCHIZO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */
817
818 #define SCHIZO_SAFARI_ERRCTRL 0x10008UL
819 #define SCHIZO_SAFERRCTRL_EN 0x8000000000000000UL
820 #define SCHIZO_SAFARI_IRQCTRL 0x10010UL
821 #define SCHIZO_SAFIRQCTRL_EN 0x8000000000000000UL
822
823 static int pbm_routes_this_ino(struct pci_pbm_info *pbm, u32 ino)
824 {
825 ino &= IMAP_INO;
826
827 if (pbm->ino_bitmap & (1UL << ino))
828 return 1;
829
830 return 0;
831 }
832
833 /* How the Tomatillo IRQs are routed around is pure guesswork here.
834 *
835 * All the Tomatillo devices I see in prtconf dumps seem to have only
836 * a single PCI bus unit attached to it. It would seem they are separate
837 * devices because their PortID (ie. JBUS ID) values are all different
838 * and thus the registers are mapped to totally different locations.
839 *
840 * However, two Tomatillo's look "similar" in that the only difference
841 * in their PortID is the lowest bit.
842 *
843 * So if we were to ignore this lower bit, it certainly looks like two
844 * PCI bus units of the same Tomatillo. I still have not really
845 * figured this out...
846 */
847 static void tomatillo_register_error_handlers(struct pci_pbm_info *pbm)
848 {
849 struct platform_device *op = of_find_device_by_node(pbm->op->dev.of_node);
850 u64 tmp, err_mask, err_no_mask;
851 int err;
852
853 /* Tomatillo IRQ property layout is:
854 * 0: PCIERR
855 * 1: UE ERR
856 * 2: CE ERR
857 * 3: SERR
858 * 4: POWER FAIL?
859 */
860
861 if (pbm_routes_this_ino(pbm, SCHIZO_UE_INO)) {
862 err = request_irq(op->archdata.irqs[1], schizo_ue_intr, 0,
863 "TOMATILLO_UE", pbm);
864 if (err)
865 printk(KERN_WARNING "%s: Could not register UE, "
866 "err=%d\n", pbm->name, err);
867 }
868 if (pbm_routes_this_ino(pbm, SCHIZO_CE_INO)) {
869 err = request_irq(op->archdata.irqs[2], schizo_ce_intr, 0,
870 "TOMATILLO_CE", pbm);
871 if (err)
872 printk(KERN_WARNING "%s: Could not register CE, "
873 "err=%d\n", pbm->name, err);
874 }
875 err = 0;
876 if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_A_INO)) {
877 err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0,
878 "TOMATILLO_PCIERR", pbm);
879 } else if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_B_INO)) {
880 err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0,
881 "TOMATILLO_PCIERR", pbm);
882 }
883 if (err)
884 printk(KERN_WARNING "%s: Could not register PCIERR, "
885 "err=%d\n", pbm->name, err);
886
887 if (pbm_routes_this_ino(pbm, SCHIZO_SERR_INO)) {
888 err = request_irq(op->archdata.irqs[3], schizo_safarierr_intr, 0,
889 "TOMATILLO_SERR", pbm);
890 if (err)
891 printk(KERN_WARNING "%s: Could not register SERR, "
892 "err=%d\n", pbm->name, err);
893 }
894
895 /* Enable UE and CE interrupts for controller. */
896 upa_writeq((SCHIZO_ECCCTRL_EE |
897 SCHIZO_ECCCTRL_UE |
898 SCHIZO_ECCCTRL_CE), pbm->controller_regs + SCHIZO_ECC_CTRL);
899
900 /* Enable PCI Error interrupts and clear error
901 * bits.
902 */
903 err_mask = (SCHIZO_PCICTRL_BUS_UNUS |
904 SCHIZO_PCICTRL_TTO_ERR |
905 SCHIZO_PCICTRL_RTRY_ERR |
906 SCHIZO_PCICTRL_SERR |
907 SCHIZO_PCICTRL_EEN);
908
909 err_no_mask = SCHIZO_PCICTRL_DTO_ERR;
910
911 tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_CTRL);
912 tmp |= err_mask;
913 tmp &= ~err_no_mask;
914 upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_CTRL);
915
916 err_mask = (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
917 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
918 SCHIZO_PCIAFSR_PTTO |
919 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
920 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
921 SCHIZO_PCIAFSR_STTO);
922
923 upa_writeq(err_mask, pbm->pbm_regs + SCHIZO_PCI_AFSR);
924
925 err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SNOOP_GR |
926 BUS_ERROR_SNOOP_PCI | BUS_ERROR_SNOOP_RD |
927 BUS_ERROR_SNOOP_RDS | BUS_ERROR_SNOOP_RDSA |
928 BUS_ERROR_SNOOP_OWN | BUS_ERROR_SNOOP_RDO |
929 BUS_ERROR_WDATA_PERR | BUS_ERROR_CTRL_PERR |
930 BUS_ERROR_SNOOP_ERR | BUS_ERROR_JBUS_ILL_B |
931 BUS_ERROR_JBUS_ILL_C | BUS_ERROR_RD_PERR |
932 BUS_ERROR_APERR | BUS_ERROR_UNMAP |
933 BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT);
934
935 upa_writeq((SCHIZO_SAFERRCTRL_EN | err_mask),
936 pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL);
937
938 upa_writeq((SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP)),
939 pbm->controller_regs + SCHIZO_SAFARI_IRQCTRL);
940 }
941
942 static void schizo_register_error_handlers(struct pci_pbm_info *pbm)
943 {
944 struct platform_device *op = of_find_device_by_node(pbm->op->dev.of_node);
945 u64 tmp, err_mask, err_no_mask;
946 int err;
947
948 /* Schizo IRQ property layout is:
949 * 0: PCIERR
950 * 1: UE ERR
951 * 2: CE ERR
952 * 3: SERR
953 * 4: POWER FAIL?
954 */
955
956 if (pbm_routes_this_ino(pbm, SCHIZO_UE_INO)) {
957 err = request_irq(op->archdata.irqs[1], schizo_ue_intr, 0,
958 "SCHIZO_UE", pbm);
959 if (err)
960 printk(KERN_WARNING "%s: Could not register UE, "
961 "err=%d\n", pbm->name, err);
962 }
963 if (pbm_routes_this_ino(pbm, SCHIZO_CE_INO)) {
964 err = request_irq(op->archdata.irqs[2], schizo_ce_intr, 0,
965 "SCHIZO_CE", pbm);
966 if (err)
967 printk(KERN_WARNING "%s: Could not register CE, "
968 "err=%d\n", pbm->name, err);
969 }
970 err = 0;
971 if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_A_INO)) {
972 err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0,
973 "SCHIZO_PCIERR", pbm);
974 } else if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_B_INO)) {
975 err = request_irq(op->archdata.irqs[0], schizo_pcierr_intr, 0,
976 "SCHIZO_PCIERR", pbm);
977 }
978 if (err)
979 printk(KERN_WARNING "%s: Could not register PCIERR, "
980 "err=%d\n", pbm->name, err);
981
982 if (pbm_routes_this_ino(pbm, SCHIZO_SERR_INO)) {
983 err = request_irq(op->archdata.irqs[3], schizo_safarierr_intr, 0,
984 "SCHIZO_SERR", pbm);
985 if (err)
986 printk(KERN_WARNING "%s: Could not register SERR, "
987 "err=%d\n", pbm->name, err);
988 }
989
990 /* Enable UE and CE interrupts for controller. */
991 upa_writeq((SCHIZO_ECCCTRL_EE |
992 SCHIZO_ECCCTRL_UE |
993 SCHIZO_ECCCTRL_CE), pbm->controller_regs + SCHIZO_ECC_CTRL);
994
995 err_mask = (SCHIZO_PCICTRL_BUS_UNUS |
996 SCHIZO_PCICTRL_ESLCK |
997 SCHIZO_PCICTRL_TTO_ERR |
998 SCHIZO_PCICTRL_RTRY_ERR |
999 SCHIZO_PCICTRL_SBH_ERR |
1000 SCHIZO_PCICTRL_SERR |
1001 SCHIZO_PCICTRL_EEN);
1002
1003 err_no_mask = (SCHIZO_PCICTRL_DTO_ERR |
1004 SCHIZO_PCICTRL_SBH_INT);
1005
1006 /* Enable PCI Error interrupts and clear error
1007 * bits for each PBM.
1008 */
1009 tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_CTRL);
1010 tmp |= err_mask;
1011 tmp &= ~err_no_mask;
1012 upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_CTRL);
1013
1014 upa_writeq((SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
1015 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
1016 SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |
1017 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
1018 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
1019 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS),
1020 pbm->pbm_regs + SCHIZO_PCI_AFSR);
1021
1022 /* Make all Safari error conditions fatal except unmapped
1023 * errors which we make generate interrupts.
1024 */
1025 err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SSMDIS |
1026 BUS_ERROR_BADMA | BUS_ERROR_BADMB |
1027 BUS_ERROR_BADMC |
1028 BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB |
1029 BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB |
1030 BUS_ERROR_CIQTO |
1031 BUS_ERROR_LPQTO | BUS_ERROR_SFPQTO |
1032 BUS_ERROR_UFPQTO | BUS_ERROR_APERR |
1033 BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT |
1034 BUS_ERROR_ILL);
1035 #if 1
1036 /* XXX Something wrong with some Excalibur systems
1037 * XXX Sun is shipping. The behavior on a 2-cpu
1038 * XXX machine is that both CPU1 parity error bits
1039 * XXX are set and are immediately set again when
1040 * XXX their error status bits are cleared. Just
1041 * XXX ignore them for now. -DaveM
1042 */
1043 err_mask &= ~(BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB |
1044 BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB);
1045 #endif
1046
1047 upa_writeq((SCHIZO_SAFERRCTRL_EN | err_mask),
1048 pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL);
1049 }
1050
1051 static void pbm_config_busmastering(struct pci_pbm_info *pbm)
1052 {
1053 u8 *addr;
1054
1055 /* Set cache-line size to 64 bytes, this is actually
1056 * a nop but I do it for completeness.
1057 */
1058 addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno,
1059 0, PCI_CACHE_LINE_SIZE);
1060 pci_config_write8(addr, 64 / sizeof(u32));
1061
1062 /* Set PBM latency timer to 64 PCI clocks. */
1063 addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno,
1064 0, PCI_LATENCY_TIMER);
1065 pci_config_write8(addr, 64);
1066 }
1067
1068 static void schizo_scan_bus(struct pci_pbm_info *pbm, struct device *parent)
1069 {
1070 pbm_config_busmastering(pbm);
1071 pbm->is_66mhz_capable =
1072 (of_find_property(pbm->op->dev.of_node, "66mhz-capable", NULL)
1073 != NULL);
1074
1075 pbm->pci_bus = pci_scan_one_pbm(pbm, parent);
1076
1077 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO)
1078 tomatillo_register_error_handlers(pbm);
1079 else
1080 schizo_register_error_handlers(pbm);
1081 }
1082
1083 #define SCHIZO_STRBUF_CONTROL (0x02800UL)
1084 #define SCHIZO_STRBUF_FLUSH (0x02808UL)
1085 #define SCHIZO_STRBUF_FSYNC (0x02810UL)
1086 #define SCHIZO_STRBUF_CTXFLUSH (0x02818UL)
1087 #define SCHIZO_STRBUF_CTXMATCH (0x10000UL)
1088
1089 static void schizo_pbm_strbuf_init(struct pci_pbm_info *pbm)
1090 {
1091 unsigned long base = pbm->pbm_regs;
1092 u64 control;
1093
1094 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) {
1095 /* TOMATILLO lacks streaming cache. */
1096 return;
1097 }
1098
1099 /* SCHIZO has context flushing. */
1100 pbm->stc.strbuf_control = base + SCHIZO_STRBUF_CONTROL;
1101 pbm->stc.strbuf_pflush = base + SCHIZO_STRBUF_FLUSH;
1102 pbm->stc.strbuf_fsync = base + SCHIZO_STRBUF_FSYNC;
1103 pbm->stc.strbuf_ctxflush = base + SCHIZO_STRBUF_CTXFLUSH;
1104 pbm->stc.strbuf_ctxmatch_base = base + SCHIZO_STRBUF_CTXMATCH;
1105
1106 pbm->stc.strbuf_flushflag = (volatile unsigned long *)
1107 ((((unsigned long)&pbm->stc.__flushflag_buf[0])
1108 + 63UL)
1109 & ~63UL);
1110 pbm->stc.strbuf_flushflag_pa = (unsigned long)
1111 __pa(pbm->stc.strbuf_flushflag);
1112
1113 /* Turn off LRU locking and diag mode, enable the
1114 * streaming buffer and leave the rerun-disable
1115 * setting however OBP set it.
1116 */
1117 control = upa_readq(pbm->stc.strbuf_control);
1118 control &= ~(SCHIZO_STRBUF_CTRL_LPTR |
1119 SCHIZO_STRBUF_CTRL_LENAB |
1120 SCHIZO_STRBUF_CTRL_DENAB);
1121 control |= SCHIZO_STRBUF_CTRL_ENAB;
1122 upa_writeq(control, pbm->stc.strbuf_control);
1123
1124 pbm->stc.strbuf_enabled = 1;
1125 }
1126
1127 #define SCHIZO_IOMMU_CONTROL (0x00200UL)
1128 #define SCHIZO_IOMMU_TSBBASE (0x00208UL)
1129 #define SCHIZO_IOMMU_FLUSH (0x00210UL)
1130 #define SCHIZO_IOMMU_CTXFLUSH (0x00218UL)
1131
1132 static int schizo_pbm_iommu_init(struct pci_pbm_info *pbm)
1133 {
1134 static const u32 vdma_default[] = { 0xc0000000, 0x40000000 };
1135 unsigned long i, tagbase, database;
1136 struct iommu *iommu = pbm->iommu;
1137 int tsbsize, err;
1138 const u32 *vdma;
1139 u32 dma_mask;
1140 u64 control;
1141
1142 vdma = of_get_property(pbm->op->dev.of_node, "virtual-dma", NULL);
1143 if (!vdma)
1144 vdma = vdma_default;
1145
1146 dma_mask = vdma[0];
1147 switch (vdma[1]) {
1148 case 0x20000000:
1149 dma_mask |= 0x1fffffff;
1150 tsbsize = 64;
1151 break;
1152
1153 case 0x40000000:
1154 dma_mask |= 0x3fffffff;
1155 tsbsize = 128;
1156 break;
1157
1158 case 0x80000000:
1159 dma_mask |= 0x7fffffff;
1160 tsbsize = 128;
1161 break;
1162
1163 default:
1164 printk(KERN_ERR PFX "Strange virtual-dma size.\n");
1165 return -EINVAL;
1166 }
1167
1168 /* Register addresses, SCHIZO has iommu ctx flushing. */
1169 iommu->iommu_control = pbm->pbm_regs + SCHIZO_IOMMU_CONTROL;
1170 iommu->iommu_tsbbase = pbm->pbm_regs + SCHIZO_IOMMU_TSBBASE;
1171 iommu->iommu_flush = pbm->pbm_regs + SCHIZO_IOMMU_FLUSH;
1172 iommu->iommu_tags = iommu->iommu_flush + (0xa580UL - 0x0210UL);
1173 iommu->iommu_ctxflush = pbm->pbm_regs + SCHIZO_IOMMU_CTXFLUSH;
1174
1175 /* We use the main control/status register of SCHIZO as the write
1176 * completion register.
1177 */
1178 iommu->write_complete_reg = pbm->controller_regs + 0x10000UL;
1179
1180 /*
1181 * Invalidate TLB Entries.
1182 */
1183 control = upa_readq(iommu->iommu_control);
1184 control |= SCHIZO_IOMMU_CTRL_DENAB;
1185 upa_writeq(control, iommu->iommu_control);
1186
1187 tagbase = SCHIZO_IOMMU_TAG, database = SCHIZO_IOMMU_DATA;
1188
1189 for (i = 0; i < 16; i++) {
1190 upa_writeq(0, pbm->pbm_regs + tagbase + (i * 8UL));
1191 upa_writeq(0, pbm->pbm_regs + database + (i * 8UL));
1192 }
1193
1194 /* Leave diag mode enabled for full-flushing done
1195 * in pci_iommu.c
1196 */
1197 err = iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask,
1198 pbm->numa_node);
1199 if (err) {
1200 printk(KERN_ERR PFX "iommu_table_init() fails with %d\n", err);
1201 return err;
1202 }
1203
1204 upa_writeq(__pa(iommu->page_table), iommu->iommu_tsbbase);
1205
1206 control = upa_readq(iommu->iommu_control);
1207 control &= ~(SCHIZO_IOMMU_CTRL_TSBSZ | SCHIZO_IOMMU_CTRL_TBWSZ);
1208 switch (tsbsize) {
1209 case 64:
1210 control |= SCHIZO_IOMMU_TSBSZ_64K;
1211 break;
1212 case 128:
1213 control |= SCHIZO_IOMMU_TSBSZ_128K;
1214 break;
1215 }
1216
1217 control |= SCHIZO_IOMMU_CTRL_ENAB;
1218 upa_writeq(control, iommu->iommu_control);
1219
1220 return 0;
1221 }
1222
1223 #define SCHIZO_PCI_IRQ_RETRY (0x1a00UL)
1224 #define SCHIZO_IRQ_RETRY_INF 0xffUL
1225
1226 #define SCHIZO_PCI_DIAG (0x2020UL)
1227 #define SCHIZO_PCIDIAG_D_BADECC (1UL << 10UL) /* Disable BAD ECC errors (Schizo) */
1228 #define SCHIZO_PCIDIAG_D_BYPASS (1UL << 9UL) /* Disable MMU bypass mode (Schizo/Tomatillo) */
1229 #define SCHIZO_PCIDIAG_D_TTO (1UL << 8UL) /* Disable TTO errors (Schizo/Tomatillo) */
1230 #define SCHIZO_PCIDIAG_D_RTRYARB (1UL << 7UL) /* Disable retry arbitration (Schizo) */
1231 #define SCHIZO_PCIDIAG_D_RETRY (1UL << 6UL) /* Disable retry limit (Schizo/Tomatillo) */
1232 #define SCHIZO_PCIDIAG_D_INTSYNC (1UL << 5UL) /* Disable interrupt/DMA synch (Schizo/Tomatillo) */
1233 #define SCHIZO_PCIDIAG_I_DMA_PARITY (1UL << 3UL) /* Invert DMA parity (Schizo/Tomatillo) */
1234 #define SCHIZO_PCIDIAG_I_PIOD_PARITY (1UL << 2UL) /* Invert PIO data parity (Schizo/Tomatillo) */
1235 #define SCHIZO_PCIDIAG_I_PIOA_PARITY (1UL << 1UL) /* Invert PIO address parity (Schizo/Tomatillo) */
1236
1237 #define TOMATILLO_PCI_IOC_CSR (0x2248UL)
1238 #define TOMATILLO_IOC_PART_WPENAB 0x0000000000080000UL
1239 #define TOMATILLO_IOC_RDMULT_PENAB 0x0000000000040000UL
1240 #define TOMATILLO_IOC_RDONE_PENAB 0x0000000000020000UL
1241 #define TOMATILLO_IOC_RDLINE_PENAB 0x0000000000010000UL
1242 #define TOMATILLO_IOC_RDMULT_PLEN 0x000000000000c000UL
1243 #define TOMATILLO_IOC_RDMULT_PLEN_SHIFT 14UL
1244 #define TOMATILLO_IOC_RDONE_PLEN 0x0000000000003000UL
1245 #define TOMATILLO_IOC_RDONE_PLEN_SHIFT 12UL
1246 #define TOMATILLO_IOC_RDLINE_PLEN 0x0000000000000c00UL
1247 #define TOMATILLO_IOC_RDLINE_PLEN_SHIFT 10UL
1248 #define TOMATILLO_IOC_PREF_OFF 0x00000000000003f8UL
1249 #define TOMATILLO_IOC_PREF_OFF_SHIFT 3UL
1250 #define TOMATILLO_IOC_RDMULT_CPENAB 0x0000000000000004UL
1251 #define TOMATILLO_IOC_RDONE_CPENAB 0x0000000000000002UL
1252 #define TOMATILLO_IOC_RDLINE_CPENAB 0x0000000000000001UL
1253
1254 #define TOMATILLO_PCI_IOC_TDIAG (0x2250UL)
1255 #define TOMATILLO_PCI_IOC_DDIAG (0x2290UL)
1256
1257 static void schizo_pbm_hw_init(struct pci_pbm_info *pbm)
1258 {
1259 u64 tmp;
1260
1261 upa_writeq(5, pbm->pbm_regs + SCHIZO_PCI_IRQ_RETRY);
1262
1263 tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_CTRL);
1264
1265 /* Enable arbiter for all PCI slots. */
1266 tmp |= 0xff;
1267
1268 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO &&
1269 pbm->chip_version >= 0x2)
1270 tmp |= 0x3UL << SCHIZO_PCICTRL_PTO_SHIFT;
1271
1272 if (!of_find_property(pbm->op->dev.of_node, "no-bus-parking", NULL))
1273 tmp |= SCHIZO_PCICTRL_PARK;
1274 else
1275 tmp &= ~SCHIZO_PCICTRL_PARK;
1276
1277 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO &&
1278 pbm->chip_version <= 0x1)
1279 tmp |= SCHIZO_PCICTRL_DTO_INT;
1280 else
1281 tmp &= ~SCHIZO_PCICTRL_DTO_INT;
1282
1283 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO)
1284 tmp |= (SCHIZO_PCICTRL_MRM_PREF |
1285 SCHIZO_PCICTRL_RDO_PREF |
1286 SCHIZO_PCICTRL_RDL_PREF);
1287
1288 upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_CTRL);
1289
1290 tmp = upa_readq(pbm->pbm_regs + SCHIZO_PCI_DIAG);
1291 tmp &= ~(SCHIZO_PCIDIAG_D_RTRYARB |
1292 SCHIZO_PCIDIAG_D_RETRY |
1293 SCHIZO_PCIDIAG_D_INTSYNC);
1294 upa_writeq(tmp, pbm->pbm_regs + SCHIZO_PCI_DIAG);
1295
1296 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) {
1297 /* Clear prefetch lengths to workaround a bug in
1298 * Jalapeno...
1299 */
1300 tmp = (TOMATILLO_IOC_PART_WPENAB |
1301 (1 << TOMATILLO_IOC_PREF_OFF_SHIFT) |
1302 TOMATILLO_IOC_RDMULT_CPENAB |
1303 TOMATILLO_IOC_RDONE_CPENAB |
1304 TOMATILLO_IOC_RDLINE_CPENAB);
1305
1306 upa_writeq(tmp, pbm->pbm_regs + TOMATILLO_PCI_IOC_CSR);
1307 }
1308 }
1309
1310 static int schizo_pbm_init(struct pci_pbm_info *pbm,
1311 struct platform_device *op, u32 portid,
1312 int chip_type)
1313 {
1314 const struct linux_prom64_registers *regs;
1315 struct device_node *dp = op->dev.of_node;
1316 const char *chipset_name;
1317 int err;
1318
1319 switch (chip_type) {
1320 case PBM_CHIP_TYPE_TOMATILLO:
1321 chipset_name = "TOMATILLO";
1322 break;
1323
1324 case PBM_CHIP_TYPE_SCHIZO_PLUS:
1325 chipset_name = "SCHIZO+";
1326 break;
1327
1328 case PBM_CHIP_TYPE_SCHIZO:
1329 default:
1330 chipset_name = "SCHIZO";
1331 break;
1332 }
1333
1334 /* For SCHIZO, three OBP regs:
1335 * 1) PBM controller regs
1336 * 2) Schizo front-end controller regs (same for both PBMs)
1337 * 3) PBM PCI config space
1338 *
1339 * For TOMATILLO, four OBP regs:
1340 * 1) PBM controller regs
1341 * 2) Tomatillo front-end controller regs
1342 * 3) PBM PCI config space
1343 * 4) Ichip regs
1344 */
1345 regs = of_get_property(dp, "reg", NULL);
1346
1347 pbm->next = pci_pbm_root;
1348 pci_pbm_root = pbm;
1349
1350 pbm->numa_node = -1;
1351
1352 pbm->pci_ops = &sun4u_pci_ops;
1353 pbm->config_space_reg_bits = 8;
1354
1355 pbm->index = pci_num_pbms++;
1356
1357 pbm->portid = portid;
1358 pbm->op = op;
1359
1360 pbm->chip_type = chip_type;
1361 pbm->chip_version = of_getintprop_default(dp, "version#", 0);
1362 pbm->chip_revision = of_getintprop_default(dp, "module-version#", 0);
1363
1364 pbm->pbm_regs = regs[0].phys_addr;
1365 pbm->controller_regs = regs[1].phys_addr - 0x10000UL;
1366
1367 if (chip_type == PBM_CHIP_TYPE_TOMATILLO)
1368 pbm->sync_reg = regs[3].phys_addr + 0x1a18UL;
1369
1370 pbm->name = dp->full_name;
1371
1372 printk("%s: %s PCI Bus Module ver[%x:%x]\n",
1373 pbm->name, chipset_name,
1374 pbm->chip_version, pbm->chip_revision);
1375
1376 schizo_pbm_hw_init(pbm);
1377
1378 pci_determine_mem_io_space(pbm);
1379
1380 pci_get_pbm_props(pbm);
1381
1382 err = schizo_pbm_iommu_init(pbm);
1383 if (err)
1384 return err;
1385
1386 schizo_pbm_strbuf_init(pbm);
1387
1388 schizo_scan_bus(pbm, &op->dev);
1389
1390 return 0;
1391 }
1392
1393 static inline int portid_compare(u32 x, u32 y, int chip_type)
1394 {
1395 if (chip_type == PBM_CHIP_TYPE_TOMATILLO) {
1396 if (x == (y ^ 1))
1397 return 1;
1398 return 0;
1399 }
1400 return (x == y);
1401 }
1402
1403 static struct pci_pbm_info *schizo_find_sibling(u32 portid, int chip_type)
1404 {
1405 struct pci_pbm_info *pbm;
1406
1407 for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
1408 if (portid_compare(pbm->portid, portid, chip_type))
1409 return pbm;
1410 }
1411 return NULL;
1412 }
1413
1414 static int __schizo_init(struct platform_device *op, unsigned long chip_type)
1415 {
1416 struct device_node *dp = op->dev.of_node;
1417 struct pci_pbm_info *pbm;
1418 struct iommu *iommu;
1419 u32 portid;
1420 int err;
1421
1422 portid = of_getintprop_default(dp, "portid", 0xff);
1423
1424 err = -ENOMEM;
1425 pbm = kzalloc(sizeof(*pbm), GFP_KERNEL);
1426 if (!pbm) {
1427 printk(KERN_ERR PFX "Cannot allocate pci_pbm_info.\n");
1428 goto out_err;
1429 }
1430
1431 pbm->sibling = schizo_find_sibling(portid, chip_type);
1432
1433 iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL);
1434 if (!iommu) {
1435 printk(KERN_ERR PFX "Cannot allocate PBM A iommu.\n");
1436 goto out_free_pbm;
1437 }
1438
1439 pbm->iommu = iommu;
1440
1441 if (schizo_pbm_init(pbm, op, portid, chip_type))
1442 goto out_free_iommu;
1443
1444 if (pbm->sibling)
1445 pbm->sibling->sibling = pbm;
1446
1447 dev_set_drvdata(&op->dev, pbm);
1448
1449 return 0;
1450
1451 out_free_iommu:
1452 kfree(pbm->iommu);
1453
1454 out_free_pbm:
1455 kfree(pbm);
1456
1457 out_err:
1458 return err;
1459 }
1460
1461 static const struct of_device_id schizo_match[];
1462 static int schizo_probe(struct platform_device *op)
1463 {
1464 const struct of_device_id *match;
1465
1466 match = of_match_device(schizo_match, &op->dev);
1467 if (!match)
1468 return -EINVAL;
1469 return __schizo_init(op, (unsigned long)match->data);
1470 }
1471
1472 /* The ordering of this table is very important. Some Tomatillo
1473 * nodes announce that they are compatible with both pci108e,a801
1474 * and pci108e,8001. So list the chips in reverse chronological
1475 * order.
1476 */
1477 static const struct of_device_id schizo_match[] = {
1478 {
1479 .name = "pci",
1480 .compatible = "pci108e,a801",
1481 .data = (void *) PBM_CHIP_TYPE_TOMATILLO,
1482 },
1483 {
1484 .name = "pci",
1485 .compatible = "pci108e,8002",
1486 .data = (void *) PBM_CHIP_TYPE_SCHIZO_PLUS,
1487 },
1488 {
1489 .name = "pci",
1490 .compatible = "pci108e,8001",
1491 .data = (void *) PBM_CHIP_TYPE_SCHIZO,
1492 },
1493 {},
1494 };
1495
1496 static struct platform_driver schizo_driver = {
1497 .driver = {
1498 .name = DRIVER_NAME,
1499 .of_match_table = schizo_match,
1500 },
1501 .probe = schizo_probe,
1502 };
1503
1504 static int __init schizo_init(void)
1505 {
1506 return platform_driver_register(&schizo_driver);
1507 }
1508
1509 subsys_initcall(schizo_init);
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