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mtd: nand: atmel: Relax tADL_min constraint
[mirror_ubuntu-artful-kernel.git] / arch / sparc / kernel / pci_sun4v.c
1 /* pci_sun4v.c: SUN4V specific PCI controller support.
2 *
3 * Copyright (C) 2006, 2007, 2008 David S. Miller (davem@davemloft.net)
4 */
5
6 #include <linux/kernel.h>
7 #include <linux/types.h>
8 #include <linux/pci.h>
9 #include <linux/init.h>
10 #include <linux/slab.h>
11 #include <linux/interrupt.h>
12 #include <linux/percpu.h>
13 #include <linux/irq.h>
14 #include <linux/msi.h>
15 #include <linux/export.h>
16 #include <linux/log2.h>
17 #include <linux/of_device.h>
18 #include <linux/iommu-common.h>
19
20 #include <asm/iommu.h>
21 #include <asm/irq.h>
22 #include <asm/hypervisor.h>
23 #include <asm/prom.h>
24
25 #include "pci_impl.h"
26 #include "iommu_common.h"
27 #include "kernel.h"
28
29 #include "pci_sun4v.h"
30
31 #define DRIVER_NAME "pci_sun4v"
32 #define PFX DRIVER_NAME ": "
33
34 static unsigned long vpci_major;
35 static unsigned long vpci_minor;
36
37 struct vpci_version {
38 unsigned long major;
39 unsigned long minor;
40 };
41
42 /* Ordered from largest major to lowest */
43 static struct vpci_version vpci_versions[] = {
44 { .major = 2, .minor = 0 },
45 { .major = 1, .minor = 1 },
46 };
47
48 static unsigned long vatu_major = 1;
49 static unsigned long vatu_minor = 1;
50
51 #define PGLIST_NENTS (PAGE_SIZE / sizeof(u64))
52
53 struct iommu_batch {
54 struct device *dev; /* Device mapping is for. */
55 unsigned long prot; /* IOMMU page protections */
56 unsigned long entry; /* Index into IOTSB. */
57 u64 *pglist; /* List of physical pages */
58 unsigned long npages; /* Number of pages in list. */
59 };
60
61 static DEFINE_PER_CPU(struct iommu_batch, iommu_batch);
62 static int iommu_batch_initialized;
63
64 /* Interrupts must be disabled. */
65 static inline void iommu_batch_start(struct device *dev, unsigned long prot, unsigned long entry)
66 {
67 struct iommu_batch *p = this_cpu_ptr(&iommu_batch);
68
69 p->dev = dev;
70 p->prot = prot;
71 p->entry = entry;
72 p->npages = 0;
73 }
74
75 /* Interrupts must be disabled. */
76 static long iommu_batch_flush(struct iommu_batch *p, u64 mask)
77 {
78 struct pci_pbm_info *pbm = p->dev->archdata.host_controller;
79 u64 *pglist = p->pglist;
80 u64 index_count;
81 unsigned long devhandle = pbm->devhandle;
82 unsigned long prot = p->prot;
83 unsigned long entry = p->entry;
84 unsigned long npages = p->npages;
85 unsigned long iotsb_num;
86 unsigned long ret;
87 long num;
88
89 /* VPCI maj=1, min=[0,1] only supports read and write */
90 if (vpci_major < 2)
91 prot &= (HV_PCI_MAP_ATTR_READ | HV_PCI_MAP_ATTR_WRITE);
92
93 while (npages != 0) {
94 if (mask <= DMA_BIT_MASK(32)) {
95 num = pci_sun4v_iommu_map(devhandle,
96 HV_PCI_TSBID(0, entry),
97 npages,
98 prot,
99 __pa(pglist));
100 if (unlikely(num < 0)) {
101 pr_err_ratelimited("%s: IOMMU map of [%08lx:%08llx:%lx:%lx:%lx] failed with status %ld\n",
102 __func__,
103 devhandle,
104 HV_PCI_TSBID(0, entry),
105 npages, prot, __pa(pglist),
106 num);
107 return -1;
108 }
109 } else {
110 index_count = HV_PCI_IOTSB_INDEX_COUNT(npages, entry),
111 iotsb_num = pbm->iommu->atu->iotsb->iotsb_num;
112 ret = pci_sun4v_iotsb_map(devhandle,
113 iotsb_num,
114 index_count,
115 prot,
116 __pa(pglist),
117 &num);
118 if (unlikely(ret != HV_EOK)) {
119 pr_err_ratelimited("%s: ATU map of [%08lx:%lx:%llx:%lx:%lx] failed with status %ld\n",
120 __func__,
121 devhandle, iotsb_num,
122 index_count, prot,
123 __pa(pglist), ret);
124 return -1;
125 }
126 }
127 entry += num;
128 npages -= num;
129 pglist += num;
130 }
131
132 p->entry = entry;
133 p->npages = 0;
134
135 return 0;
136 }
137
138 static inline void iommu_batch_new_entry(unsigned long entry, u64 mask)
139 {
140 struct iommu_batch *p = this_cpu_ptr(&iommu_batch);
141
142 if (p->entry + p->npages == entry)
143 return;
144 if (p->entry != ~0UL)
145 iommu_batch_flush(p, mask);
146 p->entry = entry;
147 }
148
149 /* Interrupts must be disabled. */
150 static inline long iommu_batch_add(u64 phys_page, u64 mask)
151 {
152 struct iommu_batch *p = this_cpu_ptr(&iommu_batch);
153
154 BUG_ON(p->npages >= PGLIST_NENTS);
155
156 p->pglist[p->npages++] = phys_page;
157 if (p->npages == PGLIST_NENTS)
158 return iommu_batch_flush(p, mask);
159
160 return 0;
161 }
162
163 /* Interrupts must be disabled. */
164 static inline long iommu_batch_end(u64 mask)
165 {
166 struct iommu_batch *p = this_cpu_ptr(&iommu_batch);
167
168 BUG_ON(p->npages >= PGLIST_NENTS);
169
170 return iommu_batch_flush(p, mask);
171 }
172
173 static void *dma_4v_alloc_coherent(struct device *dev, size_t size,
174 dma_addr_t *dma_addrp, gfp_t gfp,
175 unsigned long attrs)
176 {
177 u64 mask;
178 unsigned long flags, order, first_page, npages, n;
179 unsigned long prot = 0;
180 struct iommu *iommu;
181 struct atu *atu;
182 struct iommu_map_table *tbl;
183 struct page *page;
184 void *ret;
185 long entry;
186 int nid;
187
188 size = IO_PAGE_ALIGN(size);
189 order = get_order(size);
190 if (unlikely(order >= MAX_ORDER))
191 return NULL;
192
193 npages = size >> IO_PAGE_SHIFT;
194
195 if (attrs & DMA_ATTR_WEAK_ORDERING)
196 prot = HV_PCI_MAP_ATTR_RELAXED_ORDER;
197
198 nid = dev->archdata.numa_node;
199 page = alloc_pages_node(nid, gfp, order);
200 if (unlikely(!page))
201 return NULL;
202
203 first_page = (unsigned long) page_address(page);
204 memset((char *)first_page, 0, PAGE_SIZE << order);
205
206 iommu = dev->archdata.iommu;
207 atu = iommu->atu;
208
209 mask = dev->coherent_dma_mask;
210 if (mask <= DMA_BIT_MASK(32))
211 tbl = &iommu->tbl;
212 else
213 tbl = &atu->tbl;
214
215 entry = iommu_tbl_range_alloc(dev, tbl, npages, NULL,
216 (unsigned long)(-1), 0);
217
218 if (unlikely(entry == IOMMU_ERROR_CODE))
219 goto range_alloc_fail;
220
221 *dma_addrp = (tbl->table_map_base + (entry << IO_PAGE_SHIFT));
222 ret = (void *) first_page;
223 first_page = __pa(first_page);
224
225 local_irq_save(flags);
226
227 iommu_batch_start(dev,
228 (HV_PCI_MAP_ATTR_READ | prot |
229 HV_PCI_MAP_ATTR_WRITE),
230 entry);
231
232 for (n = 0; n < npages; n++) {
233 long err = iommu_batch_add(first_page + (n * PAGE_SIZE), mask);
234 if (unlikely(err < 0L))
235 goto iommu_map_fail;
236 }
237
238 if (unlikely(iommu_batch_end(mask) < 0L))
239 goto iommu_map_fail;
240
241 local_irq_restore(flags);
242
243 return ret;
244
245 iommu_map_fail:
246 local_irq_restore(flags);
247 iommu_tbl_range_free(tbl, *dma_addrp, npages, IOMMU_ERROR_CODE);
248
249 range_alloc_fail:
250 free_pages(first_page, order);
251 return NULL;
252 }
253
254 unsigned long dma_4v_iotsb_bind(unsigned long devhandle,
255 unsigned long iotsb_num,
256 struct pci_bus *bus_dev)
257 {
258 struct pci_dev *pdev;
259 unsigned long err;
260 unsigned int bus;
261 unsigned int device;
262 unsigned int fun;
263
264 list_for_each_entry(pdev, &bus_dev->devices, bus_list) {
265 if (pdev->subordinate) {
266 /* No need to bind pci bridge */
267 dma_4v_iotsb_bind(devhandle, iotsb_num,
268 pdev->subordinate);
269 } else {
270 bus = bus_dev->number;
271 device = PCI_SLOT(pdev->devfn);
272 fun = PCI_FUNC(pdev->devfn);
273 err = pci_sun4v_iotsb_bind(devhandle, iotsb_num,
274 HV_PCI_DEVICE_BUILD(bus,
275 device,
276 fun));
277
278 /* If bind fails for one device it is going to fail
279 * for rest of the devices because we are sharing
280 * IOTSB. So in case of failure simply return with
281 * error.
282 */
283 if (err)
284 return err;
285 }
286 }
287
288 return 0;
289 }
290
291 static void dma_4v_iommu_demap(struct device *dev, unsigned long devhandle,
292 dma_addr_t dvma, unsigned long iotsb_num,
293 unsigned long entry, unsigned long npages)
294 {
295 unsigned long num, flags;
296 unsigned long ret;
297
298 local_irq_save(flags);
299 do {
300 if (dvma <= DMA_BIT_MASK(32)) {
301 num = pci_sun4v_iommu_demap(devhandle,
302 HV_PCI_TSBID(0, entry),
303 npages);
304 } else {
305 ret = pci_sun4v_iotsb_demap(devhandle, iotsb_num,
306 entry, npages, &num);
307 if (unlikely(ret != HV_EOK)) {
308 pr_err_ratelimited("pci_iotsb_demap() failed with error: %ld\n",
309 ret);
310 }
311 }
312 entry += num;
313 npages -= num;
314 } while (npages != 0);
315 local_irq_restore(flags);
316 }
317
318 static void dma_4v_free_coherent(struct device *dev, size_t size, void *cpu,
319 dma_addr_t dvma, unsigned long attrs)
320 {
321 struct pci_pbm_info *pbm;
322 struct iommu *iommu;
323 struct atu *atu;
324 struct iommu_map_table *tbl;
325 unsigned long order, npages, entry;
326 unsigned long iotsb_num;
327 u32 devhandle;
328
329 npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
330 iommu = dev->archdata.iommu;
331 pbm = dev->archdata.host_controller;
332 atu = iommu->atu;
333 devhandle = pbm->devhandle;
334
335 if (dvma <= DMA_BIT_MASK(32)) {
336 tbl = &iommu->tbl;
337 iotsb_num = 0; /* we don't care for legacy iommu */
338 } else {
339 tbl = &atu->tbl;
340 iotsb_num = atu->iotsb->iotsb_num;
341 }
342 entry = ((dvma - tbl->table_map_base) >> IO_PAGE_SHIFT);
343 dma_4v_iommu_demap(dev, devhandle, dvma, iotsb_num, entry, npages);
344 iommu_tbl_range_free(tbl, dvma, npages, IOMMU_ERROR_CODE);
345 order = get_order(size);
346 if (order < 10)
347 free_pages((unsigned long)cpu, order);
348 }
349
350 static dma_addr_t dma_4v_map_page(struct device *dev, struct page *page,
351 unsigned long offset, size_t sz,
352 enum dma_data_direction direction,
353 unsigned long attrs)
354 {
355 struct iommu *iommu;
356 struct atu *atu;
357 struct iommu_map_table *tbl;
358 u64 mask;
359 unsigned long flags, npages, oaddr;
360 unsigned long i, base_paddr;
361 unsigned long prot;
362 dma_addr_t bus_addr, ret;
363 long entry;
364
365 iommu = dev->archdata.iommu;
366 atu = iommu->atu;
367
368 if (unlikely(direction == DMA_NONE))
369 goto bad;
370
371 oaddr = (unsigned long)(page_address(page) + offset);
372 npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
373 npages >>= IO_PAGE_SHIFT;
374
375 mask = *dev->dma_mask;
376 if (mask <= DMA_BIT_MASK(32))
377 tbl = &iommu->tbl;
378 else
379 tbl = &atu->tbl;
380
381 entry = iommu_tbl_range_alloc(dev, tbl, npages, NULL,
382 (unsigned long)(-1), 0);
383
384 if (unlikely(entry == IOMMU_ERROR_CODE))
385 goto bad;
386
387 bus_addr = (tbl->table_map_base + (entry << IO_PAGE_SHIFT));
388 ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
389 base_paddr = __pa(oaddr & IO_PAGE_MASK);
390 prot = HV_PCI_MAP_ATTR_READ;
391 if (direction != DMA_TO_DEVICE)
392 prot |= HV_PCI_MAP_ATTR_WRITE;
393
394 if (attrs & DMA_ATTR_WEAK_ORDERING)
395 prot |= HV_PCI_MAP_ATTR_RELAXED_ORDER;
396
397 local_irq_save(flags);
398
399 iommu_batch_start(dev, prot, entry);
400
401 for (i = 0; i < npages; i++, base_paddr += IO_PAGE_SIZE) {
402 long err = iommu_batch_add(base_paddr, mask);
403 if (unlikely(err < 0L))
404 goto iommu_map_fail;
405 }
406 if (unlikely(iommu_batch_end(mask) < 0L))
407 goto iommu_map_fail;
408
409 local_irq_restore(flags);
410
411 return ret;
412
413 bad:
414 if (printk_ratelimit())
415 WARN_ON(1);
416 return SPARC_MAPPING_ERROR;
417
418 iommu_map_fail:
419 local_irq_restore(flags);
420 iommu_tbl_range_free(tbl, bus_addr, npages, IOMMU_ERROR_CODE);
421 return SPARC_MAPPING_ERROR;
422 }
423
424 static void dma_4v_unmap_page(struct device *dev, dma_addr_t bus_addr,
425 size_t sz, enum dma_data_direction direction,
426 unsigned long attrs)
427 {
428 struct pci_pbm_info *pbm;
429 struct iommu *iommu;
430 struct atu *atu;
431 struct iommu_map_table *tbl;
432 unsigned long npages;
433 unsigned long iotsb_num;
434 long entry;
435 u32 devhandle;
436
437 if (unlikely(direction == DMA_NONE)) {
438 if (printk_ratelimit())
439 WARN_ON(1);
440 return;
441 }
442
443 iommu = dev->archdata.iommu;
444 pbm = dev->archdata.host_controller;
445 atu = iommu->atu;
446 devhandle = pbm->devhandle;
447
448 npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
449 npages >>= IO_PAGE_SHIFT;
450 bus_addr &= IO_PAGE_MASK;
451
452 if (bus_addr <= DMA_BIT_MASK(32)) {
453 iotsb_num = 0; /* we don't care for legacy iommu */
454 tbl = &iommu->tbl;
455 } else {
456 iotsb_num = atu->iotsb->iotsb_num;
457 tbl = &atu->tbl;
458 }
459 entry = (bus_addr - tbl->table_map_base) >> IO_PAGE_SHIFT;
460 dma_4v_iommu_demap(dev, devhandle, bus_addr, iotsb_num, entry, npages);
461 iommu_tbl_range_free(tbl, bus_addr, npages, IOMMU_ERROR_CODE);
462 }
463
464 static int dma_4v_map_sg(struct device *dev, struct scatterlist *sglist,
465 int nelems, enum dma_data_direction direction,
466 unsigned long attrs)
467 {
468 struct scatterlist *s, *outs, *segstart;
469 unsigned long flags, handle, prot;
470 dma_addr_t dma_next = 0, dma_addr;
471 unsigned int max_seg_size;
472 unsigned long seg_boundary_size;
473 int outcount, incount, i;
474 struct iommu *iommu;
475 struct atu *atu;
476 struct iommu_map_table *tbl;
477 u64 mask;
478 unsigned long base_shift;
479 long err;
480
481 BUG_ON(direction == DMA_NONE);
482
483 iommu = dev->archdata.iommu;
484 if (nelems == 0 || !iommu)
485 return 0;
486 atu = iommu->atu;
487
488 prot = HV_PCI_MAP_ATTR_READ;
489 if (direction != DMA_TO_DEVICE)
490 prot |= HV_PCI_MAP_ATTR_WRITE;
491
492 if (attrs & DMA_ATTR_WEAK_ORDERING)
493 prot |= HV_PCI_MAP_ATTR_RELAXED_ORDER;
494
495 outs = s = segstart = &sglist[0];
496 outcount = 1;
497 incount = nelems;
498 handle = 0;
499
500 /* Init first segment length for backout at failure */
501 outs->dma_length = 0;
502
503 local_irq_save(flags);
504
505 iommu_batch_start(dev, prot, ~0UL);
506
507 max_seg_size = dma_get_max_seg_size(dev);
508 seg_boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
509 IO_PAGE_SIZE) >> IO_PAGE_SHIFT;
510
511 mask = *dev->dma_mask;
512 if (mask <= DMA_BIT_MASK(32))
513 tbl = &iommu->tbl;
514 else
515 tbl = &atu->tbl;
516
517 base_shift = tbl->table_map_base >> IO_PAGE_SHIFT;
518
519 for_each_sg(sglist, s, nelems, i) {
520 unsigned long paddr, npages, entry, out_entry = 0, slen;
521
522 slen = s->length;
523 /* Sanity check */
524 if (slen == 0) {
525 dma_next = 0;
526 continue;
527 }
528 /* Allocate iommu entries for that segment */
529 paddr = (unsigned long) SG_ENT_PHYS_ADDRESS(s);
530 npages = iommu_num_pages(paddr, slen, IO_PAGE_SIZE);
531 entry = iommu_tbl_range_alloc(dev, tbl, npages,
532 &handle, (unsigned long)(-1), 0);
533
534 /* Handle failure */
535 if (unlikely(entry == IOMMU_ERROR_CODE)) {
536 pr_err_ratelimited("iommu_alloc failed, iommu %p paddr %lx npages %lx\n",
537 tbl, paddr, npages);
538 goto iommu_map_failed;
539 }
540
541 iommu_batch_new_entry(entry, mask);
542
543 /* Convert entry to a dma_addr_t */
544 dma_addr = tbl->table_map_base + (entry << IO_PAGE_SHIFT);
545 dma_addr |= (s->offset & ~IO_PAGE_MASK);
546
547 /* Insert into HW table */
548 paddr &= IO_PAGE_MASK;
549 while (npages--) {
550 err = iommu_batch_add(paddr, mask);
551 if (unlikely(err < 0L))
552 goto iommu_map_failed;
553 paddr += IO_PAGE_SIZE;
554 }
555
556 /* If we are in an open segment, try merging */
557 if (segstart != s) {
558 /* We cannot merge if:
559 * - allocated dma_addr isn't contiguous to previous allocation
560 */
561 if ((dma_addr != dma_next) ||
562 (outs->dma_length + s->length > max_seg_size) ||
563 (is_span_boundary(out_entry, base_shift,
564 seg_boundary_size, outs, s))) {
565 /* Can't merge: create a new segment */
566 segstart = s;
567 outcount++;
568 outs = sg_next(outs);
569 } else {
570 outs->dma_length += s->length;
571 }
572 }
573
574 if (segstart == s) {
575 /* This is a new segment, fill entries */
576 outs->dma_address = dma_addr;
577 outs->dma_length = slen;
578 out_entry = entry;
579 }
580
581 /* Calculate next page pointer for contiguous check */
582 dma_next = dma_addr + slen;
583 }
584
585 err = iommu_batch_end(mask);
586
587 if (unlikely(err < 0L))
588 goto iommu_map_failed;
589
590 local_irq_restore(flags);
591
592 if (outcount < incount) {
593 outs = sg_next(outs);
594 outs->dma_address = SPARC_MAPPING_ERROR;
595 outs->dma_length = 0;
596 }
597
598 return outcount;
599
600 iommu_map_failed:
601 for_each_sg(sglist, s, nelems, i) {
602 if (s->dma_length != 0) {
603 unsigned long vaddr, npages;
604
605 vaddr = s->dma_address & IO_PAGE_MASK;
606 npages = iommu_num_pages(s->dma_address, s->dma_length,
607 IO_PAGE_SIZE);
608 iommu_tbl_range_free(tbl, vaddr, npages,
609 IOMMU_ERROR_CODE);
610 /* XXX demap? XXX */
611 s->dma_address = SPARC_MAPPING_ERROR;
612 s->dma_length = 0;
613 }
614 if (s == outs)
615 break;
616 }
617 local_irq_restore(flags);
618
619 return 0;
620 }
621
622 static void dma_4v_unmap_sg(struct device *dev, struct scatterlist *sglist,
623 int nelems, enum dma_data_direction direction,
624 unsigned long attrs)
625 {
626 struct pci_pbm_info *pbm;
627 struct scatterlist *sg;
628 struct iommu *iommu;
629 struct atu *atu;
630 unsigned long flags, entry;
631 unsigned long iotsb_num;
632 u32 devhandle;
633
634 BUG_ON(direction == DMA_NONE);
635
636 iommu = dev->archdata.iommu;
637 pbm = dev->archdata.host_controller;
638 atu = iommu->atu;
639 devhandle = pbm->devhandle;
640
641 local_irq_save(flags);
642
643 sg = sglist;
644 while (nelems--) {
645 dma_addr_t dma_handle = sg->dma_address;
646 unsigned int len = sg->dma_length;
647 unsigned long npages;
648 struct iommu_map_table *tbl;
649 unsigned long shift = IO_PAGE_SHIFT;
650
651 if (!len)
652 break;
653 npages = iommu_num_pages(dma_handle, len, IO_PAGE_SIZE);
654
655 if (dma_handle <= DMA_BIT_MASK(32)) {
656 iotsb_num = 0; /* we don't care for legacy iommu */
657 tbl = &iommu->tbl;
658 } else {
659 iotsb_num = atu->iotsb->iotsb_num;
660 tbl = &atu->tbl;
661 }
662 entry = ((dma_handle - tbl->table_map_base) >> shift);
663 dma_4v_iommu_demap(dev, devhandle, dma_handle, iotsb_num,
664 entry, npages);
665 iommu_tbl_range_free(tbl, dma_handle, npages,
666 IOMMU_ERROR_CODE);
667 sg = sg_next(sg);
668 }
669
670 local_irq_restore(flags);
671 }
672
673 static int dma_4v_supported(struct device *dev, u64 device_mask)
674 {
675 struct iommu *iommu = dev->archdata.iommu;
676 u64 dma_addr_mask;
677
678 if (device_mask > DMA_BIT_MASK(32) && iommu->atu)
679 dma_addr_mask = iommu->atu->dma_addr_mask;
680 else
681 dma_addr_mask = iommu->dma_addr_mask;
682
683 if ((device_mask & dma_addr_mask) == dma_addr_mask)
684 return 1;
685 return pci64_dma_supported(to_pci_dev(dev), device_mask);
686 }
687
688 static int dma_4v_mapping_error(struct device *dev, dma_addr_t dma_addr)
689 {
690 return dma_addr == SPARC_MAPPING_ERROR;
691 }
692
693 static const struct dma_map_ops sun4v_dma_ops = {
694 .alloc = dma_4v_alloc_coherent,
695 .free = dma_4v_free_coherent,
696 .map_page = dma_4v_map_page,
697 .unmap_page = dma_4v_unmap_page,
698 .map_sg = dma_4v_map_sg,
699 .unmap_sg = dma_4v_unmap_sg,
700 .dma_supported = dma_4v_supported,
701 .mapping_error = dma_4v_mapping_error,
702 };
703
704 static void pci_sun4v_scan_bus(struct pci_pbm_info *pbm, struct device *parent)
705 {
706 struct property *prop;
707 struct device_node *dp;
708
709 dp = pbm->op->dev.of_node;
710 prop = of_find_property(dp, "66mhz-capable", NULL);
711 pbm->is_66mhz_capable = (prop != NULL);
712 pbm->pci_bus = pci_scan_one_pbm(pbm, parent);
713
714 /* XXX register error interrupt handlers XXX */
715 }
716
717 static unsigned long probe_existing_entries(struct pci_pbm_info *pbm,
718 struct iommu_map_table *iommu)
719 {
720 struct iommu_pool *pool;
721 unsigned long i, pool_nr, cnt = 0;
722 u32 devhandle;
723
724 devhandle = pbm->devhandle;
725 for (pool_nr = 0; pool_nr < iommu->nr_pools; pool_nr++) {
726 pool = &(iommu->pools[pool_nr]);
727 for (i = pool->start; i <= pool->end; i++) {
728 unsigned long ret, io_attrs, ra;
729
730 ret = pci_sun4v_iommu_getmap(devhandle,
731 HV_PCI_TSBID(0, i),
732 &io_attrs, &ra);
733 if (ret == HV_EOK) {
734 if (page_in_phys_avail(ra)) {
735 pci_sun4v_iommu_demap(devhandle,
736 HV_PCI_TSBID(0,
737 i), 1);
738 } else {
739 cnt++;
740 __set_bit(i, iommu->map);
741 }
742 }
743 }
744 }
745 return cnt;
746 }
747
748 static int pci_sun4v_atu_alloc_iotsb(struct pci_pbm_info *pbm)
749 {
750 struct atu *atu = pbm->iommu->atu;
751 struct atu_iotsb *iotsb;
752 void *table;
753 u64 table_size;
754 u64 iotsb_num;
755 unsigned long order;
756 unsigned long err;
757
758 iotsb = kzalloc(sizeof(*iotsb), GFP_KERNEL);
759 if (!iotsb) {
760 err = -ENOMEM;
761 goto out_err;
762 }
763 atu->iotsb = iotsb;
764
765 /* calculate size of IOTSB */
766 table_size = (atu->size / IO_PAGE_SIZE) * 8;
767 order = get_order(table_size);
768 table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, order);
769 if (!table) {
770 err = -ENOMEM;
771 goto table_failed;
772 }
773 iotsb->table = table;
774 iotsb->ra = __pa(table);
775 iotsb->dvma_size = atu->size;
776 iotsb->dvma_base = atu->base;
777 iotsb->table_size = table_size;
778 iotsb->page_size = IO_PAGE_SIZE;
779
780 /* configure and register IOTSB with HV */
781 err = pci_sun4v_iotsb_conf(pbm->devhandle,
782 iotsb->ra,
783 iotsb->table_size,
784 iotsb->page_size,
785 iotsb->dvma_base,
786 &iotsb_num);
787 if (err) {
788 pr_err(PFX "pci_iotsb_conf failed error: %ld\n", err);
789 goto iotsb_conf_failed;
790 }
791 iotsb->iotsb_num = iotsb_num;
792
793 err = dma_4v_iotsb_bind(pbm->devhandle, iotsb_num, pbm->pci_bus);
794 if (err) {
795 pr_err(PFX "pci_iotsb_bind failed error: %ld\n", err);
796 goto iotsb_conf_failed;
797 }
798
799 return 0;
800
801 iotsb_conf_failed:
802 free_pages((unsigned long)table, order);
803 table_failed:
804 kfree(iotsb);
805 out_err:
806 return err;
807 }
808
809 static int pci_sun4v_atu_init(struct pci_pbm_info *pbm)
810 {
811 struct atu *atu = pbm->iommu->atu;
812 unsigned long err;
813 const u64 *ranges;
814 u64 map_size, num_iotte;
815 u64 dma_mask;
816 const u32 *page_size;
817 int len;
818
819 ranges = of_get_property(pbm->op->dev.of_node, "iommu-address-ranges",
820 &len);
821 if (!ranges) {
822 pr_err(PFX "No iommu-address-ranges\n");
823 return -EINVAL;
824 }
825
826 page_size = of_get_property(pbm->op->dev.of_node, "iommu-pagesizes",
827 NULL);
828 if (!page_size) {
829 pr_err(PFX "No iommu-pagesizes\n");
830 return -EINVAL;
831 }
832
833 /* There are 4 iommu-address-ranges supported. Each range is pair of
834 * {base, size}. The ranges[0] and ranges[1] are 32bit address space
835 * while ranges[2] and ranges[3] are 64bit space. We want to use 64bit
836 * address ranges to support 64bit addressing. Because 'size' for
837 * address ranges[2] and ranges[3] are same we can select either of
838 * ranges[2] or ranges[3] for mapping. However due to 'size' is too
839 * large for OS to allocate IOTSB we are using fix size 32G
840 * (ATU_64_SPACE_SIZE) which is more than enough for all PCIe devices
841 * to share.
842 */
843 atu->ranges = (struct atu_ranges *)ranges;
844 atu->base = atu->ranges[3].base;
845 atu->size = ATU_64_SPACE_SIZE;
846
847 /* Create IOTSB */
848 err = pci_sun4v_atu_alloc_iotsb(pbm);
849 if (err) {
850 pr_err(PFX "Error creating ATU IOTSB\n");
851 return err;
852 }
853
854 /* Create ATU iommu map.
855 * One bit represents one iotte in IOTSB table.
856 */
857 dma_mask = (roundup_pow_of_two(atu->size) - 1UL);
858 num_iotte = atu->size / IO_PAGE_SIZE;
859 map_size = num_iotte / 8;
860 atu->tbl.table_map_base = atu->base;
861 atu->dma_addr_mask = dma_mask;
862 atu->tbl.map = kzalloc(map_size, GFP_KERNEL);
863 if (!atu->tbl.map)
864 return -ENOMEM;
865
866 iommu_tbl_pool_init(&atu->tbl, num_iotte, IO_PAGE_SHIFT,
867 NULL, false /* no large_pool */,
868 0 /* default npools */,
869 false /* want span boundary checking */);
870
871 return 0;
872 }
873
874 static int pci_sun4v_iommu_init(struct pci_pbm_info *pbm)
875 {
876 static const u32 vdma_default[] = { 0x80000000, 0x80000000 };
877 struct iommu *iommu = pbm->iommu;
878 unsigned long num_tsb_entries, sz;
879 u32 dma_mask, dma_offset;
880 const u32 *vdma;
881
882 vdma = of_get_property(pbm->op->dev.of_node, "virtual-dma", NULL);
883 if (!vdma)
884 vdma = vdma_default;
885
886 if ((vdma[0] | vdma[1]) & ~IO_PAGE_MASK) {
887 printk(KERN_ERR PFX "Strange virtual-dma[%08x:%08x].\n",
888 vdma[0], vdma[1]);
889 return -EINVAL;
890 }
891
892 dma_mask = (roundup_pow_of_two(vdma[1]) - 1UL);
893 num_tsb_entries = vdma[1] / IO_PAGE_SIZE;
894
895 dma_offset = vdma[0];
896
897 /* Setup initial software IOMMU state. */
898 spin_lock_init(&iommu->lock);
899 iommu->ctx_lowest_free = 1;
900 iommu->tbl.table_map_base = dma_offset;
901 iommu->dma_addr_mask = dma_mask;
902
903 /* Allocate and initialize the free area map. */
904 sz = (num_tsb_entries + 7) / 8;
905 sz = (sz + 7UL) & ~7UL;
906 iommu->tbl.map = kzalloc(sz, GFP_KERNEL);
907 if (!iommu->tbl.map) {
908 printk(KERN_ERR PFX "Error, kmalloc(arena.map) failed.\n");
909 return -ENOMEM;
910 }
911 iommu_tbl_pool_init(&iommu->tbl, num_tsb_entries, IO_PAGE_SHIFT,
912 NULL, false /* no large_pool */,
913 0 /* default npools */,
914 false /* want span boundary checking */);
915 sz = probe_existing_entries(pbm, &iommu->tbl);
916 if (sz)
917 printk("%s: Imported %lu TSB entries from OBP\n",
918 pbm->name, sz);
919
920 return 0;
921 }
922
923 #ifdef CONFIG_PCI_MSI
924 struct pci_sun4v_msiq_entry {
925 u64 version_type;
926 #define MSIQ_VERSION_MASK 0xffffffff00000000UL
927 #define MSIQ_VERSION_SHIFT 32
928 #define MSIQ_TYPE_MASK 0x00000000000000ffUL
929 #define MSIQ_TYPE_SHIFT 0
930 #define MSIQ_TYPE_NONE 0x00
931 #define MSIQ_TYPE_MSG 0x01
932 #define MSIQ_TYPE_MSI32 0x02
933 #define MSIQ_TYPE_MSI64 0x03
934 #define MSIQ_TYPE_INTX 0x08
935 #define MSIQ_TYPE_NONE2 0xff
936
937 u64 intx_sysino;
938 u64 reserved1;
939 u64 stick;
940 u64 req_id; /* bus/device/func */
941 #define MSIQ_REQID_BUS_MASK 0xff00UL
942 #define MSIQ_REQID_BUS_SHIFT 8
943 #define MSIQ_REQID_DEVICE_MASK 0x00f8UL
944 #define MSIQ_REQID_DEVICE_SHIFT 3
945 #define MSIQ_REQID_FUNC_MASK 0x0007UL
946 #define MSIQ_REQID_FUNC_SHIFT 0
947
948 u64 msi_address;
949
950 /* The format of this value is message type dependent.
951 * For MSI bits 15:0 are the data from the MSI packet.
952 * For MSI-X bits 31:0 are the data from the MSI packet.
953 * For MSG, the message code and message routing code where:
954 * bits 39:32 is the bus/device/fn of the msg target-id
955 * bits 18:16 is the message routing code
956 * bits 7:0 is the message code
957 * For INTx the low order 2-bits are:
958 * 00 - INTA
959 * 01 - INTB
960 * 10 - INTC
961 * 11 - INTD
962 */
963 u64 msi_data;
964
965 u64 reserved2;
966 };
967
968 static int pci_sun4v_get_head(struct pci_pbm_info *pbm, unsigned long msiqid,
969 unsigned long *head)
970 {
971 unsigned long err, limit;
972
973 err = pci_sun4v_msiq_gethead(pbm->devhandle, msiqid, head);
974 if (unlikely(err))
975 return -ENXIO;
976
977 limit = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
978 if (unlikely(*head >= limit))
979 return -EFBIG;
980
981 return 0;
982 }
983
984 static int pci_sun4v_dequeue_msi(struct pci_pbm_info *pbm,
985 unsigned long msiqid, unsigned long *head,
986 unsigned long *msi)
987 {
988 struct pci_sun4v_msiq_entry *ep;
989 unsigned long err, type;
990
991 /* Note: void pointer arithmetic, 'head' is a byte offset */
992 ep = (pbm->msi_queues + ((msiqid - pbm->msiq_first) *
993 (pbm->msiq_ent_count *
994 sizeof(struct pci_sun4v_msiq_entry))) +
995 *head);
996
997 if ((ep->version_type & MSIQ_TYPE_MASK) == 0)
998 return 0;
999
1000 type = (ep->version_type & MSIQ_TYPE_MASK) >> MSIQ_TYPE_SHIFT;
1001 if (unlikely(type != MSIQ_TYPE_MSI32 &&
1002 type != MSIQ_TYPE_MSI64))
1003 return -EINVAL;
1004
1005 *msi = ep->msi_data;
1006
1007 err = pci_sun4v_msi_setstate(pbm->devhandle,
1008 ep->msi_data /* msi_num */,
1009 HV_MSISTATE_IDLE);
1010 if (unlikely(err))
1011 return -ENXIO;
1012
1013 /* Clear the entry. */
1014 ep->version_type &= ~MSIQ_TYPE_MASK;
1015
1016 (*head) += sizeof(struct pci_sun4v_msiq_entry);
1017 if (*head >=
1018 (pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry)))
1019 *head = 0;
1020
1021 return 1;
1022 }
1023
1024 static int pci_sun4v_set_head(struct pci_pbm_info *pbm, unsigned long msiqid,
1025 unsigned long head)
1026 {
1027 unsigned long err;
1028
1029 err = pci_sun4v_msiq_sethead(pbm->devhandle, msiqid, head);
1030 if (unlikely(err))
1031 return -EINVAL;
1032
1033 return 0;
1034 }
1035
1036 static int pci_sun4v_msi_setup(struct pci_pbm_info *pbm, unsigned long msiqid,
1037 unsigned long msi, int is_msi64)
1038 {
1039 if (pci_sun4v_msi_setmsiq(pbm->devhandle, msi, msiqid,
1040 (is_msi64 ?
1041 HV_MSITYPE_MSI64 : HV_MSITYPE_MSI32)))
1042 return -ENXIO;
1043 if (pci_sun4v_msi_setstate(pbm->devhandle, msi, HV_MSISTATE_IDLE))
1044 return -ENXIO;
1045 if (pci_sun4v_msi_setvalid(pbm->devhandle, msi, HV_MSIVALID_VALID))
1046 return -ENXIO;
1047 return 0;
1048 }
1049
1050 static int pci_sun4v_msi_teardown(struct pci_pbm_info *pbm, unsigned long msi)
1051 {
1052 unsigned long err, msiqid;
1053
1054 err = pci_sun4v_msi_getmsiq(pbm->devhandle, msi, &msiqid);
1055 if (err)
1056 return -ENXIO;
1057
1058 pci_sun4v_msi_setvalid(pbm->devhandle, msi, HV_MSIVALID_INVALID);
1059
1060 return 0;
1061 }
1062
1063 static int pci_sun4v_msiq_alloc(struct pci_pbm_info *pbm)
1064 {
1065 unsigned long q_size, alloc_size, pages, order;
1066 int i;
1067
1068 q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
1069 alloc_size = (pbm->msiq_num * q_size);
1070 order = get_order(alloc_size);
1071 pages = __get_free_pages(GFP_KERNEL | __GFP_COMP, order);
1072 if (pages == 0UL) {
1073 printk(KERN_ERR "MSI: Cannot allocate MSI queues (o=%lu).\n",
1074 order);
1075 return -ENOMEM;
1076 }
1077 memset((char *)pages, 0, PAGE_SIZE << order);
1078 pbm->msi_queues = (void *) pages;
1079
1080 for (i = 0; i < pbm->msiq_num; i++) {
1081 unsigned long err, base = __pa(pages + (i * q_size));
1082 unsigned long ret1, ret2;
1083
1084 err = pci_sun4v_msiq_conf(pbm->devhandle,
1085 pbm->msiq_first + i,
1086 base, pbm->msiq_ent_count);
1087 if (err) {
1088 printk(KERN_ERR "MSI: msiq register fails (err=%lu)\n",
1089 err);
1090 goto h_error;
1091 }
1092
1093 err = pci_sun4v_msiq_info(pbm->devhandle,
1094 pbm->msiq_first + i,
1095 &ret1, &ret2);
1096 if (err) {
1097 printk(KERN_ERR "MSI: Cannot read msiq (err=%lu)\n",
1098 err);
1099 goto h_error;
1100 }
1101 if (ret1 != base || ret2 != pbm->msiq_ent_count) {
1102 printk(KERN_ERR "MSI: Bogus qconf "
1103 "expected[%lx:%x] got[%lx:%lx]\n",
1104 base, pbm->msiq_ent_count,
1105 ret1, ret2);
1106 goto h_error;
1107 }
1108 }
1109
1110 return 0;
1111
1112 h_error:
1113 free_pages(pages, order);
1114 return -EINVAL;
1115 }
1116
1117 static void pci_sun4v_msiq_free(struct pci_pbm_info *pbm)
1118 {
1119 unsigned long q_size, alloc_size, pages, order;
1120 int i;
1121
1122 for (i = 0; i < pbm->msiq_num; i++) {
1123 unsigned long msiqid = pbm->msiq_first + i;
1124
1125 (void) pci_sun4v_msiq_conf(pbm->devhandle, msiqid, 0UL, 0);
1126 }
1127
1128 q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
1129 alloc_size = (pbm->msiq_num * q_size);
1130 order = get_order(alloc_size);
1131
1132 pages = (unsigned long) pbm->msi_queues;
1133
1134 free_pages(pages, order);
1135
1136 pbm->msi_queues = NULL;
1137 }
1138
1139 static int pci_sun4v_msiq_build_irq(struct pci_pbm_info *pbm,
1140 unsigned long msiqid,
1141 unsigned long devino)
1142 {
1143 unsigned int irq = sun4v_build_irq(pbm->devhandle, devino);
1144
1145 if (!irq)
1146 return -ENOMEM;
1147
1148 if (pci_sun4v_msiq_setvalid(pbm->devhandle, msiqid, HV_MSIQ_VALID))
1149 return -EINVAL;
1150 if (pci_sun4v_msiq_setstate(pbm->devhandle, msiqid, HV_MSIQSTATE_IDLE))
1151 return -EINVAL;
1152
1153 return irq;
1154 }
1155
1156 static const struct sparc64_msiq_ops pci_sun4v_msiq_ops = {
1157 .get_head = pci_sun4v_get_head,
1158 .dequeue_msi = pci_sun4v_dequeue_msi,
1159 .set_head = pci_sun4v_set_head,
1160 .msi_setup = pci_sun4v_msi_setup,
1161 .msi_teardown = pci_sun4v_msi_teardown,
1162 .msiq_alloc = pci_sun4v_msiq_alloc,
1163 .msiq_free = pci_sun4v_msiq_free,
1164 .msiq_build_irq = pci_sun4v_msiq_build_irq,
1165 };
1166
1167 static void pci_sun4v_msi_init(struct pci_pbm_info *pbm)
1168 {
1169 sparc64_pbm_msi_init(pbm, &pci_sun4v_msiq_ops);
1170 }
1171 #else /* CONFIG_PCI_MSI */
1172 static void pci_sun4v_msi_init(struct pci_pbm_info *pbm)
1173 {
1174 }
1175 #endif /* !(CONFIG_PCI_MSI) */
1176
1177 static int pci_sun4v_pbm_init(struct pci_pbm_info *pbm,
1178 struct platform_device *op, u32 devhandle)
1179 {
1180 struct device_node *dp = op->dev.of_node;
1181 int err;
1182
1183 pbm->numa_node = of_node_to_nid(dp);
1184
1185 pbm->pci_ops = &sun4v_pci_ops;
1186 pbm->config_space_reg_bits = 12;
1187
1188 pbm->index = pci_num_pbms++;
1189
1190 pbm->op = op;
1191
1192 pbm->devhandle = devhandle;
1193
1194 pbm->name = dp->full_name;
1195
1196 printk("%s: SUN4V PCI Bus Module\n", pbm->name);
1197 printk("%s: On NUMA node %d\n", pbm->name, pbm->numa_node);
1198
1199 pci_determine_mem_io_space(pbm);
1200
1201 pci_get_pbm_props(pbm);
1202
1203 err = pci_sun4v_iommu_init(pbm);
1204 if (err)
1205 return err;
1206
1207 pci_sun4v_msi_init(pbm);
1208
1209 pci_sun4v_scan_bus(pbm, &op->dev);
1210
1211 /* if atu_init fails its not complete failure.
1212 * we can still continue using legacy iommu.
1213 */
1214 if (pbm->iommu->atu) {
1215 err = pci_sun4v_atu_init(pbm);
1216 if (err) {
1217 kfree(pbm->iommu->atu);
1218 pbm->iommu->atu = NULL;
1219 pr_err(PFX "ATU init failed, err=%d\n", err);
1220 }
1221 }
1222
1223 pbm->next = pci_pbm_root;
1224 pci_pbm_root = pbm;
1225
1226 return 0;
1227 }
1228
1229 static int pci_sun4v_probe(struct platform_device *op)
1230 {
1231 const struct linux_prom64_registers *regs;
1232 static int hvapi_negotiated = 0;
1233 struct pci_pbm_info *pbm;
1234 struct device_node *dp;
1235 struct iommu *iommu;
1236 struct atu *atu;
1237 u32 devhandle;
1238 int i, err = -ENODEV;
1239 static bool hv_atu = true;
1240
1241 dp = op->dev.of_node;
1242
1243 if (!hvapi_negotiated++) {
1244 for (i = 0; i < ARRAY_SIZE(vpci_versions); i++) {
1245 vpci_major = vpci_versions[i].major;
1246 vpci_minor = vpci_versions[i].minor;
1247
1248 err = sun4v_hvapi_register(HV_GRP_PCI, vpci_major,
1249 &vpci_minor);
1250 if (!err)
1251 break;
1252 }
1253
1254 if (err) {
1255 pr_err(PFX "Could not register hvapi, err=%d\n", err);
1256 return err;
1257 }
1258 pr_info(PFX "Registered hvapi major[%lu] minor[%lu]\n",
1259 vpci_major, vpci_minor);
1260
1261 err = sun4v_hvapi_register(HV_GRP_ATU, vatu_major, &vatu_minor);
1262 if (err) {
1263 /* don't return an error if we fail to register the
1264 * ATU group, but ATU hcalls won't be available.
1265 */
1266 hv_atu = false;
1267 pr_err(PFX "Could not register hvapi ATU err=%d\n",
1268 err);
1269 } else {
1270 pr_info(PFX "Registered hvapi ATU major[%lu] minor[%lu]\n",
1271 vatu_major, vatu_minor);
1272 }
1273
1274 dma_ops = &sun4v_dma_ops;
1275 }
1276
1277 regs = of_get_property(dp, "reg", NULL);
1278 err = -ENODEV;
1279 if (!regs) {
1280 printk(KERN_ERR PFX "Could not find config registers\n");
1281 goto out_err;
1282 }
1283 devhandle = (regs->phys_addr >> 32UL) & 0x0fffffff;
1284
1285 err = -ENOMEM;
1286 if (!iommu_batch_initialized) {
1287 for_each_possible_cpu(i) {
1288 unsigned long page = get_zeroed_page(GFP_KERNEL);
1289
1290 if (!page)
1291 goto out_err;
1292
1293 per_cpu(iommu_batch, i).pglist = (u64 *) page;
1294 }
1295 iommu_batch_initialized = 1;
1296 }
1297
1298 pbm = kzalloc(sizeof(*pbm), GFP_KERNEL);
1299 if (!pbm) {
1300 printk(KERN_ERR PFX "Could not allocate pci_pbm_info\n");
1301 goto out_err;
1302 }
1303
1304 iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL);
1305 if (!iommu) {
1306 printk(KERN_ERR PFX "Could not allocate pbm iommu\n");
1307 goto out_free_controller;
1308 }
1309
1310 pbm->iommu = iommu;
1311 iommu->atu = NULL;
1312 if (hv_atu) {
1313 atu = kzalloc(sizeof(*atu), GFP_KERNEL);
1314 if (!atu)
1315 pr_err(PFX "Could not allocate atu\n");
1316 else
1317 iommu->atu = atu;
1318 }
1319
1320 err = pci_sun4v_pbm_init(pbm, op, devhandle);
1321 if (err)
1322 goto out_free_iommu;
1323
1324 dev_set_drvdata(&op->dev, pbm);
1325
1326 return 0;
1327
1328 out_free_iommu:
1329 kfree(iommu->atu);
1330 kfree(pbm->iommu);
1331
1332 out_free_controller:
1333 kfree(pbm);
1334
1335 out_err:
1336 return err;
1337 }
1338
1339 static const struct of_device_id pci_sun4v_match[] = {
1340 {
1341 .name = "pci",
1342 .compatible = "SUNW,sun4v-pci",
1343 },
1344 {},
1345 };
1346
1347 static struct platform_driver pci_sun4v_driver = {
1348 .driver = {
1349 .name = DRIVER_NAME,
1350 .of_match_table = pci_sun4v_match,
1351 },
1352 .probe = pci_sun4v_probe,
1353 };
1354
1355 static int __init pci_sun4v_init(void)
1356 {
1357 return platform_driver_register(&pci_sun4v_driver);
1358 }
1359
1360 subsys_initcall(pci_sun4v_init);
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