1 /* smp.c: Sparc64 SMP support.
3 * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net)
6 #include <linux/export.h>
7 #include <linux/kernel.h>
8 #include <linux/sched/mm.h>
9 #include <linux/sched/hotplug.h>
11 #include <linux/pagemap.h>
12 #include <linux/threads.h>
13 #include <linux/smp.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel_stat.h>
16 #include <linux/delay.h>
17 #include <linux/init.h>
18 #include <linux/spinlock.h>
20 #include <linux/seq_file.h>
21 #include <linux/cache.h>
22 #include <linux/jiffies.h>
23 #include <linux/profile.h>
24 #include <linux/bootmem.h>
25 #include <linux/vmalloc.h>
26 #include <linux/ftrace.h>
27 #include <linux/cpu.h>
28 #include <linux/slab.h>
29 #include <linux/kgdb.h>
32 #include <asm/ptrace.h>
33 #include <linux/atomic.h>
34 #include <asm/tlbflush.h>
35 #include <asm/mmu_context.h>
36 #include <asm/cpudata.h>
37 #include <asm/hvtramp.h>
39 #include <asm/timer.h>
40 #include <asm/setup.h>
43 #include <asm/irq_regs.h>
45 #include <asm/pgtable.h>
46 #include <asm/oplib.h>
47 #include <linux/uaccess.h>
48 #include <asm/starfire.h>
50 #include <asm/sections.h>
52 #include <asm/mdesc.h>
54 #include <asm/hypervisor.h>
60 DEFINE_PER_CPU(cpumask_t
, cpu_sibling_map
) = CPU_MASK_NONE
;
61 cpumask_t cpu_core_map
[NR_CPUS
] __read_mostly
=
62 { [0 ... NR_CPUS
-1] = CPU_MASK_NONE
};
64 cpumask_t cpu_core_sib_map
[NR_CPUS
] __read_mostly
= {
65 [0 ... NR_CPUS
-1] = CPU_MASK_NONE
};
67 cpumask_t cpu_core_sib_cache_map
[NR_CPUS
] __read_mostly
= {
68 [0 ... NR_CPUS
- 1] = CPU_MASK_NONE
};
70 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map
);
71 EXPORT_SYMBOL(cpu_core_map
);
72 EXPORT_SYMBOL(cpu_core_sib_map
);
73 EXPORT_SYMBOL(cpu_core_sib_cache_map
);
75 static cpumask_t smp_commenced_mask
;
77 static DEFINE_PER_CPU(bool, poke
);
80 void smp_info(struct seq_file
*m
)
84 seq_printf(m
, "State:\n");
85 for_each_online_cpu(i
)
86 seq_printf(m
, "CPU%d:\t\tonline\n", i
);
89 void smp_bogo(struct seq_file
*m
)
93 for_each_online_cpu(i
)
95 "Cpu%dClkTck\t: %016lx\n",
96 i
, cpu_data(i
).clock_tick
);
99 extern void setup_sparc64_timer(void);
101 static volatile unsigned long callin_flag
= 0;
103 void smp_callin(void)
105 int cpuid
= hard_smp_processor_id();
107 __local_per_cpu_offset
= __per_cpu_offset(cpuid
);
109 if (tlb_type
== hypervisor
)
110 sun4v_ktsb_register();
114 setup_sparc64_timer();
116 if (cheetah_pcache_forced_on
)
117 cheetah_enable_pcache();
120 __asm__
__volatile__("membar #Sync\n\t"
121 "flush %%g6" : : : "memory");
123 /* Clear this or we will die instantly when we
124 * schedule back to this idler...
126 current_thread_info()->new_child
= 0;
128 /* Attach to the address space of init_task. */
130 current
->active_mm
= &init_mm
;
132 /* inform the notifiers about the new cpu */
133 notify_cpu_starting(cpuid
);
135 while (!cpumask_test_cpu(cpuid
, &smp_commenced_mask
))
138 set_cpu_online(cpuid
, true);
140 /* idle thread is expected to have preempt disabled */
145 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE
);
150 printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
151 panic("SMP bolixed\n");
154 /* This tick register synchronization scheme is taken entirely from
155 * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit.
157 * The only change I've made is to rework it so that the master
158 * initiates the synchonization instead of the slave. -DaveM
162 #define SLAVE (SMP_CACHE_BYTES/sizeof(unsigned long))
164 #define NUM_ROUNDS 64 /* magic value */
165 #define NUM_ITERS 5 /* likewise */
167 static DEFINE_RAW_SPINLOCK(itc_sync_lock
);
168 static unsigned long go
[SLAVE
+ 1];
170 #define DEBUG_TICK_SYNC 0
172 static inline long get_delta (long *rt
, long *master
)
174 unsigned long best_t0
= 0, best_t1
= ~0UL, best_tm
= 0;
175 unsigned long tcenter
, t0
, t1
, tm
;
178 for (i
= 0; i
< NUM_ITERS
; i
++) {
179 t0
= tick_ops
->get_tick();
181 membar_safe("#StoreLoad");
182 while (!(tm
= go
[SLAVE
]))
186 t1
= tick_ops
->get_tick();
188 if (t1
- t0
< best_t1
- best_t0
)
189 best_t0
= t0
, best_t1
= t1
, best_tm
= tm
;
192 *rt
= best_t1
- best_t0
;
193 *master
= best_tm
- best_t0
;
195 /* average best_t0 and best_t1 without overflow: */
196 tcenter
= (best_t0
/2 + best_t1
/2);
197 if (best_t0
% 2 + best_t1
% 2 == 2)
199 return tcenter
- best_tm
;
202 void smp_synchronize_tick_client(void)
204 long i
, delta
, adj
, adjust_latency
= 0, done
= 0;
205 unsigned long flags
, rt
, master_time_stamp
;
208 long rt
; /* roundtrip time */
209 long master
; /* master's timestamp */
210 long diff
; /* difference between midpoint and master's timestamp */
211 long lat
; /* estimate of itc adjustment latency */
220 local_irq_save(flags
);
222 for (i
= 0; i
< NUM_ROUNDS
; i
++) {
223 delta
= get_delta(&rt
, &master_time_stamp
);
225 done
= 1; /* let's lock on to this... */
229 adjust_latency
+= -delta
;
230 adj
= -delta
+ adjust_latency
/4;
234 tick_ops
->add_tick(adj
);
238 t
[i
].master
= master_time_stamp
;
240 t
[i
].lat
= adjust_latency
/4;
244 local_irq_restore(flags
);
247 for (i
= 0; i
< NUM_ROUNDS
; i
++)
248 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
249 t
[i
].rt
, t
[i
].master
, t
[i
].diff
, t
[i
].lat
);
252 printk(KERN_INFO
"CPU %d: synchronized TICK with master CPU "
253 "(last diff %ld cycles, maxerr %lu cycles)\n",
254 smp_processor_id(), delta
, rt
);
257 static void smp_start_sync_tick_client(int cpu
);
259 static void smp_synchronize_one_tick(int cpu
)
261 unsigned long flags
, i
;
265 smp_start_sync_tick_client(cpu
);
267 /* wait for client to be ready */
271 /* now let the client proceed into his loop */
273 membar_safe("#StoreLoad");
275 raw_spin_lock_irqsave(&itc_sync_lock
, flags
);
277 for (i
= 0; i
< NUM_ROUNDS
*NUM_ITERS
; i
++) {
282 go
[SLAVE
] = tick_ops
->get_tick();
283 membar_safe("#StoreLoad");
286 raw_spin_unlock_irqrestore(&itc_sync_lock
, flags
);
289 #if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
290 static void ldom_startcpu_cpuid(unsigned int cpu
, unsigned long thread_reg
,
293 extern unsigned long sparc64_ttable_tl0
;
294 extern unsigned long kern_locked_tte_data
;
295 struct hvtramp_descr
*hdesc
;
296 unsigned long trampoline_ra
;
297 struct trap_per_cpu
*tb
;
298 u64 tte_vaddr
, tte_data
;
299 unsigned long hv_err
;
302 hdesc
= kzalloc(sizeof(*hdesc
) +
303 (sizeof(struct hvtramp_mapping
) *
304 num_kernel_image_mappings
- 1),
307 printk(KERN_ERR
"ldom_startcpu_cpuid: Cannot allocate "
314 hdesc
->num_mappings
= num_kernel_image_mappings
;
316 tb
= &trap_block
[cpu
];
318 hdesc
->fault_info_va
= (unsigned long) &tb
->fault_info
;
319 hdesc
->fault_info_pa
= kimage_addr_to_ra(&tb
->fault_info
);
321 hdesc
->thread_reg
= thread_reg
;
323 tte_vaddr
= (unsigned long) KERNBASE
;
324 tte_data
= kern_locked_tte_data
;
326 for (i
= 0; i
< hdesc
->num_mappings
; i
++) {
327 hdesc
->maps
[i
].vaddr
= tte_vaddr
;
328 hdesc
->maps
[i
].tte
= tte_data
;
329 tte_vaddr
+= 0x400000;
330 tte_data
+= 0x400000;
333 trampoline_ra
= kimage_addr_to_ra(hv_cpu_startup
);
335 hv_err
= sun4v_cpu_start(cpu
, trampoline_ra
,
336 kimage_addr_to_ra(&sparc64_ttable_tl0
),
339 printk(KERN_ERR
"ldom_startcpu_cpuid: sun4v_cpu_start() "
340 "gives error %lu\n", hv_err
);
344 extern unsigned long sparc64_cpu_startup
;
346 /* The OBP cpu startup callback truncates the 3rd arg cookie to
347 * 32-bits (I think) so to be safe we have it read the pointer
348 * contained here so we work on >4GB machines. -DaveM
350 static struct thread_info
*cpu_new_thread
= NULL
;
352 static int smp_boot_one_cpu(unsigned int cpu
, struct task_struct
*idle
)
354 unsigned long entry
=
355 (unsigned long)(&sparc64_cpu_startup
);
356 unsigned long cookie
=
357 (unsigned long)(&cpu_new_thread
);
362 cpu_new_thread
= task_thread_info(idle
);
364 if (tlb_type
== hypervisor
) {
365 #if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
366 if (ldom_domaining_enabled
)
367 ldom_startcpu_cpuid(cpu
,
368 (unsigned long) cpu_new_thread
,
372 prom_startcpu_cpuid(cpu
, entry
, cookie
);
374 struct device_node
*dp
= of_find_node_by_cpuid(cpu
);
376 prom_startcpu(dp
->phandle
, entry
, cookie
);
379 for (timeout
= 0; timeout
< 50000; timeout
++) {
388 printk("Processor %d is stuck.\n", cpu
);
391 cpu_new_thread
= NULL
;
398 static void spitfire_xcall_helper(u64 data0
, u64 data1
, u64 data2
, u64 pstate
, unsigned long cpu
)
403 if (this_is_starfire
) {
404 /* map to real upaid */
405 cpu
= (((cpu
& 0x3c) << 1) |
406 ((cpu
& 0x40) >> 4) |
410 target
= (cpu
<< 14) | 0x70;
412 /* Ok, this is the real Spitfire Errata #54.
413 * One must read back from a UDB internal register
414 * after writes to the UDB interrupt dispatch, but
415 * before the membar Sync for that write.
416 * So we use the high UDB control register (ASI 0x7f,
417 * ADDR 0x20) for the dummy read. -DaveM
420 __asm__
__volatile__(
421 "wrpr %1, %2, %%pstate\n\t"
422 "stxa %4, [%0] %3\n\t"
423 "stxa %5, [%0+%8] %3\n\t"
425 "stxa %6, [%0+%8] %3\n\t"
427 "stxa %%g0, [%7] %3\n\t"
430 "ldxa [%%g1] 0x7f, %%g0\n\t"
433 : "r" (pstate
), "i" (PSTATE_IE
), "i" (ASI_INTR_W
),
434 "r" (data0
), "r" (data1
), "r" (data2
), "r" (target
),
435 "r" (0x10), "0" (tmp
)
438 /* NOTE: PSTATE_IE is still clear. */
441 __asm__
__volatile__("ldxa [%%g0] %1, %0"
443 : "i" (ASI_INTR_DISPATCH_STAT
));
445 __asm__
__volatile__("wrpr %0, 0x0, %%pstate"
452 } while (result
& 0x1);
453 __asm__
__volatile__("wrpr %0, 0x0, %%pstate"
456 printk("CPU[%d]: mondo stuckage result[%016llx]\n",
457 smp_processor_id(), result
);
464 static void spitfire_xcall_deliver(struct trap_per_cpu
*tb
, int cnt
)
466 u64
*mondo
, data0
, data1
, data2
;
471 __asm__
__volatile__("rdpr %%pstate, %0" : "=r" (pstate
));
472 cpu_list
= __va(tb
->cpu_list_pa
);
473 mondo
= __va(tb
->cpu_mondo_block_pa
);
477 for (i
= 0; i
< cnt
; i
++)
478 spitfire_xcall_helper(data0
, data1
, data2
, pstate
, cpu_list
[i
]);
481 /* Cheetah now allows to send the whole 64-bytes of data in the interrupt
482 * packet, but we have no use for that. However we do take advantage of
483 * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
485 static void cheetah_xcall_deliver(struct trap_per_cpu
*tb
, int cnt
)
487 int nack_busy_id
, is_jbus
, need_more
;
488 u64
*mondo
, pstate
, ver
, busy_mask
;
491 cpu_list
= __va(tb
->cpu_list_pa
);
492 mondo
= __va(tb
->cpu_mondo_block_pa
);
494 /* Unfortunately, someone at Sun had the brilliant idea to make the
495 * busy/nack fields hard-coded by ITID number for this Ultra-III
496 * derivative processor.
498 __asm__ ("rdpr %%ver, %0" : "=r" (ver
));
499 is_jbus
= ((ver
>> 32) == __JALAPENO_ID
||
500 (ver
>> 32) == __SERRANO_ID
);
502 __asm__
__volatile__("rdpr %%pstate, %0" : "=r" (pstate
));
506 __asm__
__volatile__("wrpr %0, %1, %%pstate\n\t"
507 : : "r" (pstate
), "i" (PSTATE_IE
));
509 /* Setup the dispatch data registers. */
510 __asm__
__volatile__("stxa %0, [%3] %6\n\t"
511 "stxa %1, [%4] %6\n\t"
512 "stxa %2, [%5] %6\n\t"
515 : "r" (mondo
[0]), "r" (mondo
[1]), "r" (mondo
[2]),
516 "r" (0x40), "r" (0x50), "r" (0x60),
524 for (i
= 0; i
< cnt
; i
++) {
531 target
= (nr
<< 14) | 0x70;
533 busy_mask
|= (0x1UL
<< (nr
* 2));
535 target
|= (nack_busy_id
<< 24);
536 busy_mask
|= (0x1UL
<<
539 __asm__
__volatile__(
540 "stxa %%g0, [%0] %1\n\t"
543 : "r" (target
), "i" (ASI_INTR_W
));
545 if (nack_busy_id
== 32) {
552 /* Now, poll for completion. */
554 u64 dispatch_stat
, nack_mask
;
557 stuck
= 100000 * nack_busy_id
;
558 nack_mask
= busy_mask
<< 1;
560 __asm__
__volatile__("ldxa [%%g0] %1, %0"
561 : "=r" (dispatch_stat
)
562 : "i" (ASI_INTR_DISPATCH_STAT
));
563 if (!(dispatch_stat
& (busy_mask
| nack_mask
))) {
564 __asm__
__volatile__("wrpr %0, 0x0, %%pstate"
566 if (unlikely(need_more
)) {
568 for (i
= 0; i
< cnt
; i
++) {
569 if (cpu_list
[i
] == 0xffff)
571 cpu_list
[i
] = 0xffff;
582 } while (dispatch_stat
& busy_mask
);
584 __asm__
__volatile__("wrpr %0, 0x0, %%pstate"
587 if (dispatch_stat
& busy_mask
) {
588 /* Busy bits will not clear, continue instead
589 * of freezing up on this cpu.
591 printk("CPU[%d]: mondo stuckage result[%016llx]\n",
592 smp_processor_id(), dispatch_stat
);
594 int i
, this_busy_nack
= 0;
596 /* Delay some random time with interrupts enabled
597 * to prevent deadlock.
599 udelay(2 * nack_busy_id
);
601 /* Clear out the mask bits for cpus which did not
604 for (i
= 0; i
< cnt
; i
++) {
612 check_mask
= (0x2UL
<< (2*nr
));
614 check_mask
= (0x2UL
<<
616 if ((dispatch_stat
& check_mask
) == 0)
617 cpu_list
[i
] = 0xffff;
619 if (this_busy_nack
== 64)
628 #define CPU_MONDO_COUNTER(cpuid) (cpu_mondo_counter[cpuid])
629 #define MONDO_USEC_WAIT_MIN 2
630 #define MONDO_USEC_WAIT_MAX 100
631 #define MONDO_RETRY_LIMIT 500000
633 /* Multi-cpu list version.
635 * Deliver xcalls to 'cnt' number of cpus in 'cpu_list'.
636 * Sometimes not all cpus receive the mondo, requiring us to re-send
637 * the mondo until all cpus have received, or cpus are truly stuck
638 * unable to receive mondo, and we timeout.
639 * Occasionally a target cpu strand is borrowed briefly by hypervisor to
640 * perform guest service, such as PCIe error handling. Consider the
641 * service time, 1 second overall wait is reasonable for 1 cpu.
642 * Here two in-between mondo check wait time are defined: 2 usec for
643 * single cpu quick turn around and up to 100usec for large cpu count.
644 * Deliver mondo to large number of cpus could take longer, we adjusts
645 * the retry count as long as target cpus are making forward progress.
647 static void hypervisor_xcall_deliver(struct trap_per_cpu
*tb
, int cnt
)
649 int this_cpu
, tot_cpus
, prev_sent
, i
, rem
;
650 int usec_wait
, retries
, tot_retries
;
651 u16 first_cpu
= 0xffff;
652 unsigned long xc_rcvd
= 0;
653 unsigned long status
;
654 int ecpuerror_id
= 0;
659 this_cpu
= smp_processor_id();
660 cpu_list
= __va(tb
->cpu_list_pa
);
661 usec_wait
= cnt
* MONDO_USEC_WAIT_MIN
;
662 if (usec_wait
> MONDO_USEC_WAIT_MAX
)
663 usec_wait
= MONDO_USEC_WAIT_MAX
;
664 retries
= tot_retries
= 0;
669 int n_sent
, mondo_delivered
, target_cpu_busy
;
671 status
= sun4v_cpu_mondo_send(cnt
,
673 tb
->cpu_mondo_block_pa
);
675 /* HV_EOK means all cpus received the xcall, we're done. */
676 if (likely(status
== HV_EOK
))
679 /* If not these non-fatal errors, panic */
680 if (unlikely((status
!= HV_EWOULDBLOCK
) &&
681 (status
!= HV_ECPUERROR
) &&
682 (status
!= HV_ENOCPU
)))
685 /* First, see if we made any forward progress.
687 * Go through the cpu_list, count the target cpus that have
688 * received our mondo (n_sent), and those that did not (rem).
689 * Re-pack cpu_list with the cpus remain to be retried in the
690 * front - this simplifies tracking the truly stalled cpus.
692 * The hypervisor indicates successful sends by setting
693 * cpu list entries to the value 0xffff.
695 * EWOULDBLOCK means some target cpus did not receive the
696 * mondo and retry usually helps.
698 * ECPUERROR means at least one target cpu is in error state,
699 * it's usually safe to skip the faulty cpu and retry.
701 * ENOCPU means one of the target cpu doesn't belong to the
702 * domain, perhaps offlined which is unexpected, but not
703 * fatal and it's okay to skip the offlined cpu.
707 for (i
= 0; i
< cnt
; i
++) {
709 if (likely(cpu
== 0xffff)) {
711 } else if ((status
== HV_ECPUERROR
) &&
712 (sun4v_cpu_state(cpu
) == HV_CPU_STATE_ERROR
)) {
713 ecpuerror_id
= cpu
+ 1;
714 } else if (status
== HV_ENOCPU
&& !cpu_online(cpu
)) {
717 cpu_list
[rem
++] = cpu
;
721 /* No cpu remained, we're done. */
725 /* Otherwise, update the cpu count for retry. */
728 /* Record the overall number of mondos received by the
729 * first of the remaining cpus.
731 if (first_cpu
!= cpu_list
[0]) {
732 first_cpu
= cpu_list
[0];
733 xc_rcvd
= CPU_MONDO_COUNTER(first_cpu
);
736 /* Was any mondo delivered successfully? */
737 mondo_delivered
= (n_sent
> prev_sent
);
740 /* or, was any target cpu busy processing other mondos? */
741 target_cpu_busy
= (xc_rcvd
< CPU_MONDO_COUNTER(first_cpu
));
742 xc_rcvd
= CPU_MONDO_COUNTER(first_cpu
);
744 /* Retry count is for no progress. If we're making progress,
745 * reset the retry count.
747 if (likely(mondo_delivered
|| target_cpu_busy
)) {
748 tot_retries
+= retries
;
750 } else if (unlikely(retries
> MONDO_RETRY_LIMIT
)) {
751 goto fatal_mondo_timeout
;
754 /* Delay a little bit to let other cpus catch up on
755 * their cpu mondo queue work.
757 if (!mondo_delivered
)
764 if (unlikely(ecpuerror_id
> 0)) {
765 pr_crit("CPU[%d]: SUN4V mondo cpu error, target cpu(%d) was in error state\n",
766 this_cpu
, ecpuerror_id
- 1);
767 } else if (unlikely(enocpu_id
> 0)) {
768 pr_crit("CPU[%d]: SUN4V mondo cpu error, target cpu(%d) does not belong to the domain\n",
769 this_cpu
, enocpu_id
- 1);
774 /* fatal errors include bad alignment, etc */
775 pr_crit("CPU[%d]: Args were cnt(%d) cpulist_pa(%lx) mondo_block_pa(%lx)\n",
776 this_cpu
, tot_cpus
, tb
->cpu_list_pa
, tb
->cpu_mondo_block_pa
);
777 panic("Unexpected SUN4V mondo error %lu\n", status
);
780 /* some cpus being non-responsive to the cpu mondo */
781 pr_crit("CPU[%d]: SUN4V mondo timeout, cpu(%d) made no forward progress after %d retries. Total target cpus(%d).\n",
782 this_cpu
, first_cpu
, (tot_retries
+ retries
), tot_cpus
);
783 panic("SUN4V mondo timeout panic\n");
786 static void (*xcall_deliver_impl
)(struct trap_per_cpu
*, int);
788 static void xcall_deliver(u64 data0
, u64 data1
, u64 data2
, const cpumask_t
*mask
)
790 struct trap_per_cpu
*tb
;
791 int this_cpu
, i
, cnt
;
796 /* We have to do this whole thing with interrupts fully disabled.
797 * Otherwise if we send an xcall from interrupt context it will
798 * corrupt both our mondo block and cpu list state.
800 * One consequence of this is that we cannot use timeout mechanisms
801 * that depend upon interrupts being delivered locally. So, for
802 * example, we cannot sample jiffies and expect it to advance.
804 * Fortunately, udelay() uses %stick/%tick so we can use that.
806 local_irq_save(flags
);
808 this_cpu
= smp_processor_id();
809 tb
= &trap_block
[this_cpu
];
811 mondo
= __va(tb
->cpu_mondo_block_pa
);
817 cpu_list
= __va(tb
->cpu_list_pa
);
819 /* Setup the initial cpu list. */
821 for_each_cpu(i
, mask
) {
822 if (i
== this_cpu
|| !cpu_online(i
))
828 xcall_deliver_impl(tb
, cnt
);
830 local_irq_restore(flags
);
833 /* Send cross call to all processors mentioned in MASK_P
834 * except self. Really, there are only two cases currently,
835 * "cpu_online_mask" and "mm_cpumask(mm)".
837 static void smp_cross_call_masked(unsigned long *func
, u32 ctx
, u64 data1
, u64 data2
, const cpumask_t
*mask
)
839 u64 data0
= (((u64
)ctx
)<<32 | (((u64
)func
) & 0xffffffff));
841 xcall_deliver(data0
, data1
, data2
, mask
);
844 /* Send cross call to all processors except self. */
845 static void smp_cross_call(unsigned long *func
, u32 ctx
, u64 data1
, u64 data2
)
847 smp_cross_call_masked(func
, ctx
, data1
, data2
, cpu_online_mask
);
850 extern unsigned long xcall_sync_tick
;
852 static void smp_start_sync_tick_client(int cpu
)
854 xcall_deliver((u64
) &xcall_sync_tick
, 0, 0,
858 extern unsigned long xcall_call_function
;
860 void arch_send_call_function_ipi_mask(const struct cpumask
*mask
)
862 xcall_deliver((u64
) &xcall_call_function
, 0, 0, mask
);
865 extern unsigned long xcall_call_function_single
;
867 void arch_send_call_function_single_ipi(int cpu
)
869 xcall_deliver((u64
) &xcall_call_function_single
, 0, 0,
873 void __irq_entry
smp_call_function_client(int irq
, struct pt_regs
*regs
)
875 clear_softint(1 << irq
);
877 generic_smp_call_function_interrupt();
881 void __irq_entry
smp_call_function_single_client(int irq
, struct pt_regs
*regs
)
883 clear_softint(1 << irq
);
885 generic_smp_call_function_single_interrupt();
889 static void tsb_sync(void *info
)
891 struct trap_per_cpu
*tp
= &trap_block
[raw_smp_processor_id()];
892 struct mm_struct
*mm
= info
;
894 /* It is not valid to test "current->active_mm == mm" here.
896 * The value of "current" is not changed atomically with
897 * switch_mm(). But that's OK, we just need to check the
898 * current cpu's trap block PGD physical address.
900 if (tp
->pgd_paddr
== __pa(mm
->pgd
))
901 tsb_context_switch(mm
);
904 void smp_tsb_sync(struct mm_struct
*mm
)
906 smp_call_function_many(mm_cpumask(mm
), tsb_sync
, mm
, 1);
909 extern unsigned long xcall_flush_tlb_mm
;
910 extern unsigned long xcall_flush_tlb_page
;
911 extern unsigned long xcall_flush_tlb_kernel_range
;
912 extern unsigned long xcall_fetch_glob_regs
;
913 extern unsigned long xcall_fetch_glob_pmu
;
914 extern unsigned long xcall_fetch_glob_pmu_n4
;
915 extern unsigned long xcall_receive_signal
;
916 extern unsigned long xcall_new_mmu_context_version
;
918 extern unsigned long xcall_kgdb_capture
;
921 #ifdef DCACHE_ALIASING_POSSIBLE
922 extern unsigned long xcall_flush_dcache_page_cheetah
;
924 extern unsigned long xcall_flush_dcache_page_spitfire
;
926 static inline void __local_flush_dcache_page(struct page
*page
)
928 #ifdef DCACHE_ALIASING_POSSIBLE
929 __flush_dcache_page(page_address(page
),
930 ((tlb_type
== spitfire
) &&
931 page_mapping(page
) != NULL
));
933 if (page_mapping(page
) != NULL
&&
934 tlb_type
== spitfire
)
935 __flush_icache_page(__pa(page_address(page
)));
939 void smp_flush_dcache_page_impl(struct page
*page
, int cpu
)
943 if (tlb_type
== hypervisor
)
946 #ifdef CONFIG_DEBUG_DCFLUSH
947 atomic_inc(&dcpage_flushes
);
950 this_cpu
= get_cpu();
952 if (cpu
== this_cpu
) {
953 __local_flush_dcache_page(page
);
954 } else if (cpu_online(cpu
)) {
955 void *pg_addr
= page_address(page
);
958 if (tlb_type
== spitfire
) {
959 data0
= ((u64
)&xcall_flush_dcache_page_spitfire
);
960 if (page_mapping(page
) != NULL
)
961 data0
|= ((u64
)1 << 32);
962 } else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
963 #ifdef DCACHE_ALIASING_POSSIBLE
964 data0
= ((u64
)&xcall_flush_dcache_page_cheetah
);
968 xcall_deliver(data0
, __pa(pg_addr
),
969 (u64
) pg_addr
, cpumask_of(cpu
));
970 #ifdef CONFIG_DEBUG_DCFLUSH
971 atomic_inc(&dcpage_flushes_xcall
);
979 void flush_dcache_page_all(struct mm_struct
*mm
, struct page
*page
)
984 if (tlb_type
== hypervisor
)
989 #ifdef CONFIG_DEBUG_DCFLUSH
990 atomic_inc(&dcpage_flushes
);
993 pg_addr
= page_address(page
);
994 if (tlb_type
== spitfire
) {
995 data0
= ((u64
)&xcall_flush_dcache_page_spitfire
);
996 if (page_mapping(page
) != NULL
)
997 data0
|= ((u64
)1 << 32);
998 } else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
999 #ifdef DCACHE_ALIASING_POSSIBLE
1000 data0
= ((u64
)&xcall_flush_dcache_page_cheetah
);
1004 xcall_deliver(data0
, __pa(pg_addr
),
1005 (u64
) pg_addr
, cpu_online_mask
);
1006 #ifdef CONFIG_DEBUG_DCFLUSH
1007 atomic_inc(&dcpage_flushes_xcall
);
1010 __local_flush_dcache_page(page
);
1016 void kgdb_roundup_cpus(unsigned long flags
)
1018 smp_cross_call(&xcall_kgdb_capture
, 0, 0, 0);
1022 void smp_fetch_global_regs(void)
1024 smp_cross_call(&xcall_fetch_glob_regs
, 0, 0, 0);
1027 void smp_fetch_global_pmu(void)
1029 if (tlb_type
== hypervisor
&&
1030 sun4v_chip_type
>= SUN4V_CHIP_NIAGARA4
)
1031 smp_cross_call(&xcall_fetch_glob_pmu_n4
, 0, 0, 0);
1033 smp_cross_call(&xcall_fetch_glob_pmu
, 0, 0, 0);
1036 /* We know that the window frames of the user have been flushed
1037 * to the stack before we get here because all callers of us
1038 * are flush_tlb_*() routines, and these run after flush_cache_*()
1039 * which performs the flushw.
1041 * The SMP TLB coherency scheme we use works as follows:
1043 * 1) mm->cpu_vm_mask is a bit mask of which cpus an address
1044 * space has (potentially) executed on, this is the heuristic
1045 * we use to avoid doing cross calls.
1047 * Also, for flushing from kswapd and also for clones, we
1048 * use cpu_vm_mask as the list of cpus to make run the TLB.
1050 * 2) TLB context numbers are shared globally across all processors
1051 * in the system, this allows us to play several games to avoid
1054 * One invariant is that when a cpu switches to a process, and
1055 * that processes tsk->active_mm->cpu_vm_mask does not have the
1056 * current cpu's bit set, that tlb context is flushed locally.
1058 * If the address space is non-shared (ie. mm->count == 1) we avoid
1059 * cross calls when we want to flush the currently running process's
1060 * tlb state. This is done by clearing all cpu bits except the current
1061 * processor's in current->mm->cpu_vm_mask and performing the
1062 * flush locally only. This will force any subsequent cpus which run
1063 * this task to flush the context from the local tlb if the process
1064 * migrates to another cpu (again).
1066 * 3) For shared address spaces (threads) and swapping we bite the
1067 * bullet for most cases and perform the cross call (but only to
1068 * the cpus listed in cpu_vm_mask).
1070 * The performance gain from "optimizing" away the cross call for threads is
1071 * questionable (in theory the big win for threads is the massive sharing of
1072 * address space state across processors).
1075 /* This currently is only used by the hugetlb arch pre-fault
1076 * hook on UltraSPARC-III+ and later when changing the pagesize
1077 * bits of the context register for an address space.
1079 void smp_flush_tlb_mm(struct mm_struct
*mm
)
1081 u32 ctx
= CTX_HWBITS(mm
->context
);
1082 int cpu
= get_cpu();
1084 if (atomic_read(&mm
->mm_users
) == 1) {
1085 cpumask_copy(mm_cpumask(mm
), cpumask_of(cpu
));
1086 goto local_flush_and_out
;
1089 smp_cross_call_masked(&xcall_flush_tlb_mm
,
1093 local_flush_and_out
:
1094 __flush_tlb_mm(ctx
, SECONDARY_CONTEXT
);
1099 struct tlb_pending_info
{
1102 unsigned long *vaddrs
;
1105 static void tlb_pending_func(void *info
)
1107 struct tlb_pending_info
*t
= info
;
1109 __flush_tlb_pending(t
->ctx
, t
->nr
, t
->vaddrs
);
1112 void smp_flush_tlb_pending(struct mm_struct
*mm
, unsigned long nr
, unsigned long *vaddrs
)
1114 u32 ctx
= CTX_HWBITS(mm
->context
);
1115 struct tlb_pending_info info
;
1116 int cpu
= get_cpu();
1120 info
.vaddrs
= vaddrs
;
1122 if (mm
== current
->mm
&& atomic_read(&mm
->mm_users
) == 1)
1123 cpumask_copy(mm_cpumask(mm
), cpumask_of(cpu
));
1125 smp_call_function_many(mm_cpumask(mm
), tlb_pending_func
,
1128 __flush_tlb_pending(ctx
, nr
, vaddrs
);
1133 void smp_flush_tlb_page(struct mm_struct
*mm
, unsigned long vaddr
)
1135 unsigned long context
= CTX_HWBITS(mm
->context
);
1136 int cpu
= get_cpu();
1138 if (mm
== current
->mm
&& atomic_read(&mm
->mm_users
) == 1)
1139 cpumask_copy(mm_cpumask(mm
), cpumask_of(cpu
));
1141 smp_cross_call_masked(&xcall_flush_tlb_page
,
1144 __flush_tlb_page(context
, vaddr
);
1149 void smp_flush_tlb_kernel_range(unsigned long start
, unsigned long end
)
1152 end
= PAGE_ALIGN(end
);
1154 smp_cross_call(&xcall_flush_tlb_kernel_range
,
1157 __flush_tlb_kernel_range(start
, end
);
1162 /* #define CAPTURE_DEBUG */
1163 extern unsigned long xcall_capture
;
1165 static atomic_t smp_capture_depth
= ATOMIC_INIT(0);
1166 static atomic_t smp_capture_registry
= ATOMIC_INIT(0);
1167 static unsigned long penguins_are_doing_time
;
1169 void smp_capture(void)
1171 int result
= atomic_add_return(1, &smp_capture_depth
);
1174 int ncpus
= num_online_cpus();
1176 #ifdef CAPTURE_DEBUG
1177 printk("CPU[%d]: Sending penguins to jail...",
1178 smp_processor_id());
1180 penguins_are_doing_time
= 1;
1181 atomic_inc(&smp_capture_registry
);
1182 smp_cross_call(&xcall_capture
, 0, 0, 0);
1183 while (atomic_read(&smp_capture_registry
) != ncpus
)
1185 #ifdef CAPTURE_DEBUG
1191 void smp_release(void)
1193 if (atomic_dec_and_test(&smp_capture_depth
)) {
1194 #ifdef CAPTURE_DEBUG
1195 printk("CPU[%d]: Giving pardon to "
1196 "imprisoned penguins\n",
1197 smp_processor_id());
1199 penguins_are_doing_time
= 0;
1200 membar_safe("#StoreLoad");
1201 atomic_dec(&smp_capture_registry
);
1205 /* Imprisoned penguins run with %pil == PIL_NORMAL_MAX, but PSTATE_IE
1206 * set, so they can service tlb flush xcalls...
1208 extern void prom_world(int);
1210 void __irq_entry
smp_penguin_jailcell(int irq
, struct pt_regs
*regs
)
1212 clear_softint(1 << irq
);
1216 __asm__
__volatile__("flushw");
1218 atomic_inc(&smp_capture_registry
);
1219 membar_safe("#StoreLoad");
1220 while (penguins_are_doing_time
)
1222 atomic_dec(&smp_capture_registry
);
1228 /* /proc/profile writes can call this, don't __init it please. */
1229 int setup_profiling_timer(unsigned int multiplier
)
1234 void __init
smp_prepare_cpus(unsigned int max_cpus
)
1238 void smp_prepare_boot_cpu(void)
1242 void __init
smp_setup_processor_id(void)
1244 if (tlb_type
== spitfire
)
1245 xcall_deliver_impl
= spitfire_xcall_deliver
;
1246 else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
)
1247 xcall_deliver_impl
= cheetah_xcall_deliver
;
1249 xcall_deliver_impl
= hypervisor_xcall_deliver
;
1252 void __init
smp_fill_in_cpu_possible_map(void)
1254 int possible_cpus
= num_possible_cpus();
1257 if (possible_cpus
> nr_cpu_ids
)
1258 possible_cpus
= nr_cpu_ids
;
1260 for (i
= 0; i
< possible_cpus
; i
++)
1261 set_cpu_possible(i
, true);
1262 for (; i
< NR_CPUS
; i
++)
1263 set_cpu_possible(i
, false);
1266 void smp_fill_in_sib_core_maps(void)
1270 for_each_present_cpu(i
) {
1273 cpumask_clear(&cpu_core_map
[i
]);
1274 if (cpu_data(i
).core_id
== 0) {
1275 cpumask_set_cpu(i
, &cpu_core_map
[i
]);
1279 for_each_present_cpu(j
) {
1280 if (cpu_data(i
).core_id
==
1281 cpu_data(j
).core_id
)
1282 cpumask_set_cpu(j
, &cpu_core_map
[i
]);
1286 for_each_present_cpu(i
) {
1289 for_each_present_cpu(j
) {
1290 if (cpu_data(i
).max_cache_id
==
1291 cpu_data(j
).max_cache_id
)
1292 cpumask_set_cpu(j
, &cpu_core_sib_cache_map
[i
]);
1294 if (cpu_data(i
).sock_id
== cpu_data(j
).sock_id
)
1295 cpumask_set_cpu(j
, &cpu_core_sib_map
[i
]);
1299 for_each_present_cpu(i
) {
1302 cpumask_clear(&per_cpu(cpu_sibling_map
, i
));
1303 if (cpu_data(i
).proc_id
== -1) {
1304 cpumask_set_cpu(i
, &per_cpu(cpu_sibling_map
, i
));
1308 for_each_present_cpu(j
) {
1309 if (cpu_data(i
).proc_id
==
1310 cpu_data(j
).proc_id
)
1311 cpumask_set_cpu(j
, &per_cpu(cpu_sibling_map
, i
));
1316 int __cpu_up(unsigned int cpu
, struct task_struct
*tidle
)
1318 int ret
= smp_boot_one_cpu(cpu
, tidle
);
1321 cpumask_set_cpu(cpu
, &smp_commenced_mask
);
1322 while (!cpu_online(cpu
))
1324 if (!cpu_online(cpu
)) {
1327 /* On SUN4V, writes to %tick and %stick are
1330 if (tlb_type
!= hypervisor
)
1331 smp_synchronize_one_tick(cpu
);
1337 #ifdef CONFIG_HOTPLUG_CPU
1338 void cpu_play_dead(void)
1340 int cpu
= smp_processor_id();
1341 unsigned long pstate
;
1345 if (tlb_type
== hypervisor
) {
1346 struct trap_per_cpu
*tb
= &trap_block
[cpu
];
1348 sun4v_cpu_qconf(HV_CPU_QUEUE_CPU_MONDO
,
1349 tb
->cpu_mondo_pa
, 0);
1350 sun4v_cpu_qconf(HV_CPU_QUEUE_DEVICE_MONDO
,
1351 tb
->dev_mondo_pa
, 0);
1352 sun4v_cpu_qconf(HV_CPU_QUEUE_RES_ERROR
,
1353 tb
->resum_mondo_pa
, 0);
1354 sun4v_cpu_qconf(HV_CPU_QUEUE_NONRES_ERROR
,
1355 tb
->nonresum_mondo_pa
, 0);
1358 cpumask_clear_cpu(cpu
, &smp_commenced_mask
);
1359 membar_safe("#Sync");
1361 local_irq_disable();
1363 __asm__
__volatile__(
1364 "rdpr %%pstate, %0\n\t"
1365 "wrpr %0, %1, %%pstate"
1373 int __cpu_disable(void)
1375 int cpu
= smp_processor_id();
1379 for_each_cpu(i
, &cpu_core_map
[cpu
])
1380 cpumask_clear_cpu(cpu
, &cpu_core_map
[i
]);
1381 cpumask_clear(&cpu_core_map
[cpu
]);
1383 for_each_cpu(i
, &per_cpu(cpu_sibling_map
, cpu
))
1384 cpumask_clear_cpu(cpu
, &per_cpu(cpu_sibling_map
, i
));
1385 cpumask_clear(&per_cpu(cpu_sibling_map
, cpu
));
1394 /* Make sure no interrupts point to this cpu. */
1399 local_irq_disable();
1401 set_cpu_online(cpu
, false);
1408 void __cpu_die(unsigned int cpu
)
1412 for (i
= 0; i
< 100; i
++) {
1414 if (!cpumask_test_cpu(cpu
, &smp_commenced_mask
))
1418 if (cpumask_test_cpu(cpu
, &smp_commenced_mask
)) {
1419 printk(KERN_ERR
"CPU %u didn't die...\n", cpu
);
1421 #if defined(CONFIG_SUN_LDOMS)
1422 unsigned long hv_err
;
1426 hv_err
= sun4v_cpu_stop(cpu
);
1427 if (hv_err
== HV_EOK
) {
1428 set_cpu_present(cpu
, false);
1431 } while (--limit
> 0);
1433 printk(KERN_ERR
"sun4v_cpu_stop() fails err=%lu\n",
1441 void __init
smp_cpus_done(unsigned int max_cpus
)
1445 static void send_cpu_ipi(int cpu
)
1447 xcall_deliver((u64
) &xcall_receive_signal
,
1448 0, 0, cpumask_of(cpu
));
1451 void scheduler_poke(void)
1456 if (!__this_cpu_read(poke
))
1459 __this_cpu_write(poke
, false);
1460 set_softint(1 << PIL_SMP_RECEIVE_SIGNAL
);
1463 static unsigned long send_cpu_poke(int cpu
)
1465 unsigned long hv_err
;
1467 per_cpu(poke
, cpu
) = true;
1468 hv_err
= sun4v_cpu_poke(cpu
);
1469 if (hv_err
!= HV_EOK
) {
1470 per_cpu(poke
, cpu
) = false;
1471 pr_err_ratelimited("%s: sun4v_cpu_poke() fails err=%lu\n",
1478 void smp_send_reschedule(int cpu
)
1480 if (cpu
== smp_processor_id()) {
1481 WARN_ON_ONCE(preemptible());
1482 set_softint(1 << PIL_SMP_RECEIVE_SIGNAL
);
1486 /* Use cpu poke to resume idle cpu if supported. */
1487 if (cpu_poke
&& idle_cpu(cpu
)) {
1490 ret
= send_cpu_poke(cpu
);
1495 /* Use IPI in following cases:
1496 * - cpu poke not supported
1498 * - send_cpu_poke() returns with error
1503 void smp_init_cpu_poke(void)
1505 unsigned long major
;
1506 unsigned long minor
;
1509 if (tlb_type
!= hypervisor
)
1512 ret
= sun4v_hvapi_get(HV_GRP_CORE
, &major
, &minor
);
1514 pr_debug("HV_GRP_CORE is not registered\n");
1518 if (major
== 1 && minor
>= 6) {
1519 /* CPU POKE is registered. */
1524 pr_debug("CPU_POKE not supported\n");
1527 void __irq_entry
smp_receive_signal_client(int irq
, struct pt_regs
*regs
)
1529 clear_softint(1 << irq
);
1533 static void stop_this_cpu(void *dummy
)
1535 set_cpu_online(smp_processor_id(), false);
1539 void smp_send_stop(void)
1543 if (tlb_type
== hypervisor
) {
1544 int this_cpu
= smp_processor_id();
1545 #ifdef CONFIG_SERIAL_SUNHV
1546 sunhv_migrate_hvcons_irq(this_cpu
);
1548 for_each_online_cpu(cpu
) {
1549 if (cpu
== this_cpu
)
1552 set_cpu_online(cpu
, false);
1553 #ifdef CONFIG_SUN_LDOMS
1554 if (ldom_domaining_enabled
) {
1555 unsigned long hv_err
;
1556 hv_err
= sun4v_cpu_stop(cpu
);
1558 printk(KERN_ERR
"sun4v_cpu_stop() "
1559 "failed err=%lu\n", hv_err
);
1562 prom_stopcpu_cpuid(cpu
);
1565 smp_call_function(stop_this_cpu
, NULL
, 0);
1569 * pcpu_alloc_bootmem - NUMA friendly alloc_bootmem wrapper for percpu
1570 * @cpu: cpu to allocate for
1571 * @size: size allocation in bytes
1574 * Allocate @size bytes aligned at @align for cpu @cpu. This wrapper
1575 * does the right thing for NUMA regardless of the current
1579 * Pointer to the allocated area on success, NULL on failure.
1581 static void * __init
pcpu_alloc_bootmem(unsigned int cpu
, size_t size
,
1584 const unsigned long goal
= __pa(MAX_DMA_ADDRESS
);
1585 #ifdef CONFIG_NEED_MULTIPLE_NODES
1586 int node
= cpu_to_node(cpu
);
1589 if (!node_online(node
) || !NODE_DATA(node
)) {
1590 ptr
= __alloc_bootmem(size
, align
, goal
);
1591 pr_info("cpu %d has no node %d or node-local memory\n",
1593 pr_debug("per cpu data for cpu%d %lu bytes at %016lx\n",
1594 cpu
, size
, __pa(ptr
));
1596 ptr
= __alloc_bootmem_node(NODE_DATA(node
),
1598 pr_debug("per cpu data for cpu%d %lu bytes on node%d at "
1599 "%016lx\n", cpu
, size
, node
, __pa(ptr
));
1603 return __alloc_bootmem(size
, align
, goal
);
1607 static void __init
pcpu_free_bootmem(void *ptr
, size_t size
)
1609 free_bootmem(__pa(ptr
), size
);
1612 static int __init
pcpu_cpu_distance(unsigned int from
, unsigned int to
)
1614 if (cpu_to_node(from
) == cpu_to_node(to
))
1615 return LOCAL_DISTANCE
;
1617 return REMOTE_DISTANCE
;
1620 static void __init
pcpu_populate_pte(unsigned long addr
)
1622 pgd_t
*pgd
= pgd_offset_k(addr
);
1626 if (pgd_none(*pgd
)) {
1629 new = __alloc_bootmem(PAGE_SIZE
, PAGE_SIZE
, PAGE_SIZE
);
1630 pgd_populate(&init_mm
, pgd
, new);
1633 pud
= pud_offset(pgd
, addr
);
1634 if (pud_none(*pud
)) {
1637 new = __alloc_bootmem(PAGE_SIZE
, PAGE_SIZE
, PAGE_SIZE
);
1638 pud_populate(&init_mm
, pud
, new);
1641 pmd
= pmd_offset(pud
, addr
);
1642 if (!pmd_present(*pmd
)) {
1645 new = __alloc_bootmem(PAGE_SIZE
, PAGE_SIZE
, PAGE_SIZE
);
1646 pmd_populate_kernel(&init_mm
, pmd
, new);
1650 void __init
setup_per_cpu_areas(void)
1652 unsigned long delta
;
1656 if (pcpu_chosen_fc
!= PCPU_FC_PAGE
) {
1657 rc
= pcpu_embed_first_chunk(PERCPU_MODULE_RESERVE
,
1658 PERCPU_DYNAMIC_RESERVE
, 4 << 20,
1663 pr_warning("PERCPU: %s allocator failed (%d), "
1664 "falling back to page size\n",
1665 pcpu_fc_names
[pcpu_chosen_fc
], rc
);
1668 rc
= pcpu_page_first_chunk(PERCPU_MODULE_RESERVE
,
1673 panic("cannot initialize percpu area (err=%d)", rc
);
1675 delta
= (unsigned long)pcpu_base_addr
- (unsigned long)__per_cpu_start
;
1676 for_each_possible_cpu(cpu
)
1677 __per_cpu_offset(cpu
) = delta
+ pcpu_unit_offsets
[cpu
];
1679 /* Setup %g5 for the boot cpu. */
1680 __local_per_cpu_offset
= __per_cpu_offset(smp_processor_id());
1682 of_fill_in_cpu_data();
1683 if (tlb_type
== hypervisor
)
1684 mdesc_fill_in_cpu_data(cpu_all_mask
);