2 * arch/sparc64/mm/init.c
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 #include <linux/extable.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/string.h>
12 #include <linux/init.h>
13 #include <linux/bootmem.h>
15 #include <linux/hugetlb.h>
16 #include <linux/initrd.h>
17 #include <linux/swap.h>
18 #include <linux/pagemap.h>
19 #include <linux/poison.h>
21 #include <linux/seq_file.h>
22 #include <linux/kprobes.h>
23 #include <linux/cache.h>
24 #include <linux/sort.h>
25 #include <linux/ioport.h>
26 #include <linux/percpu.h>
27 #include <linux/memblock.h>
28 #include <linux/mmzone.h>
29 #include <linux/gfp.h>
33 #include <asm/pgalloc.h>
34 #include <asm/pgtable.h>
35 #include <asm/oplib.h>
36 #include <asm/iommu.h>
38 #include <linux/uaccess.h>
39 #include <asm/mmu_context.h>
40 #include <asm/tlbflush.h>
42 #include <asm/starfire.h>
44 #include <asm/spitfire.h>
45 #include <asm/sections.h>
47 #include <asm/hypervisor.h>
49 #include <asm/mdesc.h>
50 #include <asm/cpudata.h>
51 #include <asm/setup.h>
56 unsigned long kern_linear_pte_xor
[4] __read_mostly
;
57 static unsigned long page_cache4v_flag
;
59 /* A bitmap, two bits for every 256MB of physical memory. These two
60 * bits determine what page size we use for kernel linear
61 * translations. They form an index into kern_linear_pte_xor[]. The
62 * value in the indexed slot is XOR'd with the TLB miss virtual
63 * address to form the resulting TTE. The mapping is:
70 * All sun4v chips support 256MB pages. Only SPARC-T4 and later
71 * support 2GB pages, and hopefully future cpus will support the 16GB
72 * pages as well. For slots 2 and 3, we encode a 256MB TTE xor there
73 * if these larger page sizes are not supported by the cpu.
75 * It would be nice to determine this from the machine description
76 * 'cpu' properties, but we need to have this table setup before the
77 * MDESC is initialized.
80 #ifndef CONFIG_DEBUG_PAGEALLOC
81 /* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings.
82 * Space is allocated for this right after the trap table in
83 * arch/sparc64/kernel/head.S
85 extern struct tsb swapper_4m_tsb
[KERNEL_TSB4M_NENTRIES
];
87 extern struct tsb swapper_tsb
[KERNEL_TSB_NENTRIES
];
89 static unsigned long cpu_pgsz_mask
;
91 #define MAX_BANKS 1024
93 static struct linux_prom64_registers pavail
[MAX_BANKS
];
94 static int pavail_ents
;
96 u64 numa_latency
[MAX_NUMNODES
][MAX_NUMNODES
];
98 static int cmp_p64(const void *a
, const void *b
)
100 const struct linux_prom64_registers
*x
= a
, *y
= b
;
102 if (x
->phys_addr
> y
->phys_addr
)
104 if (x
->phys_addr
< y
->phys_addr
)
109 static void __init
read_obp_memory(const char *property
,
110 struct linux_prom64_registers
*regs
,
113 phandle node
= prom_finddevice("/memory");
114 int prop_size
= prom_getproplen(node
, property
);
117 ents
= prop_size
/ sizeof(struct linux_prom64_registers
);
118 if (ents
> MAX_BANKS
) {
119 prom_printf("The machine has more %s property entries than "
120 "this kernel can support (%d).\n",
121 property
, MAX_BANKS
);
125 ret
= prom_getproperty(node
, property
, (char *) regs
, prop_size
);
127 prom_printf("Couldn't get %s property from /memory.\n",
132 /* Sanitize what we got from the firmware, by page aligning
135 for (i
= 0; i
< ents
; i
++) {
136 unsigned long base
, size
;
138 base
= regs
[i
].phys_addr
;
139 size
= regs
[i
].reg_size
;
142 if (base
& ~PAGE_MASK
) {
143 unsigned long new_base
= PAGE_ALIGN(base
);
145 size
-= new_base
- base
;
146 if ((long) size
< 0L)
151 /* If it is empty, simply get rid of it.
152 * This simplifies the logic of the other
153 * functions that process these arrays.
155 memmove(®s
[i
], ®s
[i
+ 1],
156 (ents
- i
- 1) * sizeof(regs
[0]));
161 regs
[i
].phys_addr
= base
;
162 regs
[i
].reg_size
= size
;
167 sort(regs
, ents
, sizeof(struct linux_prom64_registers
),
171 /* Kernel physical address base and size in bytes. */
172 unsigned long kern_base __read_mostly
;
173 unsigned long kern_size __read_mostly
;
175 /* Initial ramdisk setup */
176 extern unsigned long sparc_ramdisk_image64
;
177 extern unsigned int sparc_ramdisk_image
;
178 extern unsigned int sparc_ramdisk_size
;
180 struct page
*mem_map_zero __read_mostly
;
181 EXPORT_SYMBOL(mem_map_zero
);
183 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly
;
185 unsigned long sparc64_kern_pri_context __read_mostly
;
186 unsigned long sparc64_kern_pri_nuc_bits __read_mostly
;
187 unsigned long sparc64_kern_sec_context __read_mostly
;
189 int num_kernel_image_mappings
;
191 #ifdef CONFIG_DEBUG_DCFLUSH
192 atomic_t dcpage_flushes
= ATOMIC_INIT(0);
194 atomic_t dcpage_flushes_xcall
= ATOMIC_INIT(0);
198 inline void flush_dcache_page_impl(struct page
*page
)
200 BUG_ON(tlb_type
== hypervisor
);
201 #ifdef CONFIG_DEBUG_DCFLUSH
202 atomic_inc(&dcpage_flushes
);
205 #ifdef DCACHE_ALIASING_POSSIBLE
206 __flush_dcache_page(page_address(page
),
207 ((tlb_type
== spitfire
) &&
208 page_mapping(page
) != NULL
));
210 if (page_mapping(page
) != NULL
&&
211 tlb_type
== spitfire
)
212 __flush_icache_page(__pa(page_address(page
)));
216 #define PG_dcache_dirty PG_arch_1
217 #define PG_dcache_cpu_shift 32UL
218 #define PG_dcache_cpu_mask \
219 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
221 #define dcache_dirty_cpu(page) \
222 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
224 static inline void set_dcache_dirty(struct page
*page
, int this_cpu
)
226 unsigned long mask
= this_cpu
;
227 unsigned long non_cpu_bits
;
229 non_cpu_bits
= ~(PG_dcache_cpu_mask
<< PG_dcache_cpu_shift
);
230 mask
= (mask
<< PG_dcache_cpu_shift
) | (1UL << PG_dcache_dirty
);
232 __asm__
__volatile__("1:\n\t"
234 "and %%g7, %1, %%g1\n\t"
235 "or %%g1, %0, %%g1\n\t"
236 "casx [%2], %%g7, %%g1\n\t"
238 "bne,pn %%xcc, 1b\n\t"
241 : "r" (mask
), "r" (non_cpu_bits
), "r" (&page
->flags
)
245 static inline void clear_dcache_dirty_cpu(struct page
*page
, unsigned long cpu
)
247 unsigned long mask
= (1UL << PG_dcache_dirty
);
249 __asm__
__volatile__("! test_and_clear_dcache_dirty\n"
252 "srlx %%g7, %4, %%g1\n\t"
253 "and %%g1, %3, %%g1\n\t"
255 "bne,pn %%icc, 2f\n\t"
256 " andn %%g7, %1, %%g1\n\t"
257 "casx [%2], %%g7, %%g1\n\t"
259 "bne,pn %%xcc, 1b\n\t"
263 : "r" (cpu
), "r" (mask
), "r" (&page
->flags
),
264 "i" (PG_dcache_cpu_mask
),
265 "i" (PG_dcache_cpu_shift
)
269 static inline void tsb_insert(struct tsb
*ent
, unsigned long tag
, unsigned long pte
)
271 unsigned long tsb_addr
= (unsigned long) ent
;
273 if (tlb_type
== cheetah_plus
|| tlb_type
== hypervisor
)
274 tsb_addr
= __pa(tsb_addr
);
276 __tsb_insert(tsb_addr
, tag
, pte
);
279 unsigned long _PAGE_ALL_SZ_BITS __read_mostly
;
281 static void flush_dcache(unsigned long pfn
)
285 page
= pfn_to_page(pfn
);
287 unsigned long pg_flags
;
289 pg_flags
= page
->flags
;
290 if (pg_flags
& (1UL << PG_dcache_dirty
)) {
291 int cpu
= ((pg_flags
>> PG_dcache_cpu_shift
) &
293 int this_cpu
= get_cpu();
295 /* This is just to optimize away some function calls
299 flush_dcache_page_impl(page
);
301 smp_flush_dcache_page_impl(page
, cpu
);
303 clear_dcache_dirty_cpu(page
, cpu
);
310 /* mm->context.lock must be held */
311 static void __update_mmu_tsb_insert(struct mm_struct
*mm
, unsigned long tsb_index
,
312 unsigned long tsb_hash_shift
, unsigned long address
,
315 struct tsb
*tsb
= mm
->context
.tsb_block
[tsb_index
].tsb
;
321 tsb
+= ((address
>> tsb_hash_shift
) &
322 (mm
->context
.tsb_block
[tsb_index
].tsb_nentries
- 1UL));
323 tag
= (address
>> 22UL);
324 tsb_insert(tsb
, tag
, tte
);
327 #ifdef CONFIG_HUGETLB_PAGE
328 static int __init
setup_hugepagesz(char *string
)
330 unsigned long long hugepage_size
;
331 unsigned int hugepage_shift
;
332 unsigned short hv_pgsz_idx
;
333 unsigned int hv_pgsz_mask
;
336 hugepage_size
= memparse(string
, &string
);
337 hugepage_shift
= ilog2(hugepage_size
);
339 switch (hugepage_shift
) {
340 case HPAGE_2GB_SHIFT
:
341 hv_pgsz_mask
= HV_PGSZ_MASK_2GB
;
342 hv_pgsz_idx
= HV_PGSZ_IDX_2GB
;
344 case HPAGE_256MB_SHIFT
:
345 hv_pgsz_mask
= HV_PGSZ_MASK_256MB
;
346 hv_pgsz_idx
= HV_PGSZ_IDX_256MB
;
349 hv_pgsz_mask
= HV_PGSZ_MASK_4MB
;
350 hv_pgsz_idx
= HV_PGSZ_IDX_4MB
;
352 case HPAGE_64K_SHIFT
:
353 hv_pgsz_mask
= HV_PGSZ_MASK_64K
;
354 hv_pgsz_idx
= HV_PGSZ_IDX_64K
;
360 if ((hv_pgsz_mask
& cpu_pgsz_mask
) == 0U) {
361 pr_warn("hugepagesz=%llu not supported by MMU.\n",
366 hugetlb_add_hstate(hugepage_shift
- PAGE_SHIFT
);
372 __setup("hugepagesz=", setup_hugepagesz
);
373 #endif /* CONFIG_HUGETLB_PAGE */
375 void update_mmu_cache(struct vm_area_struct
*vma
, unsigned long address
, pte_t
*ptep
)
377 struct mm_struct
*mm
;
381 if (tlb_type
!= hypervisor
) {
382 unsigned long pfn
= pte_pfn(pte
);
390 /* Don't insert a non-valid PTE into the TSB, we'll deadlock. */
391 if (!pte_accessible(mm
, pte
))
394 spin_lock_irqsave(&mm
->context
.lock
, flags
);
396 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
397 if ((mm
->context
.hugetlb_pte_count
|| mm
->context
.thp_pte_count
) &&
398 is_hugetlb_pmd(__pmd(pte_val(pte
)))) {
399 /* We are fabricating 8MB pages using 4MB real hw pages. */
400 pte_val(pte
) |= (address
& (1UL << REAL_HPAGE_SHIFT
));
401 __update_mmu_tsb_insert(mm
, MM_TSB_HUGE
, REAL_HPAGE_SHIFT
,
402 address
, pte_val(pte
));
405 __update_mmu_tsb_insert(mm
, MM_TSB_BASE
, PAGE_SHIFT
,
406 address
, pte_val(pte
));
408 spin_unlock_irqrestore(&mm
->context
.lock
, flags
);
411 void flush_dcache_page(struct page
*page
)
413 struct address_space
*mapping
;
416 if (tlb_type
== hypervisor
)
419 /* Do not bother with the expensive D-cache flush if it
420 * is merely the zero page. The 'bigcore' testcase in GDB
421 * causes this case to run millions of times.
423 if (page
== ZERO_PAGE(0))
426 this_cpu
= get_cpu();
428 mapping
= page_mapping(page
);
429 if (mapping
&& !mapping_mapped(mapping
)) {
430 int dirty
= test_bit(PG_dcache_dirty
, &page
->flags
);
432 int dirty_cpu
= dcache_dirty_cpu(page
);
434 if (dirty_cpu
== this_cpu
)
436 smp_flush_dcache_page_impl(page
, dirty_cpu
);
438 set_dcache_dirty(page
, this_cpu
);
440 /* We could delay the flush for the !page_mapping
441 * case too. But that case is for exec env/arg
442 * pages and those are %99 certainly going to get
443 * faulted into the tlb (and thus flushed) anyways.
445 flush_dcache_page_impl(page
);
451 EXPORT_SYMBOL(flush_dcache_page
);
453 void __kprobes
flush_icache_range(unsigned long start
, unsigned long end
)
455 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
456 if (tlb_type
== spitfire
) {
459 /* This code only runs on Spitfire cpus so this is
460 * why we can assume _PAGE_PADDR_4U.
462 for (kaddr
= start
; kaddr
< end
; kaddr
+= PAGE_SIZE
) {
463 unsigned long paddr
, mask
= _PAGE_PADDR_4U
;
465 if (kaddr
>= PAGE_OFFSET
)
466 paddr
= kaddr
& mask
;
468 pgd_t
*pgdp
= pgd_offset_k(kaddr
);
469 pud_t
*pudp
= pud_offset(pgdp
, kaddr
);
470 pmd_t
*pmdp
= pmd_offset(pudp
, kaddr
);
471 pte_t
*ptep
= pte_offset_kernel(pmdp
, kaddr
);
473 paddr
= pte_val(*ptep
) & mask
;
475 __flush_icache_page(paddr
);
479 EXPORT_SYMBOL(flush_icache_range
);
481 void mmu_info(struct seq_file
*m
)
483 static const char *pgsz_strings
[] = {
484 "8K", "64K", "512K", "4MB", "32MB",
485 "256MB", "2GB", "16GB",
489 if (tlb_type
== cheetah
)
490 seq_printf(m
, "MMU Type\t: Cheetah\n");
491 else if (tlb_type
== cheetah_plus
)
492 seq_printf(m
, "MMU Type\t: Cheetah+\n");
493 else if (tlb_type
== spitfire
)
494 seq_printf(m
, "MMU Type\t: Spitfire\n");
495 else if (tlb_type
== hypervisor
)
496 seq_printf(m
, "MMU Type\t: Hypervisor (sun4v)\n");
498 seq_printf(m
, "MMU Type\t: ???\n");
500 seq_printf(m
, "MMU PGSZs\t: ");
502 for (i
= 0; i
< ARRAY_SIZE(pgsz_strings
); i
++) {
503 if (cpu_pgsz_mask
& (1UL << i
)) {
504 seq_printf(m
, "%s%s",
505 printed
? "," : "", pgsz_strings
[i
]);
511 #ifdef CONFIG_DEBUG_DCFLUSH
512 seq_printf(m
, "DCPageFlushes\t: %d\n",
513 atomic_read(&dcpage_flushes
));
515 seq_printf(m
, "DCPageFlushesXC\t: %d\n",
516 atomic_read(&dcpage_flushes_xcall
));
517 #endif /* CONFIG_SMP */
518 #endif /* CONFIG_DEBUG_DCFLUSH */
521 struct linux_prom_translation prom_trans
[512] __read_mostly
;
522 unsigned int prom_trans_ents __read_mostly
;
524 unsigned long kern_locked_tte_data
;
526 /* The obp translations are saved based on 8k pagesize, since obp can
527 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
528 * HI_OBP_ADDRESS range are handled in ktlb.S.
530 static inline int in_obp_range(unsigned long vaddr
)
532 return (vaddr
>= LOW_OBP_ADDRESS
&&
533 vaddr
< HI_OBP_ADDRESS
);
536 static int cmp_ptrans(const void *a
, const void *b
)
538 const struct linux_prom_translation
*x
= a
, *y
= b
;
540 if (x
->virt
> y
->virt
)
542 if (x
->virt
< y
->virt
)
547 /* Read OBP translations property into 'prom_trans[]'. */
548 static void __init
read_obp_translations(void)
550 int n
, node
, ents
, first
, last
, i
;
552 node
= prom_finddevice("/virtual-memory");
553 n
= prom_getproplen(node
, "translations");
554 if (unlikely(n
== 0 || n
== -1)) {
555 prom_printf("prom_mappings: Couldn't get size.\n");
558 if (unlikely(n
> sizeof(prom_trans
))) {
559 prom_printf("prom_mappings: Size %d is too big.\n", n
);
563 if ((n
= prom_getproperty(node
, "translations",
564 (char *)&prom_trans
[0],
565 sizeof(prom_trans
))) == -1) {
566 prom_printf("prom_mappings: Couldn't get property.\n");
570 n
= n
/ sizeof(struct linux_prom_translation
);
574 sort(prom_trans
, ents
, sizeof(struct linux_prom_translation
),
577 /* Now kick out all the non-OBP entries. */
578 for (i
= 0; i
< ents
; i
++) {
579 if (in_obp_range(prom_trans
[i
].virt
))
583 for (; i
< ents
; i
++) {
584 if (!in_obp_range(prom_trans
[i
].virt
))
589 for (i
= 0; i
< (last
- first
); i
++) {
590 struct linux_prom_translation
*src
= &prom_trans
[i
+ first
];
591 struct linux_prom_translation
*dest
= &prom_trans
[i
];
595 for (; i
< ents
; i
++) {
596 struct linux_prom_translation
*dest
= &prom_trans
[i
];
597 dest
->virt
= dest
->size
= dest
->data
= 0x0UL
;
600 prom_trans_ents
= last
- first
;
602 if (tlb_type
== spitfire
) {
603 /* Clear diag TTE bits. */
604 for (i
= 0; i
< prom_trans_ents
; i
++)
605 prom_trans
[i
].data
&= ~0x0003fe0000000000UL
;
608 /* Force execute bit on. */
609 for (i
= 0; i
< prom_trans_ents
; i
++)
610 prom_trans
[i
].data
|= (tlb_type
== hypervisor
?
611 _PAGE_EXEC_4V
: _PAGE_EXEC_4U
);
614 static void __init
hypervisor_tlb_lock(unsigned long vaddr
,
618 unsigned long ret
= sun4v_mmu_map_perm_addr(vaddr
, 0, pte
, mmu
);
621 prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: "
622 "errors with %lx\n", vaddr
, 0, pte
, mmu
, ret
);
627 static unsigned long kern_large_tte(unsigned long paddr
);
629 static void __init
remap_kernel(void)
631 unsigned long phys_page
, tte_vaddr
, tte_data
;
632 int i
, tlb_ent
= sparc64_highest_locked_tlbent();
634 tte_vaddr
= (unsigned long) KERNBASE
;
635 phys_page
= (prom_boot_mapping_phys_low
>> ILOG2_4MB
) << ILOG2_4MB
;
636 tte_data
= kern_large_tte(phys_page
);
638 kern_locked_tte_data
= tte_data
;
640 /* Now lock us into the TLBs via Hypervisor or OBP. */
641 if (tlb_type
== hypervisor
) {
642 for (i
= 0; i
< num_kernel_image_mappings
; i
++) {
643 hypervisor_tlb_lock(tte_vaddr
, tte_data
, HV_MMU_DMMU
);
644 hypervisor_tlb_lock(tte_vaddr
, tte_data
, HV_MMU_IMMU
);
645 tte_vaddr
+= 0x400000;
646 tte_data
+= 0x400000;
649 for (i
= 0; i
< num_kernel_image_mappings
; i
++) {
650 prom_dtlb_load(tlb_ent
- i
, tte_data
, tte_vaddr
);
651 prom_itlb_load(tlb_ent
- i
, tte_data
, tte_vaddr
);
652 tte_vaddr
+= 0x400000;
653 tte_data
+= 0x400000;
655 sparc64_highest_unlocked_tlb_ent
= tlb_ent
- i
;
657 if (tlb_type
== cheetah_plus
) {
658 sparc64_kern_pri_context
= (CTX_CHEETAH_PLUS_CTX0
|
659 CTX_CHEETAH_PLUS_NUC
);
660 sparc64_kern_pri_nuc_bits
= CTX_CHEETAH_PLUS_NUC
;
661 sparc64_kern_sec_context
= CTX_CHEETAH_PLUS_CTX0
;
666 static void __init
inherit_prom_mappings(void)
668 /* Now fixup OBP's idea about where we really are mapped. */
669 printk("Remapping the kernel... ");
674 void prom_world(int enter
)
679 __asm__
__volatile__("flushw");
682 void __flush_dcache_range(unsigned long start
, unsigned long end
)
686 if (tlb_type
== spitfire
) {
689 for (va
= start
; va
< end
; va
+= 32) {
690 spitfire_put_dcache_tag(va
& 0x3fe0, 0x0);
694 } else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
697 for (va
= start
; va
< end
; va
+= 32)
698 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
702 "i" (ASI_DCACHE_INVALIDATE
));
705 EXPORT_SYMBOL(__flush_dcache_range
);
707 /* get_new_mmu_context() uses "cache + 1". */
708 DEFINE_SPINLOCK(ctx_alloc_lock
);
709 unsigned long tlb_context_cache
= CTX_FIRST_VERSION
- 1;
710 #define MAX_CTX_NR (1UL << CTX_NR_BITS)
711 #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
712 DECLARE_BITMAP(mmu_context_bmap
, MAX_CTX_NR
);
714 /* Caller does TLB context flushing on local CPU if necessary.
715 * The caller also ensures that CTX_VALID(mm->context) is false.
717 * We must be careful about boundary cases so that we never
718 * let the user have CTX 0 (nucleus) or we ever use a CTX
719 * version of zero (and thus NO_CONTEXT would not be caught
720 * by version mis-match tests in mmu_context.h).
722 * Always invoked with interrupts disabled.
724 void get_new_mmu_context(struct mm_struct
*mm
)
726 unsigned long ctx
, new_ctx
;
727 unsigned long orig_pgsz_bits
;
730 spin_lock(&ctx_alloc_lock
);
731 orig_pgsz_bits
= (mm
->context
.sparc64_ctx_val
& CTX_PGSZ_MASK
);
732 ctx
= (tlb_context_cache
+ 1) & CTX_NR_MASK
;
733 new_ctx
= find_next_zero_bit(mmu_context_bmap
, 1 << CTX_NR_BITS
, ctx
);
735 if (new_ctx
>= (1 << CTX_NR_BITS
)) {
736 new_ctx
= find_next_zero_bit(mmu_context_bmap
, ctx
, 1);
737 if (new_ctx
>= ctx
) {
739 new_ctx
= (tlb_context_cache
& CTX_VERSION_MASK
) +
742 new_ctx
= CTX_FIRST_VERSION
;
744 /* Don't call memset, for 16 entries that's just
747 mmu_context_bmap
[0] = 3;
748 mmu_context_bmap
[1] = 0;
749 mmu_context_bmap
[2] = 0;
750 mmu_context_bmap
[3] = 0;
751 for (i
= 4; i
< CTX_BMAP_SLOTS
; i
+= 4) {
752 mmu_context_bmap
[i
+ 0] = 0;
753 mmu_context_bmap
[i
+ 1] = 0;
754 mmu_context_bmap
[i
+ 2] = 0;
755 mmu_context_bmap
[i
+ 3] = 0;
761 mmu_context_bmap
[new_ctx
>>6] |= (1UL << (new_ctx
& 63));
762 new_ctx
|= (tlb_context_cache
& CTX_VERSION_MASK
);
764 tlb_context_cache
= new_ctx
;
765 mm
->context
.sparc64_ctx_val
= new_ctx
| orig_pgsz_bits
;
766 spin_unlock(&ctx_alloc_lock
);
768 if (unlikely(new_version
))
769 smp_new_mmu_context_version();
772 static int numa_enabled
= 1;
773 static int numa_debug
;
775 static int __init
early_numa(char *p
)
780 if (strstr(p
, "off"))
783 if (strstr(p
, "debug"))
788 early_param("numa", early_numa
);
790 #define numadbg(f, a...) \
791 do { if (numa_debug) \
792 printk(KERN_INFO f, ## a); \
795 static void __init
find_ramdisk(unsigned long phys_base
)
797 #ifdef CONFIG_BLK_DEV_INITRD
798 if (sparc_ramdisk_image
|| sparc_ramdisk_image64
) {
799 unsigned long ramdisk_image
;
801 /* Older versions of the bootloader only supported a
802 * 32-bit physical address for the ramdisk image
803 * location, stored at sparc_ramdisk_image. Newer
804 * SILO versions set sparc_ramdisk_image to zero and
805 * provide a full 64-bit physical address at
806 * sparc_ramdisk_image64.
808 ramdisk_image
= sparc_ramdisk_image
;
810 ramdisk_image
= sparc_ramdisk_image64
;
812 /* Another bootloader quirk. The bootloader normalizes
813 * the physical address to KERNBASE, so we have to
814 * factor that back out and add in the lowest valid
815 * physical page address to get the true physical address.
817 ramdisk_image
-= KERNBASE
;
818 ramdisk_image
+= phys_base
;
820 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
821 ramdisk_image
, sparc_ramdisk_size
);
823 initrd_start
= ramdisk_image
;
824 initrd_end
= ramdisk_image
+ sparc_ramdisk_size
;
826 memblock_reserve(initrd_start
, sparc_ramdisk_size
);
828 initrd_start
+= PAGE_OFFSET
;
829 initrd_end
+= PAGE_OFFSET
;
834 struct node_mem_mask
{
838 static struct node_mem_mask node_masks
[MAX_NUMNODES
];
839 static int num_node_masks
;
841 #ifdef CONFIG_NEED_MULTIPLE_NODES
843 struct mdesc_mlgroup
{
850 static struct mdesc_mlgroup
*mlgroups
;
851 static int num_mlgroups
;
853 int numa_cpu_lookup_table
[NR_CPUS
];
854 cpumask_t numa_cpumask_lookup_table
[MAX_NUMNODES
];
856 struct mdesc_mblock
{
859 u64 offset
; /* RA-to-PA */
861 static struct mdesc_mblock
*mblocks
;
862 static int num_mblocks
;
864 static struct mdesc_mblock
* __init
addr_to_mblock(unsigned long addr
)
866 struct mdesc_mblock
*m
= NULL
;
869 for (i
= 0; i
< num_mblocks
; i
++) {
872 if (addr
>= m
->base
&&
873 addr
< (m
->base
+ m
->size
)) {
881 static u64 __init
memblock_nid_range_sun4u(u64 start
, u64 end
, int *nid
)
883 int prev_nid
, new_nid
;
886 for ( ; start
< end
; start
+= PAGE_SIZE
) {
887 for (new_nid
= 0; new_nid
< num_node_masks
; new_nid
++) {
888 struct node_mem_mask
*p
= &node_masks
[new_nid
];
890 if ((start
& p
->mask
) == p
->match
) {
897 if (new_nid
== num_node_masks
) {
899 WARN_ONCE(1, "addr[%Lx] doesn't match a NUMA node rule. Some memory will be owned by node 0.",
904 if (prev_nid
!= new_nid
)
909 return start
> end
? end
: start
;
912 static u64 __init
memblock_nid_range(u64 start
, u64 end
, int *nid
)
914 u64 ret_end
, pa_start
, m_mask
, m_match
, m_end
;
915 struct mdesc_mblock
*mblock
;
918 if (tlb_type
!= hypervisor
)
919 return memblock_nid_range_sun4u(start
, end
, nid
);
921 mblock
= addr_to_mblock(start
);
923 WARN_ONCE(1, "memblock_nid_range: Can't find mblock addr[%Lx]",
931 pa_start
= start
+ mblock
->offset
;
935 for (_nid
= 0; _nid
< num_node_masks
; _nid
++) {
936 struct node_mem_mask
*const m
= &node_masks
[_nid
];
938 if ((pa_start
& m
->mask
) == m
->match
) {
945 if (num_node_masks
== _nid
) {
946 /* We could not find NUMA group, so default to 0, but lets
947 * search for latency group, so we could calculate the correct
948 * end address that we return
952 for (i
= 0; i
< num_mlgroups
; i
++) {
953 struct mdesc_mlgroup
*const m
= &mlgroups
[i
];
955 if ((pa_start
& m
->mask
) == m
->match
) {
962 if (i
== num_mlgroups
) {
963 WARN_ONCE(1, "memblock_nid_range: Can't find latency group addr[%Lx]",
972 * Each latency group has match and mask, and each memory block has an
973 * offset. An address belongs to a latency group if its address matches
974 * the following formula: ((addr + offset) & mask) == match
975 * It is, however, slow to check every single page if it matches a
976 * particular latency group. As optimization we calculate end value by
977 * using bit arithmetics.
979 m_end
= m_match
+ (1ul << __ffs(m_mask
)) - mblock
->offset
;
980 m_end
+= pa_start
& ~((1ul << fls64(m_mask
)) - 1);
981 ret_end
= m_end
> end
? end
: m_end
;
989 /* This must be invoked after performing all of the necessary
990 * memblock_set_node() calls for 'nid'. We need to be able to get
991 * correct data from get_pfn_range_for_nid().
993 static void __init
allocate_node_data(int nid
)
995 struct pglist_data
*p
;
996 unsigned long start_pfn
, end_pfn
;
997 #ifdef CONFIG_NEED_MULTIPLE_NODES
1000 paddr
= memblock_alloc_try_nid(sizeof(struct pglist_data
), SMP_CACHE_BYTES
, nid
);
1002 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid
);
1005 NODE_DATA(nid
) = __va(paddr
);
1006 memset(NODE_DATA(nid
), 0, sizeof(struct pglist_data
));
1008 NODE_DATA(nid
)->node_id
= nid
;
1013 get_pfn_range_for_nid(nid
, &start_pfn
, &end_pfn
);
1014 p
->node_start_pfn
= start_pfn
;
1015 p
->node_spanned_pages
= end_pfn
- start_pfn
;
1018 static void init_node_masks_nonnuma(void)
1020 #ifdef CONFIG_NEED_MULTIPLE_NODES
1024 numadbg("Initializing tables for non-numa.\n");
1026 node_masks
[0].mask
= 0;
1027 node_masks
[0].match
= 0;
1030 #ifdef CONFIG_NEED_MULTIPLE_NODES
1031 for (i
= 0; i
< NR_CPUS
; i
++)
1032 numa_cpu_lookup_table
[i
] = 0;
1034 cpumask_setall(&numa_cpumask_lookup_table
[0]);
1038 #ifdef CONFIG_NEED_MULTIPLE_NODES
1039 struct pglist_data
*node_data
[MAX_NUMNODES
];
1041 EXPORT_SYMBOL(numa_cpu_lookup_table
);
1042 EXPORT_SYMBOL(numa_cpumask_lookup_table
);
1043 EXPORT_SYMBOL(node_data
);
1045 static int scan_pio_for_cfg_handle(struct mdesc_handle
*md
, u64 pio
,
1050 mdesc_for_each_arc(arc
, md
, pio
, MDESC_ARC_TYPE_FWD
) {
1051 u64 target
= mdesc_arc_target(md
, arc
);
1054 val
= mdesc_get_property(md
, target
,
1055 "cfg-handle", NULL
);
1056 if (val
&& *val
== cfg_handle
)
1062 static int scan_arcs_for_cfg_handle(struct mdesc_handle
*md
, u64 grp
,
1065 u64 arc
, candidate
, best_latency
= ~(u64
)0;
1067 candidate
= MDESC_NODE_NULL
;
1068 mdesc_for_each_arc(arc
, md
, grp
, MDESC_ARC_TYPE_FWD
) {
1069 u64 target
= mdesc_arc_target(md
, arc
);
1070 const char *name
= mdesc_node_name(md
, target
);
1073 if (strcmp(name
, "pio-latency-group"))
1076 val
= mdesc_get_property(md
, target
, "latency", NULL
);
1080 if (*val
< best_latency
) {
1082 best_latency
= *val
;
1086 if (candidate
== MDESC_NODE_NULL
)
1089 return scan_pio_for_cfg_handle(md
, candidate
, cfg_handle
);
1092 int of_node_to_nid(struct device_node
*dp
)
1094 const struct linux_prom64_registers
*regs
;
1095 struct mdesc_handle
*md
;
1100 /* This is the right thing to do on currently supported
1101 * SUN4U NUMA platforms as well, as the PCI controller does
1102 * not sit behind any particular memory controller.
1107 regs
= of_get_property(dp
, "reg", NULL
);
1111 cfg_handle
= (regs
->phys_addr
>> 32UL) & 0x0fffffff;
1117 mdesc_for_each_node_by_name(md
, grp
, "group") {
1118 if (!scan_arcs_for_cfg_handle(md
, grp
, cfg_handle
)) {
1130 static void __init
add_node_ranges(void)
1132 struct memblock_region
*reg
;
1133 unsigned long prev_max
;
1136 prev_max
= memblock
.memory
.max
;
1138 for_each_memblock(memory
, reg
) {
1139 unsigned long size
= reg
->size
;
1140 unsigned long start
, end
;
1144 while (start
< end
) {
1145 unsigned long this_end
;
1148 this_end
= memblock_nid_range(start
, end
, &nid
);
1150 numadbg("Setting memblock NUMA node nid[%d] "
1151 "start[%lx] end[%lx]\n",
1152 nid
, start
, this_end
);
1154 memblock_set_node(start
, this_end
- start
,
1155 &memblock
.memory
, nid
);
1156 if (memblock
.memory
.max
!= prev_max
)
1157 goto memblock_resized
;
1163 static int __init
grab_mlgroups(struct mdesc_handle
*md
)
1165 unsigned long paddr
;
1169 mdesc_for_each_node_by_name(md
, node
, "memory-latency-group")
1174 paddr
= memblock_alloc(count
* sizeof(struct mdesc_mlgroup
),
1179 mlgroups
= __va(paddr
);
1180 num_mlgroups
= count
;
1183 mdesc_for_each_node_by_name(md
, node
, "memory-latency-group") {
1184 struct mdesc_mlgroup
*m
= &mlgroups
[count
++];
1189 val
= mdesc_get_property(md
, node
, "latency", NULL
);
1191 val
= mdesc_get_property(md
, node
, "address-match", NULL
);
1193 val
= mdesc_get_property(md
, node
, "address-mask", NULL
);
1196 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
1197 "match[%llx] mask[%llx]\n",
1198 count
- 1, m
->node
, m
->latency
, m
->match
, m
->mask
);
1204 static int __init
grab_mblocks(struct mdesc_handle
*md
)
1206 unsigned long paddr
;
1210 mdesc_for_each_node_by_name(md
, node
, "mblock")
1215 paddr
= memblock_alloc(count
* sizeof(struct mdesc_mblock
),
1220 mblocks
= __va(paddr
);
1221 num_mblocks
= count
;
1224 mdesc_for_each_node_by_name(md
, node
, "mblock") {
1225 struct mdesc_mblock
*m
= &mblocks
[count
++];
1228 val
= mdesc_get_property(md
, node
, "base", NULL
);
1230 val
= mdesc_get_property(md
, node
, "size", NULL
);
1232 val
= mdesc_get_property(md
, node
,
1233 "address-congruence-offset", NULL
);
1235 /* The address-congruence-offset property is optional.
1236 * Explicity zero it be identifty this.
1243 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
1244 count
- 1, m
->base
, m
->size
, m
->offset
);
1250 static void __init
numa_parse_mdesc_group_cpus(struct mdesc_handle
*md
,
1251 u64 grp
, cpumask_t
*mask
)
1255 cpumask_clear(mask
);
1257 mdesc_for_each_arc(arc
, md
, grp
, MDESC_ARC_TYPE_BACK
) {
1258 u64 target
= mdesc_arc_target(md
, arc
);
1259 const char *name
= mdesc_node_name(md
, target
);
1262 if (strcmp(name
, "cpu"))
1264 id
= mdesc_get_property(md
, target
, "id", NULL
);
1265 if (*id
< nr_cpu_ids
)
1266 cpumask_set_cpu(*id
, mask
);
1270 static struct mdesc_mlgroup
* __init
find_mlgroup(u64 node
)
1274 for (i
= 0; i
< num_mlgroups
; i
++) {
1275 struct mdesc_mlgroup
*m
= &mlgroups
[i
];
1276 if (m
->node
== node
)
1282 int __node_distance(int from
, int to
)
1284 if ((from
>= MAX_NUMNODES
) || (to
>= MAX_NUMNODES
)) {
1285 pr_warn("Returning default NUMA distance value for %d->%d\n",
1287 return (from
== to
) ? LOCAL_DISTANCE
: REMOTE_DISTANCE
;
1289 return numa_latency
[from
][to
];
1292 static int __init
find_best_numa_node_for_mlgroup(struct mdesc_mlgroup
*grp
)
1296 for (i
= 0; i
< MAX_NUMNODES
; i
++) {
1297 struct node_mem_mask
*n
= &node_masks
[i
];
1299 if ((grp
->mask
== n
->mask
) && (grp
->match
== n
->match
))
1305 static void __init
find_numa_latencies_for_group(struct mdesc_handle
*md
,
1310 mdesc_for_each_arc(arc
, md
, grp
, MDESC_ARC_TYPE_FWD
) {
1312 u64 target
= mdesc_arc_target(md
, arc
);
1313 struct mdesc_mlgroup
*m
= find_mlgroup(target
);
1317 tnode
= find_best_numa_node_for_mlgroup(m
);
1318 if (tnode
== MAX_NUMNODES
)
1320 numa_latency
[index
][tnode
] = m
->latency
;
1324 static int __init
numa_attach_mlgroup(struct mdesc_handle
*md
, u64 grp
,
1327 struct mdesc_mlgroup
*candidate
= NULL
;
1328 u64 arc
, best_latency
= ~(u64
)0;
1329 struct node_mem_mask
*n
;
1331 mdesc_for_each_arc(arc
, md
, grp
, MDESC_ARC_TYPE_FWD
) {
1332 u64 target
= mdesc_arc_target(md
, arc
);
1333 struct mdesc_mlgroup
*m
= find_mlgroup(target
);
1336 if (m
->latency
< best_latency
) {
1338 best_latency
= m
->latency
;
1344 if (num_node_masks
!= index
) {
1345 printk(KERN_ERR
"Inconsistent NUMA state, "
1346 "index[%d] != num_node_masks[%d]\n",
1347 index
, num_node_masks
);
1351 n
= &node_masks
[num_node_masks
++];
1353 n
->mask
= candidate
->mask
;
1354 n
->match
= candidate
->match
;
1356 numadbg("NUMA NODE[%d]: mask[%lx] match[%lx] (latency[%llx])\n",
1357 index
, n
->mask
, n
->match
, candidate
->latency
);
1362 static int __init
numa_parse_mdesc_group(struct mdesc_handle
*md
, u64 grp
,
1368 numa_parse_mdesc_group_cpus(md
, grp
, &mask
);
1370 for_each_cpu(cpu
, &mask
)
1371 numa_cpu_lookup_table
[cpu
] = index
;
1372 cpumask_copy(&numa_cpumask_lookup_table
[index
], &mask
);
1375 printk(KERN_INFO
"NUMA GROUP[%d]: cpus [ ", index
);
1376 for_each_cpu(cpu
, &mask
)
1381 return numa_attach_mlgroup(md
, grp
, index
);
1384 static int __init
numa_parse_mdesc(void)
1386 struct mdesc_handle
*md
= mdesc_grab();
1387 int i
, j
, err
, count
;
1390 node
= mdesc_node_by_name(md
, MDESC_NODE_NULL
, "latency-groups");
1391 if (node
== MDESC_NODE_NULL
) {
1396 err
= grab_mblocks(md
);
1400 err
= grab_mlgroups(md
);
1405 mdesc_for_each_node_by_name(md
, node
, "group") {
1406 err
= numa_parse_mdesc_group(md
, node
, count
);
1413 mdesc_for_each_node_by_name(md
, node
, "group") {
1414 find_numa_latencies_for_group(md
, node
, count
);
1418 /* Normalize numa latency matrix according to ACPI SLIT spec. */
1419 for (i
= 0; i
< MAX_NUMNODES
; i
++) {
1420 u64 self_latency
= numa_latency
[i
][i
];
1422 for (j
= 0; j
< MAX_NUMNODES
; j
++) {
1423 numa_latency
[i
][j
] =
1424 (numa_latency
[i
][j
] * LOCAL_DISTANCE
) /
1431 for (i
= 0; i
< num_node_masks
; i
++) {
1432 allocate_node_data(i
);
1442 static int __init
numa_parse_jbus(void)
1444 unsigned long cpu
, index
;
1446 /* NUMA node id is encoded in bits 36 and higher, and there is
1447 * a 1-to-1 mapping from CPU ID to NUMA node ID.
1450 for_each_present_cpu(cpu
) {
1451 numa_cpu_lookup_table
[cpu
] = index
;
1452 cpumask_copy(&numa_cpumask_lookup_table
[index
], cpumask_of(cpu
));
1453 node_masks
[index
].mask
= ~((1UL << 36UL) - 1UL);
1454 node_masks
[index
].match
= cpu
<< 36UL;
1458 num_node_masks
= index
;
1462 for (index
= 0; index
< num_node_masks
; index
++) {
1463 allocate_node_data(index
);
1464 node_set_online(index
);
1470 static int __init
numa_parse_sun4u(void)
1472 if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
1475 __asm__ ("rdpr %%ver, %0" : "=r" (ver
));
1476 if ((ver
>> 32UL) == __JALAPENO_ID
||
1477 (ver
>> 32UL) == __SERRANO_ID
)
1478 return numa_parse_jbus();
1483 static int __init
bootmem_init_numa(void)
1488 numadbg("bootmem_init_numa()\n");
1490 /* Some sane defaults for numa latency values */
1491 for (i
= 0; i
< MAX_NUMNODES
; i
++) {
1492 for (j
= 0; j
< MAX_NUMNODES
; j
++)
1493 numa_latency
[i
][j
] = (i
== j
) ?
1494 LOCAL_DISTANCE
: REMOTE_DISTANCE
;
1498 if (tlb_type
== hypervisor
)
1499 err
= numa_parse_mdesc();
1501 err
= numa_parse_sun4u();
1508 static int bootmem_init_numa(void)
1515 static void __init
bootmem_init_nonnuma(void)
1517 unsigned long top_of_ram
= memblock_end_of_DRAM();
1518 unsigned long total_ram
= memblock_phys_mem_size();
1520 numadbg("bootmem_init_nonnuma()\n");
1522 printk(KERN_INFO
"Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1523 top_of_ram
, total_ram
);
1524 printk(KERN_INFO
"Memory hole size: %ldMB\n",
1525 (top_of_ram
- total_ram
) >> 20);
1527 init_node_masks_nonnuma();
1528 memblock_set_node(0, (phys_addr_t
)ULLONG_MAX
, &memblock
.memory
, 0);
1529 allocate_node_data(0);
1533 static unsigned long __init
bootmem_init(unsigned long phys_base
)
1535 unsigned long end_pfn
;
1537 end_pfn
= memblock_end_of_DRAM() >> PAGE_SHIFT
;
1538 max_pfn
= max_low_pfn
= end_pfn
;
1539 min_low_pfn
= (phys_base
>> PAGE_SHIFT
);
1541 if (bootmem_init_numa() < 0)
1542 bootmem_init_nonnuma();
1544 /* Dump memblock with node info. */
1545 memblock_dump_all();
1547 /* XXX cpu notifier XXX */
1549 sparse_memory_present_with_active_regions(MAX_NUMNODES
);
1555 static struct linux_prom64_registers pall
[MAX_BANKS
] __initdata
;
1556 static int pall_ents __initdata
;
1558 static unsigned long max_phys_bits
= 40;
1560 bool kern_addr_valid(unsigned long addr
)
1567 if ((long)addr
< 0L) {
1568 unsigned long pa
= __pa(addr
);
1570 if ((pa
>> max_phys_bits
) != 0UL)
1573 return pfn_valid(pa
>> PAGE_SHIFT
);
1576 if (addr
>= (unsigned long) KERNBASE
&&
1577 addr
< (unsigned long)&_end
)
1580 pgd
= pgd_offset_k(addr
);
1584 pud
= pud_offset(pgd
, addr
);
1588 if (pud_large(*pud
))
1589 return pfn_valid(pud_pfn(*pud
));
1591 pmd
= pmd_offset(pud
, addr
);
1595 if (pmd_large(*pmd
))
1596 return pfn_valid(pmd_pfn(*pmd
));
1598 pte
= pte_offset_kernel(pmd
, addr
);
1602 return pfn_valid(pte_pfn(*pte
));
1604 EXPORT_SYMBOL(kern_addr_valid
);
1606 static unsigned long __ref
kernel_map_hugepud(unsigned long vstart
,
1610 const unsigned long mask16gb
= (1UL << 34) - 1UL;
1611 u64 pte_val
= vstart
;
1613 /* Each PUD is 8GB */
1614 if ((vstart
& mask16gb
) ||
1615 (vend
- vstart
<= mask16gb
)) {
1616 pte_val
^= kern_linear_pte_xor
[2];
1617 pud_val(*pud
) = pte_val
| _PAGE_PUD_HUGE
;
1619 return vstart
+ PUD_SIZE
;
1622 pte_val
^= kern_linear_pte_xor
[3];
1623 pte_val
|= _PAGE_PUD_HUGE
;
1625 vend
= vstart
+ mask16gb
+ 1UL;
1626 while (vstart
< vend
) {
1627 pud_val(*pud
) = pte_val
;
1629 pte_val
+= PUD_SIZE
;
1636 static bool kernel_can_map_hugepud(unsigned long vstart
, unsigned long vend
,
1639 if (guard
&& !(vstart
& ~PUD_MASK
) && (vend
- vstart
) >= PUD_SIZE
)
1645 static unsigned long __ref
kernel_map_hugepmd(unsigned long vstart
,
1649 const unsigned long mask256mb
= (1UL << 28) - 1UL;
1650 const unsigned long mask2gb
= (1UL << 31) - 1UL;
1651 u64 pte_val
= vstart
;
1653 /* Each PMD is 8MB */
1654 if ((vstart
& mask256mb
) ||
1655 (vend
- vstart
<= mask256mb
)) {
1656 pte_val
^= kern_linear_pte_xor
[0];
1657 pmd_val(*pmd
) = pte_val
| _PAGE_PMD_HUGE
;
1659 return vstart
+ PMD_SIZE
;
1662 if ((vstart
& mask2gb
) ||
1663 (vend
- vstart
<= mask2gb
)) {
1664 pte_val
^= kern_linear_pte_xor
[1];
1665 pte_val
|= _PAGE_PMD_HUGE
;
1666 vend
= vstart
+ mask256mb
+ 1UL;
1668 pte_val
^= kern_linear_pte_xor
[2];
1669 pte_val
|= _PAGE_PMD_HUGE
;
1670 vend
= vstart
+ mask2gb
+ 1UL;
1673 while (vstart
< vend
) {
1674 pmd_val(*pmd
) = pte_val
;
1676 pte_val
+= PMD_SIZE
;
1684 static bool kernel_can_map_hugepmd(unsigned long vstart
, unsigned long vend
,
1687 if (guard
&& !(vstart
& ~PMD_MASK
) && (vend
- vstart
) >= PMD_SIZE
)
1693 static unsigned long __ref
kernel_map_range(unsigned long pstart
,
1694 unsigned long pend
, pgprot_t prot
,
1697 unsigned long vstart
= PAGE_OFFSET
+ pstart
;
1698 unsigned long vend
= PAGE_OFFSET
+ pend
;
1699 unsigned long alloc_bytes
= 0UL;
1701 if ((vstart
& ~PAGE_MASK
) || (vend
& ~PAGE_MASK
)) {
1702 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1707 while (vstart
< vend
) {
1708 unsigned long this_end
, paddr
= __pa(vstart
);
1709 pgd_t
*pgd
= pgd_offset_k(vstart
);
1714 if (pgd_none(*pgd
)) {
1717 new = __alloc_bootmem(PAGE_SIZE
, PAGE_SIZE
, PAGE_SIZE
);
1718 alloc_bytes
+= PAGE_SIZE
;
1719 pgd_populate(&init_mm
, pgd
, new);
1721 pud
= pud_offset(pgd
, vstart
);
1722 if (pud_none(*pud
)) {
1725 if (kernel_can_map_hugepud(vstart
, vend
, use_huge
)) {
1726 vstart
= kernel_map_hugepud(vstart
, vend
, pud
);
1729 new = __alloc_bootmem(PAGE_SIZE
, PAGE_SIZE
, PAGE_SIZE
);
1730 alloc_bytes
+= PAGE_SIZE
;
1731 pud_populate(&init_mm
, pud
, new);
1734 pmd
= pmd_offset(pud
, vstart
);
1735 if (pmd_none(*pmd
)) {
1738 if (kernel_can_map_hugepmd(vstart
, vend
, use_huge
)) {
1739 vstart
= kernel_map_hugepmd(vstart
, vend
, pmd
);
1742 new = __alloc_bootmem(PAGE_SIZE
, PAGE_SIZE
, PAGE_SIZE
);
1743 alloc_bytes
+= PAGE_SIZE
;
1744 pmd_populate_kernel(&init_mm
, pmd
, new);
1747 pte
= pte_offset_kernel(pmd
, vstart
);
1748 this_end
= (vstart
+ PMD_SIZE
) & PMD_MASK
;
1749 if (this_end
> vend
)
1752 while (vstart
< this_end
) {
1753 pte_val(*pte
) = (paddr
| pgprot_val(prot
));
1755 vstart
+= PAGE_SIZE
;
1764 static void __init
flush_all_kernel_tsbs(void)
1768 for (i
= 0; i
< KERNEL_TSB_NENTRIES
; i
++) {
1769 struct tsb
*ent
= &swapper_tsb
[i
];
1771 ent
->tag
= (1UL << TSB_TAG_INVALID_BIT
);
1773 #ifndef CONFIG_DEBUG_PAGEALLOC
1774 for (i
= 0; i
< KERNEL_TSB4M_NENTRIES
; i
++) {
1775 struct tsb
*ent
= &swapper_4m_tsb
[i
];
1777 ent
->tag
= (1UL << TSB_TAG_INVALID_BIT
);
1782 extern unsigned int kvmap_linear_patch
[1];
1784 static void __init
kernel_physical_mapping_init(void)
1786 unsigned long i
, mem_alloced
= 0UL;
1787 bool use_huge
= true;
1789 #ifdef CONFIG_DEBUG_PAGEALLOC
1792 for (i
= 0; i
< pall_ents
; i
++) {
1793 unsigned long phys_start
, phys_end
;
1795 phys_start
= pall
[i
].phys_addr
;
1796 phys_end
= phys_start
+ pall
[i
].reg_size
;
1798 mem_alloced
+= kernel_map_range(phys_start
, phys_end
,
1799 PAGE_KERNEL
, use_huge
);
1802 printk("Allocated %ld bytes for kernel page tables.\n",
1805 kvmap_linear_patch
[0] = 0x01000000; /* nop */
1806 flushi(&kvmap_linear_patch
[0]);
1808 flush_all_kernel_tsbs();
1813 #ifdef CONFIG_DEBUG_PAGEALLOC
1814 void __kernel_map_pages(struct page
*page
, int numpages
, int enable
)
1816 unsigned long phys_start
= page_to_pfn(page
) << PAGE_SHIFT
;
1817 unsigned long phys_end
= phys_start
+ (numpages
* PAGE_SIZE
);
1819 kernel_map_range(phys_start
, phys_end
,
1820 (enable
? PAGE_KERNEL
: __pgprot(0)), false);
1822 flush_tsb_kernel_range(PAGE_OFFSET
+ phys_start
,
1823 PAGE_OFFSET
+ phys_end
);
1825 /* we should perform an IPI and flush all tlbs,
1826 * but that can deadlock->flush only current cpu.
1828 __flush_tlb_kernel_range(PAGE_OFFSET
+ phys_start
,
1829 PAGE_OFFSET
+ phys_end
);
1833 unsigned long __init
find_ecache_flush_span(unsigned long size
)
1837 for (i
= 0; i
< pavail_ents
; i
++) {
1838 if (pavail
[i
].reg_size
>= size
)
1839 return pavail
[i
].phys_addr
;
1845 unsigned long PAGE_OFFSET
;
1846 EXPORT_SYMBOL(PAGE_OFFSET
);
1848 unsigned long VMALLOC_END
= 0x0000010000000000UL
;
1849 EXPORT_SYMBOL(VMALLOC_END
);
1851 unsigned long sparc64_va_hole_top
= 0xfffff80000000000UL
;
1852 unsigned long sparc64_va_hole_bottom
= 0x0000080000000000UL
;
1854 static void __init
setup_page_offset(void)
1856 if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
1857 /* Cheetah/Panther support a full 64-bit virtual
1858 * address, so we can use all that our page tables
1861 sparc64_va_hole_top
= 0xfff0000000000000UL
;
1862 sparc64_va_hole_bottom
= 0x0010000000000000UL
;
1865 } else if (tlb_type
== hypervisor
) {
1866 switch (sun4v_chip_type
) {
1867 case SUN4V_CHIP_NIAGARA1
:
1868 case SUN4V_CHIP_NIAGARA2
:
1869 /* T1 and T2 support 48-bit virtual addresses. */
1870 sparc64_va_hole_top
= 0xffff800000000000UL
;
1871 sparc64_va_hole_bottom
= 0x0000800000000000UL
;
1875 case SUN4V_CHIP_NIAGARA3
:
1876 /* T3 supports 48-bit virtual addresses. */
1877 sparc64_va_hole_top
= 0xffff800000000000UL
;
1878 sparc64_va_hole_bottom
= 0x0000800000000000UL
;
1882 case SUN4V_CHIP_NIAGARA4
:
1883 case SUN4V_CHIP_NIAGARA5
:
1884 case SUN4V_CHIP_SPARC64X
:
1885 case SUN4V_CHIP_SPARC_M6
:
1886 /* T4 and later support 52-bit virtual addresses. */
1887 sparc64_va_hole_top
= 0xfff8000000000000UL
;
1888 sparc64_va_hole_bottom
= 0x0008000000000000UL
;
1891 case SUN4V_CHIP_SPARC_M7
:
1892 case SUN4V_CHIP_SPARC_SN
:
1894 /* M7 and later support 52-bit virtual addresses. */
1895 sparc64_va_hole_top
= 0xfff8000000000000UL
;
1896 sparc64_va_hole_bottom
= 0x0008000000000000UL
;
1902 if (max_phys_bits
> MAX_PHYS_ADDRESS_BITS
) {
1903 prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n",
1908 PAGE_OFFSET
= sparc64_va_hole_top
;
1909 VMALLOC_END
= ((sparc64_va_hole_bottom
>> 1) +
1910 (sparc64_va_hole_bottom
>> 2));
1912 pr_info("MM: PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n",
1913 PAGE_OFFSET
, max_phys_bits
);
1914 pr_info("MM: VMALLOC [0x%016lx --> 0x%016lx]\n",
1915 VMALLOC_START
, VMALLOC_END
);
1916 pr_info("MM: VMEMMAP [0x%016lx --> 0x%016lx]\n",
1917 VMEMMAP_BASE
, VMEMMAP_BASE
<< 1);
1920 static void __init
tsb_phys_patch(void)
1922 struct tsb_ldquad_phys_patch_entry
*pquad
;
1923 struct tsb_phys_patch_entry
*p
;
1925 pquad
= &__tsb_ldquad_phys_patch
;
1926 while (pquad
< &__tsb_ldquad_phys_patch_end
) {
1927 unsigned long addr
= pquad
->addr
;
1929 if (tlb_type
== hypervisor
)
1930 *(unsigned int *) addr
= pquad
->sun4v_insn
;
1932 *(unsigned int *) addr
= pquad
->sun4u_insn
;
1934 __asm__
__volatile__("flush %0"
1941 p
= &__tsb_phys_patch
;
1942 while (p
< &__tsb_phys_patch_end
) {
1943 unsigned long addr
= p
->addr
;
1945 *(unsigned int *) addr
= p
->insn
;
1947 __asm__
__volatile__("flush %0"
1955 /* Don't mark as init, we give this to the Hypervisor. */
1956 #ifndef CONFIG_DEBUG_PAGEALLOC
1957 #define NUM_KTSB_DESCR 2
1959 #define NUM_KTSB_DESCR 1
1961 static struct hv_tsb_descr ktsb_descr
[NUM_KTSB_DESCR
];
1963 /* The swapper TSBs are loaded with a base sequence of:
1965 * sethi %uhi(SYMBOL), REG1
1966 * sethi %hi(SYMBOL), REG2
1967 * or REG1, %ulo(SYMBOL), REG1
1968 * or REG2, %lo(SYMBOL), REG2
1969 * sllx REG1, 32, REG1
1970 * or REG1, REG2, REG1
1972 * When we use physical addressing for the TSB accesses, we patch the
1973 * first four instructions in the above sequence.
1976 static void patch_one_ktsb_phys(unsigned int *start
, unsigned int *end
, unsigned long pa
)
1978 unsigned long high_bits
, low_bits
;
1980 high_bits
= (pa
>> 32) & 0xffffffff;
1981 low_bits
= (pa
>> 0) & 0xffffffff;
1983 while (start
< end
) {
1984 unsigned int *ia
= (unsigned int *)(unsigned long)*start
;
1986 ia
[0] = (ia
[0] & ~0x3fffff) | (high_bits
>> 10);
1987 __asm__
__volatile__("flush %0" : : "r" (ia
));
1989 ia
[1] = (ia
[1] & ~0x3fffff) | (low_bits
>> 10);
1990 __asm__
__volatile__("flush %0" : : "r" (ia
+ 1));
1992 ia
[2] = (ia
[2] & ~0x1fff) | (high_bits
& 0x3ff);
1993 __asm__
__volatile__("flush %0" : : "r" (ia
+ 2));
1995 ia
[3] = (ia
[3] & ~0x1fff) | (low_bits
& 0x3ff);
1996 __asm__
__volatile__("flush %0" : : "r" (ia
+ 3));
2002 static void ktsb_phys_patch(void)
2004 extern unsigned int __swapper_tsb_phys_patch
;
2005 extern unsigned int __swapper_tsb_phys_patch_end
;
2006 unsigned long ktsb_pa
;
2008 ktsb_pa
= kern_base
+ ((unsigned long)&swapper_tsb
[0] - KERNBASE
);
2009 patch_one_ktsb_phys(&__swapper_tsb_phys_patch
,
2010 &__swapper_tsb_phys_patch_end
, ktsb_pa
);
2011 #ifndef CONFIG_DEBUG_PAGEALLOC
2013 extern unsigned int __swapper_4m_tsb_phys_patch
;
2014 extern unsigned int __swapper_4m_tsb_phys_patch_end
;
2015 ktsb_pa
= (kern_base
+
2016 ((unsigned long)&swapper_4m_tsb
[0] - KERNBASE
));
2017 patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch
,
2018 &__swapper_4m_tsb_phys_patch_end
, ktsb_pa
);
2023 static void __init
sun4v_ktsb_init(void)
2025 unsigned long ktsb_pa
;
2027 /* First KTSB for PAGE_SIZE mappings. */
2028 ktsb_pa
= kern_base
+ ((unsigned long)&swapper_tsb
[0] - KERNBASE
);
2030 switch (PAGE_SIZE
) {
2033 ktsb_descr
[0].pgsz_idx
= HV_PGSZ_IDX_8K
;
2034 ktsb_descr
[0].pgsz_mask
= HV_PGSZ_MASK_8K
;
2038 ktsb_descr
[0].pgsz_idx
= HV_PGSZ_IDX_64K
;
2039 ktsb_descr
[0].pgsz_mask
= HV_PGSZ_MASK_64K
;
2043 ktsb_descr
[0].pgsz_idx
= HV_PGSZ_IDX_512K
;
2044 ktsb_descr
[0].pgsz_mask
= HV_PGSZ_MASK_512K
;
2047 case 4 * 1024 * 1024:
2048 ktsb_descr
[0].pgsz_idx
= HV_PGSZ_IDX_4MB
;
2049 ktsb_descr
[0].pgsz_mask
= HV_PGSZ_MASK_4MB
;
2053 ktsb_descr
[0].assoc
= 1;
2054 ktsb_descr
[0].num_ttes
= KERNEL_TSB_NENTRIES
;
2055 ktsb_descr
[0].ctx_idx
= 0;
2056 ktsb_descr
[0].tsb_base
= ktsb_pa
;
2057 ktsb_descr
[0].resv
= 0;
2059 #ifndef CONFIG_DEBUG_PAGEALLOC
2060 /* Second KTSB for 4MB/256MB/2GB/16GB mappings. */
2061 ktsb_pa
= (kern_base
+
2062 ((unsigned long)&swapper_4m_tsb
[0] - KERNBASE
));
2064 ktsb_descr
[1].pgsz_idx
= HV_PGSZ_IDX_4MB
;
2065 ktsb_descr
[1].pgsz_mask
= ((HV_PGSZ_MASK_4MB
|
2066 HV_PGSZ_MASK_256MB
|
2068 HV_PGSZ_MASK_16GB
) &
2070 ktsb_descr
[1].assoc
= 1;
2071 ktsb_descr
[1].num_ttes
= KERNEL_TSB4M_NENTRIES
;
2072 ktsb_descr
[1].ctx_idx
= 0;
2073 ktsb_descr
[1].tsb_base
= ktsb_pa
;
2074 ktsb_descr
[1].resv
= 0;
2078 void sun4v_ktsb_register(void)
2080 unsigned long pa
, ret
;
2082 pa
= kern_base
+ ((unsigned long)&ktsb_descr
[0] - KERNBASE
);
2084 ret
= sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR
, pa
);
2086 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
2087 "errors with %lx\n", pa
, ret
);
2092 static void __init
sun4u_linear_pte_xor_finalize(void)
2094 #ifndef CONFIG_DEBUG_PAGEALLOC
2095 /* This is where we would add Panther support for
2096 * 32MB and 256MB pages.
2101 static void __init
sun4v_linear_pte_xor_finalize(void)
2103 unsigned long pagecv_flag
;
2105 /* Bit 9 of TTE is no longer CV bit on M7 processor and it instead
2106 * enables MCD error. Do not set bit 9 on M7 processor.
2108 switch (sun4v_chip_type
) {
2109 case SUN4V_CHIP_SPARC_M7
:
2110 case SUN4V_CHIP_SPARC_SN
:
2114 pagecv_flag
= _PAGE_CV_4V
;
2117 #ifndef CONFIG_DEBUG_PAGEALLOC
2118 if (cpu_pgsz_mask
& HV_PGSZ_MASK_256MB
) {
2119 kern_linear_pte_xor
[1] = (_PAGE_VALID
| _PAGE_SZ256MB_4V
) ^
2121 kern_linear_pte_xor
[1] |= (_PAGE_CP_4V
| pagecv_flag
|
2122 _PAGE_P_4V
| _PAGE_W_4V
);
2124 kern_linear_pte_xor
[1] = kern_linear_pte_xor
[0];
2127 if (cpu_pgsz_mask
& HV_PGSZ_MASK_2GB
) {
2128 kern_linear_pte_xor
[2] = (_PAGE_VALID
| _PAGE_SZ2GB_4V
) ^
2130 kern_linear_pte_xor
[2] |= (_PAGE_CP_4V
| pagecv_flag
|
2131 _PAGE_P_4V
| _PAGE_W_4V
);
2133 kern_linear_pte_xor
[2] = kern_linear_pte_xor
[1];
2136 if (cpu_pgsz_mask
& HV_PGSZ_MASK_16GB
) {
2137 kern_linear_pte_xor
[3] = (_PAGE_VALID
| _PAGE_SZ16GB_4V
) ^
2139 kern_linear_pte_xor
[3] |= (_PAGE_CP_4V
| pagecv_flag
|
2140 _PAGE_P_4V
| _PAGE_W_4V
);
2142 kern_linear_pte_xor
[3] = kern_linear_pte_xor
[2];
2147 /* paging_init() sets up the page tables */
2149 static unsigned long last_valid_pfn
;
2151 static void sun4u_pgprot_init(void);
2152 static void sun4v_pgprot_init(void);
2154 static phys_addr_t __init
available_memory(void)
2156 phys_addr_t available
= 0ULL;
2157 phys_addr_t pa_start
, pa_end
;
2160 for_each_free_mem_range(i
, NUMA_NO_NODE
, MEMBLOCK_NONE
, &pa_start
,
2162 available
= available
+ (pa_end
- pa_start
);
2167 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
2168 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
2169 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2170 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2171 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2172 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2174 /* We need to exclude reserved regions. This exclusion will include
2175 * vmlinux and initrd. To be more precise the initrd size could be used to
2176 * compute a new lower limit because it is freed later during initialization.
2178 static void __init
reduce_memory(phys_addr_t limit_ram
)
2180 phys_addr_t avail_ram
= available_memory();
2181 phys_addr_t pa_start
, pa_end
;
2184 if (limit_ram
>= avail_ram
)
2187 for_each_free_mem_range(i
, NUMA_NO_NODE
, MEMBLOCK_NONE
, &pa_start
,
2189 phys_addr_t region_size
= pa_end
- pa_start
;
2190 phys_addr_t clip_start
= pa_start
;
2192 avail_ram
= avail_ram
- region_size
;
2193 /* Are we consuming too much? */
2194 if (avail_ram
< limit_ram
) {
2195 phys_addr_t give_back
= limit_ram
- avail_ram
;
2197 region_size
= region_size
- give_back
;
2198 clip_start
= clip_start
+ give_back
;
2201 memblock_remove(clip_start
, region_size
);
2203 if (avail_ram
<= limit_ram
)
2209 void __init
paging_init(void)
2211 unsigned long end_pfn
, shift
, phys_base
;
2212 unsigned long real_end
, i
;
2214 setup_page_offset();
2216 /* These build time checkes make sure that the dcache_dirty_cpu()
2217 * page->flags usage will work.
2219 * When a page gets marked as dcache-dirty, we store the
2220 * cpu number starting at bit 32 in the page->flags. Also,
2221 * functions like clear_dcache_dirty_cpu use the cpu mask
2222 * in 13-bit signed-immediate instruction fields.
2226 * Page flags must not reach into upper 32 bits that are used
2227 * for the cpu number
2229 BUILD_BUG_ON(NR_PAGEFLAGS
> 32);
2232 * The bit fields placed in the high range must not reach below
2233 * the 32 bit boundary. Otherwise we cannot place the cpu field
2234 * at the 32 bit boundary.
2236 BUILD_BUG_ON(SECTIONS_WIDTH
+ NODES_WIDTH
+ ZONES_WIDTH
+
2237 ilog2(roundup_pow_of_two(NR_CPUS
)) > 32);
2239 BUILD_BUG_ON(NR_CPUS
> 4096);
2241 kern_base
= (prom_boot_mapping_phys_low
>> ILOG2_4MB
) << ILOG2_4MB
;
2242 kern_size
= (unsigned long)&_end
- (unsigned long)KERNBASE
;
2244 /* Invalidate both kernel TSBs. */
2245 memset(swapper_tsb
, 0x40, sizeof(swapper_tsb
));
2246 #ifndef CONFIG_DEBUG_PAGEALLOC
2247 memset(swapper_4m_tsb
, 0x40, sizeof(swapper_4m_tsb
));
2250 /* TTE.cv bit on sparc v9 occupies the same position as TTE.mcde
2251 * bit on M7 processor. This is a conflicting usage of the same
2252 * bit. Enabling TTE.cv on M7 would turn on Memory Corruption
2253 * Detection error on all pages and this will lead to problems
2254 * later. Kernel does not run with MCD enabled and hence rest
2255 * of the required steps to fully configure memory corruption
2256 * detection are not taken. We need to ensure TTE.mcde is not
2257 * set on M7 processor. Compute the value of cacheability
2258 * flag for use later taking this into consideration.
2260 switch (sun4v_chip_type
) {
2261 case SUN4V_CHIP_SPARC_M7
:
2262 case SUN4V_CHIP_SPARC_SN
:
2263 page_cache4v_flag
= _PAGE_CP_4V
;
2266 page_cache4v_flag
= _PAGE_CACHE_4V
;
2270 if (tlb_type
== hypervisor
)
2271 sun4v_pgprot_init();
2273 sun4u_pgprot_init();
2275 if (tlb_type
== cheetah_plus
||
2276 tlb_type
== hypervisor
) {
2281 if (tlb_type
== hypervisor
)
2282 sun4v_patch_tlb_handlers();
2284 /* Find available physical memory...
2286 * Read it twice in order to work around a bug in openfirmware.
2287 * The call to grab this table itself can cause openfirmware to
2288 * allocate memory, which in turn can take away some space from
2289 * the list of available memory. Reading it twice makes sure
2290 * we really do get the final value.
2292 read_obp_translations();
2293 read_obp_memory("reg", &pall
[0], &pall_ents
);
2294 read_obp_memory("available", &pavail
[0], &pavail_ents
);
2295 read_obp_memory("available", &pavail
[0], &pavail_ents
);
2297 phys_base
= 0xffffffffffffffffUL
;
2298 for (i
= 0; i
< pavail_ents
; i
++) {
2299 phys_base
= min(phys_base
, pavail
[i
].phys_addr
);
2300 memblock_add(pavail
[i
].phys_addr
, pavail
[i
].reg_size
);
2303 memblock_reserve(kern_base
, kern_size
);
2305 find_ramdisk(phys_base
);
2307 if (cmdline_memory_size
)
2308 reduce_memory(cmdline_memory_size
);
2310 memblock_allow_resize();
2311 memblock_dump_all();
2313 set_bit(0, mmu_context_bmap
);
2315 shift
= kern_base
+ PAGE_OFFSET
- ((unsigned long)KERNBASE
);
2317 real_end
= (unsigned long)_end
;
2318 num_kernel_image_mappings
= DIV_ROUND_UP(real_end
- KERNBASE
, 1 << ILOG2_4MB
);
2319 printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
2320 num_kernel_image_mappings
);
2322 /* Set kernel pgd to upper alias so physical page computations
2325 init_mm
.pgd
+= ((shift
) / (sizeof(pgd_t
)));
2327 memset(swapper_pg_dir
, 0, sizeof(swapper_pg_dir
));
2329 inherit_prom_mappings();
2331 /* Ok, we can use our TLB miss and window trap handlers safely. */
2336 prom_build_devicetree();
2337 of_populate_present_mask();
2339 of_fill_in_cpu_data();
2342 if (tlb_type
== hypervisor
) {
2344 mdesc_populate_present_mask(cpu_all_mask
);
2346 mdesc_fill_in_cpu_data(cpu_all_mask
);
2348 mdesc_get_page_sizes(cpu_all_mask
, &cpu_pgsz_mask
);
2350 sun4v_linear_pte_xor_finalize();
2353 sun4v_ktsb_register();
2355 unsigned long impl
, ver
;
2357 cpu_pgsz_mask
= (HV_PGSZ_MASK_8K
| HV_PGSZ_MASK_64K
|
2358 HV_PGSZ_MASK_512K
| HV_PGSZ_MASK_4MB
);
2360 __asm__
__volatile__("rdpr %%ver, %0" : "=r" (ver
));
2361 impl
= ((ver
>> 32) & 0xffff);
2362 if (impl
== PANTHER_IMPL
)
2363 cpu_pgsz_mask
|= (HV_PGSZ_MASK_32MB
|
2364 HV_PGSZ_MASK_256MB
);
2366 sun4u_linear_pte_xor_finalize();
2369 /* Flush the TLBs and the 4M TSB so that the updated linear
2370 * pte XOR settings are realized for all mappings.
2373 #ifndef CONFIG_DEBUG_PAGEALLOC
2374 memset(swapper_4m_tsb
, 0x40, sizeof(swapper_4m_tsb
));
2378 /* Setup bootmem... */
2379 last_valid_pfn
= end_pfn
= bootmem_init(phys_base
);
2381 kernel_physical_mapping_init();
2384 unsigned long max_zone_pfns
[MAX_NR_ZONES
];
2386 memset(max_zone_pfns
, 0, sizeof(max_zone_pfns
));
2388 max_zone_pfns
[ZONE_NORMAL
] = end_pfn
;
2390 free_area_init_nodes(max_zone_pfns
);
2393 printk("Booting Linux...\n");
2396 int page_in_phys_avail(unsigned long paddr
)
2402 for (i
= 0; i
< pavail_ents
; i
++) {
2403 unsigned long start
, end
;
2405 start
= pavail
[i
].phys_addr
;
2406 end
= start
+ pavail
[i
].reg_size
;
2408 if (paddr
>= start
&& paddr
< end
)
2411 if (paddr
>= kern_base
&& paddr
< (kern_base
+ kern_size
))
2413 #ifdef CONFIG_BLK_DEV_INITRD
2414 if (paddr
>= __pa(initrd_start
) &&
2415 paddr
< __pa(PAGE_ALIGN(initrd_end
)))
2422 static void __init
register_page_bootmem_info(void)
2424 #ifdef CONFIG_NEED_MULTIPLE_NODES
2427 for_each_online_node(i
)
2428 if (NODE_DATA(i
)->node_spanned_pages
)
2429 register_page_bootmem_info_node(NODE_DATA(i
));
2432 void __init
mem_init(void)
2434 high_memory
= __va(last_valid_pfn
<< PAGE_SHIFT
);
2436 register_page_bootmem_info();
2440 * Set up the zero page, mark it reserved, so that page count
2441 * is not manipulated when freeing the page from user ptes.
2443 mem_map_zero
= alloc_pages(GFP_KERNEL
|__GFP_ZERO
, 0);
2444 if (mem_map_zero
== NULL
) {
2445 prom_printf("paging_init: Cannot alloc zero page.\n");
2448 mark_page_reserved(mem_map_zero
);
2450 mem_init_print_info(NULL
);
2452 if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
)
2453 cheetah_ecache_flush_init();
2456 void free_initmem(void)
2458 unsigned long addr
, initend
;
2461 /* If the physical memory maps were trimmed by kernel command
2462 * line options, don't even try freeing this initmem stuff up.
2463 * The kernel image could have been in the trimmed out region
2464 * and if so the freeing below will free invalid page structs.
2466 if (cmdline_memory_size
)
2470 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2472 addr
= PAGE_ALIGN((unsigned long)(__init_begin
));
2473 initend
= (unsigned long)(__init_end
) & PAGE_MASK
;
2474 for (; addr
< initend
; addr
+= PAGE_SIZE
) {
2478 ((unsigned long) __va(kern_base
)) -
2479 ((unsigned long) KERNBASE
));
2480 memset((void *)addr
, POISON_FREE_INITMEM
, PAGE_SIZE
);
2483 free_reserved_page(virt_to_page(page
));
2487 #ifdef CONFIG_BLK_DEV_INITRD
2488 void free_initrd_mem(unsigned long start
, unsigned long end
)
2490 free_reserved_area((void *)start
, (void *)end
, POISON_FREE_INITMEM
,
2495 pgprot_t PAGE_KERNEL __read_mostly
;
2496 EXPORT_SYMBOL(PAGE_KERNEL
);
2498 pgprot_t PAGE_KERNEL_LOCKED __read_mostly
;
2499 pgprot_t PAGE_COPY __read_mostly
;
2501 pgprot_t PAGE_SHARED __read_mostly
;
2502 EXPORT_SYMBOL(PAGE_SHARED
);
2504 unsigned long pg_iobits __read_mostly
;
2506 unsigned long _PAGE_IE __read_mostly
;
2507 EXPORT_SYMBOL(_PAGE_IE
);
2509 unsigned long _PAGE_E __read_mostly
;
2510 EXPORT_SYMBOL(_PAGE_E
);
2512 unsigned long _PAGE_CACHE __read_mostly
;
2513 EXPORT_SYMBOL(_PAGE_CACHE
);
2515 #ifdef CONFIG_SPARSEMEM_VMEMMAP
2516 int __meminit
vmemmap_populate(unsigned long vstart
, unsigned long vend
,
2519 unsigned long pte_base
;
2521 pte_base
= (_PAGE_VALID
| _PAGE_SZ4MB_4U
|
2522 _PAGE_CP_4U
| _PAGE_CV_4U
|
2523 _PAGE_P_4U
| _PAGE_W_4U
);
2524 if (tlb_type
== hypervisor
)
2525 pte_base
= (_PAGE_VALID
| _PAGE_SZ4MB_4V
|
2526 page_cache4v_flag
| _PAGE_P_4V
| _PAGE_W_4V
);
2528 pte_base
|= _PAGE_PMD_HUGE
;
2530 vstart
= vstart
& PMD_MASK
;
2531 vend
= ALIGN(vend
, PMD_SIZE
);
2532 for (; vstart
< vend
; vstart
+= PMD_SIZE
) {
2533 pgd_t
*pgd
= pgd_offset_k(vstart
);
2538 if (pgd_none(*pgd
)) {
2539 pud_t
*new = vmemmap_alloc_block(PAGE_SIZE
, node
);
2543 pgd_populate(&init_mm
, pgd
, new);
2546 pud
= pud_offset(pgd
, vstart
);
2547 if (pud_none(*pud
)) {
2548 pmd_t
*new = vmemmap_alloc_block(PAGE_SIZE
, node
);
2552 pud_populate(&init_mm
, pud
, new);
2555 pmd
= pmd_offset(pud
, vstart
);
2557 pte
= pmd_val(*pmd
);
2558 if (!(pte
& _PAGE_VALID
)) {
2559 void *block
= vmemmap_alloc_block(PMD_SIZE
, node
);
2564 pmd_val(*pmd
) = pte_base
| __pa(block
);
2571 void vmemmap_free(unsigned long start
, unsigned long end
)
2574 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
2576 static void prot_init_common(unsigned long page_none
,
2577 unsigned long page_shared
,
2578 unsigned long page_copy
,
2579 unsigned long page_readonly
,
2580 unsigned long page_exec_bit
)
2582 PAGE_COPY
= __pgprot(page_copy
);
2583 PAGE_SHARED
= __pgprot(page_shared
);
2585 protection_map
[0x0] = __pgprot(page_none
);
2586 protection_map
[0x1] = __pgprot(page_readonly
& ~page_exec_bit
);
2587 protection_map
[0x2] = __pgprot(page_copy
& ~page_exec_bit
);
2588 protection_map
[0x3] = __pgprot(page_copy
& ~page_exec_bit
);
2589 protection_map
[0x4] = __pgprot(page_readonly
);
2590 protection_map
[0x5] = __pgprot(page_readonly
);
2591 protection_map
[0x6] = __pgprot(page_copy
);
2592 protection_map
[0x7] = __pgprot(page_copy
);
2593 protection_map
[0x8] = __pgprot(page_none
);
2594 protection_map
[0x9] = __pgprot(page_readonly
& ~page_exec_bit
);
2595 protection_map
[0xa] = __pgprot(page_shared
& ~page_exec_bit
);
2596 protection_map
[0xb] = __pgprot(page_shared
& ~page_exec_bit
);
2597 protection_map
[0xc] = __pgprot(page_readonly
);
2598 protection_map
[0xd] = __pgprot(page_readonly
);
2599 protection_map
[0xe] = __pgprot(page_shared
);
2600 protection_map
[0xf] = __pgprot(page_shared
);
2603 static void __init
sun4u_pgprot_init(void)
2605 unsigned long page_none
, page_shared
, page_copy
, page_readonly
;
2606 unsigned long page_exec_bit
;
2609 PAGE_KERNEL
= __pgprot (_PAGE_PRESENT_4U
| _PAGE_VALID
|
2610 _PAGE_CACHE_4U
| _PAGE_P_4U
|
2611 __ACCESS_BITS_4U
| __DIRTY_BITS_4U
|
2613 PAGE_KERNEL_LOCKED
= __pgprot (_PAGE_PRESENT_4U
| _PAGE_VALID
|
2614 _PAGE_CACHE_4U
| _PAGE_P_4U
|
2615 __ACCESS_BITS_4U
| __DIRTY_BITS_4U
|
2616 _PAGE_EXEC_4U
| _PAGE_L_4U
);
2618 _PAGE_IE
= _PAGE_IE_4U
;
2619 _PAGE_E
= _PAGE_E_4U
;
2620 _PAGE_CACHE
= _PAGE_CACHE_4U
;
2622 pg_iobits
= (_PAGE_VALID
| _PAGE_PRESENT_4U
| __DIRTY_BITS_4U
|
2623 __ACCESS_BITS_4U
| _PAGE_E_4U
);
2625 #ifdef CONFIG_DEBUG_PAGEALLOC
2626 kern_linear_pte_xor
[0] = _PAGE_VALID
^ PAGE_OFFSET
;
2628 kern_linear_pte_xor
[0] = (_PAGE_VALID
| _PAGE_SZ4MB_4U
) ^
2631 kern_linear_pte_xor
[0] |= (_PAGE_CP_4U
| _PAGE_CV_4U
|
2632 _PAGE_P_4U
| _PAGE_W_4U
);
2634 for (i
= 1; i
< 4; i
++)
2635 kern_linear_pte_xor
[i
] = kern_linear_pte_xor
[0];
2637 _PAGE_ALL_SZ_BITS
= (_PAGE_SZ4MB_4U
| _PAGE_SZ512K_4U
|
2638 _PAGE_SZ64K_4U
| _PAGE_SZ8K_4U
|
2639 _PAGE_SZ32MB_4U
| _PAGE_SZ256MB_4U
);
2642 page_none
= _PAGE_PRESENT_4U
| _PAGE_ACCESSED_4U
| _PAGE_CACHE_4U
;
2643 page_shared
= (_PAGE_VALID
| _PAGE_PRESENT_4U
| _PAGE_CACHE_4U
|
2644 __ACCESS_BITS_4U
| _PAGE_WRITE_4U
| _PAGE_EXEC_4U
);
2645 page_copy
= (_PAGE_VALID
| _PAGE_PRESENT_4U
| _PAGE_CACHE_4U
|
2646 __ACCESS_BITS_4U
| _PAGE_EXEC_4U
);
2647 page_readonly
= (_PAGE_VALID
| _PAGE_PRESENT_4U
| _PAGE_CACHE_4U
|
2648 __ACCESS_BITS_4U
| _PAGE_EXEC_4U
);
2650 page_exec_bit
= _PAGE_EXEC_4U
;
2652 prot_init_common(page_none
, page_shared
, page_copy
, page_readonly
,
2656 static void __init
sun4v_pgprot_init(void)
2658 unsigned long page_none
, page_shared
, page_copy
, page_readonly
;
2659 unsigned long page_exec_bit
;
2662 PAGE_KERNEL
= __pgprot (_PAGE_PRESENT_4V
| _PAGE_VALID
|
2663 page_cache4v_flag
| _PAGE_P_4V
|
2664 __ACCESS_BITS_4V
| __DIRTY_BITS_4V
|
2666 PAGE_KERNEL_LOCKED
= PAGE_KERNEL
;
2668 _PAGE_IE
= _PAGE_IE_4V
;
2669 _PAGE_E
= _PAGE_E_4V
;
2670 _PAGE_CACHE
= page_cache4v_flag
;
2672 #ifdef CONFIG_DEBUG_PAGEALLOC
2673 kern_linear_pte_xor
[0] = _PAGE_VALID
^ PAGE_OFFSET
;
2675 kern_linear_pte_xor
[0] = (_PAGE_VALID
| _PAGE_SZ4MB_4V
) ^
2678 kern_linear_pte_xor
[0] |= (page_cache4v_flag
| _PAGE_P_4V
|
2681 for (i
= 1; i
< 4; i
++)
2682 kern_linear_pte_xor
[i
] = kern_linear_pte_xor
[0];
2684 pg_iobits
= (_PAGE_VALID
| _PAGE_PRESENT_4V
| __DIRTY_BITS_4V
|
2685 __ACCESS_BITS_4V
| _PAGE_E_4V
);
2687 _PAGE_ALL_SZ_BITS
= (_PAGE_SZ16GB_4V
| _PAGE_SZ2GB_4V
|
2688 _PAGE_SZ256MB_4V
| _PAGE_SZ32MB_4V
|
2689 _PAGE_SZ4MB_4V
| _PAGE_SZ512K_4V
|
2690 _PAGE_SZ64K_4V
| _PAGE_SZ8K_4V
);
2692 page_none
= _PAGE_PRESENT_4V
| _PAGE_ACCESSED_4V
| page_cache4v_flag
;
2693 page_shared
= (_PAGE_VALID
| _PAGE_PRESENT_4V
| page_cache4v_flag
|
2694 __ACCESS_BITS_4V
| _PAGE_WRITE_4V
| _PAGE_EXEC_4V
);
2695 page_copy
= (_PAGE_VALID
| _PAGE_PRESENT_4V
| page_cache4v_flag
|
2696 __ACCESS_BITS_4V
| _PAGE_EXEC_4V
);
2697 page_readonly
= (_PAGE_VALID
| _PAGE_PRESENT_4V
| page_cache4v_flag
|
2698 __ACCESS_BITS_4V
| _PAGE_EXEC_4V
);
2700 page_exec_bit
= _PAGE_EXEC_4V
;
2702 prot_init_common(page_none
, page_shared
, page_copy
, page_readonly
,
2706 unsigned long pte_sz_bits(unsigned long sz
)
2708 if (tlb_type
== hypervisor
) {
2712 return _PAGE_SZ8K_4V
;
2714 return _PAGE_SZ64K_4V
;
2716 return _PAGE_SZ512K_4V
;
2717 case 4 * 1024 * 1024:
2718 return _PAGE_SZ4MB_4V
;
2724 return _PAGE_SZ8K_4U
;
2726 return _PAGE_SZ64K_4U
;
2728 return _PAGE_SZ512K_4U
;
2729 case 4 * 1024 * 1024:
2730 return _PAGE_SZ4MB_4U
;
2735 pte_t
mk_pte_io(unsigned long page
, pgprot_t prot
, int space
, unsigned long page_size
)
2739 pte_val(pte
) = page
| pgprot_val(pgprot_noncached(prot
));
2740 pte_val(pte
) |= (((unsigned long)space
) << 32);
2741 pte_val(pte
) |= pte_sz_bits(page_size
);
2746 static unsigned long kern_large_tte(unsigned long paddr
)
2750 val
= (_PAGE_VALID
| _PAGE_SZ4MB_4U
|
2751 _PAGE_CP_4U
| _PAGE_CV_4U
| _PAGE_P_4U
|
2752 _PAGE_EXEC_4U
| _PAGE_L_4U
| _PAGE_W_4U
);
2753 if (tlb_type
== hypervisor
)
2754 val
= (_PAGE_VALID
| _PAGE_SZ4MB_4V
|
2755 page_cache4v_flag
| _PAGE_P_4V
|
2756 _PAGE_EXEC_4V
| _PAGE_W_4V
);
2761 /* If not locked, zap it. */
2762 void __flush_tlb_all(void)
2764 unsigned long pstate
;
2767 __asm__
__volatile__("flushw\n\t"
2768 "rdpr %%pstate, %0\n\t"
2769 "wrpr %0, %1, %%pstate"
2772 if (tlb_type
== hypervisor
) {
2773 sun4v_mmu_demap_all();
2774 } else if (tlb_type
== spitfire
) {
2775 for (i
= 0; i
< 64; i
++) {
2776 /* Spitfire Errata #32 workaround */
2777 /* NOTE: Always runs on spitfire, so no
2778 * cheetah+ page size encodings.
2780 __asm__
__volatile__("stxa %0, [%1] %2\n\t"
2784 "r" (PRIMARY_CONTEXT
), "i" (ASI_DMMU
));
2786 if (!(spitfire_get_dtlb_data(i
) & _PAGE_L_4U
)) {
2787 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
2790 : "r" (TLB_TAG_ACCESS
), "i" (ASI_DMMU
));
2791 spitfire_put_dtlb_data(i
, 0x0UL
);
2794 /* Spitfire Errata #32 workaround */
2795 /* NOTE: Always runs on spitfire, so no
2796 * cheetah+ page size encodings.
2798 __asm__
__volatile__("stxa %0, [%1] %2\n\t"
2802 "r" (PRIMARY_CONTEXT
), "i" (ASI_DMMU
));
2804 if (!(spitfire_get_itlb_data(i
) & _PAGE_L_4U
)) {
2805 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
2808 : "r" (TLB_TAG_ACCESS
), "i" (ASI_IMMU
));
2809 spitfire_put_itlb_data(i
, 0x0UL
);
2812 } else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
2813 cheetah_flush_dtlb_all();
2814 cheetah_flush_itlb_all();
2816 __asm__
__volatile__("wrpr %0, 0, %%pstate"
2820 pte_t
*pte_alloc_one_kernel(struct mm_struct
*mm
,
2821 unsigned long address
)
2823 struct page
*page
= alloc_page(GFP_KERNEL
| __GFP_NOTRACK
| __GFP_ZERO
);
2827 pte
= (pte_t
*) page_address(page
);
2832 pgtable_t
pte_alloc_one(struct mm_struct
*mm
,
2833 unsigned long address
)
2835 struct page
*page
= alloc_page(GFP_KERNEL
| __GFP_NOTRACK
| __GFP_ZERO
);
2838 if (!pgtable_page_ctor(page
)) {
2839 free_hot_cold_page(page
, 0);
2842 return (pte_t
*) page_address(page
);
2845 void pte_free_kernel(struct mm_struct
*mm
, pte_t
*pte
)
2847 free_page((unsigned long)pte
);
2850 static void __pte_free(pgtable_t pte
)
2852 struct page
*page
= virt_to_page(pte
);
2854 pgtable_page_dtor(page
);
2858 void pte_free(struct mm_struct
*mm
, pgtable_t pte
)
2863 void pgtable_free(void *table
, bool is_page
)
2868 kmem_cache_free(pgtable_cache
, table
);
2871 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
2872 void update_mmu_cache_pmd(struct vm_area_struct
*vma
, unsigned long addr
,
2875 unsigned long pte
, flags
;
2876 struct mm_struct
*mm
;
2879 if (!pmd_large(entry
) || !pmd_young(entry
))
2882 pte
= pmd_val(entry
);
2884 /* Don't insert a non-valid PMD into the TSB, we'll deadlock. */
2885 if (!(pte
& _PAGE_VALID
))
2888 /* We are fabricating 8MB pages using 4MB real hw pages. */
2889 pte
|= (addr
& (1UL << REAL_HPAGE_SHIFT
));
2893 spin_lock_irqsave(&mm
->context
.lock
, flags
);
2895 if (mm
->context
.tsb_block
[MM_TSB_HUGE
].tsb
!= NULL
)
2896 __update_mmu_tsb_insert(mm
, MM_TSB_HUGE
, REAL_HPAGE_SHIFT
,
2899 spin_unlock_irqrestore(&mm
->context
.lock
, flags
);
2901 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
2903 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
2904 static void context_reload(void *__data
)
2906 struct mm_struct
*mm
= __data
;
2908 if (mm
== current
->mm
)
2909 load_secondary_context(mm
);
2912 void hugetlb_setup(struct pt_regs
*regs
)
2914 struct mm_struct
*mm
= current
->mm
;
2915 struct tsb_config
*tp
;
2917 if (faulthandler_disabled() || !mm
) {
2918 const struct exception_table_entry
*entry
;
2920 entry
= search_exception_tables(regs
->tpc
);
2922 regs
->tpc
= entry
->fixup
;
2923 regs
->tnpc
= regs
->tpc
+ 4;
2926 pr_alert("Unexpected HugeTLB setup in atomic context.\n");
2927 die_if_kernel("HugeTSB in atomic", regs
);
2930 tp
= &mm
->context
.tsb_block
[MM_TSB_HUGE
];
2931 if (likely(tp
->tsb
== NULL
))
2932 tsb_grow(mm
, MM_TSB_HUGE
, 0);
2934 tsb_context_switch(mm
);
2937 /* On UltraSPARC-III+ and later, configure the second half of
2938 * the Data-TLB for huge pages.
2940 if (tlb_type
== cheetah_plus
) {
2941 bool need_context_reload
= false;
2944 spin_lock_irq(&ctx_alloc_lock
);
2945 ctx
= mm
->context
.sparc64_ctx_val
;
2946 ctx
&= ~CTX_PGSZ_MASK
;
2947 ctx
|= CTX_PGSZ_BASE
<< CTX_PGSZ0_SHIFT
;
2948 ctx
|= CTX_PGSZ_HUGE
<< CTX_PGSZ1_SHIFT
;
2950 if (ctx
!= mm
->context
.sparc64_ctx_val
) {
2951 /* When changing the page size fields, we
2952 * must perform a context flush so that no
2953 * stale entries match. This flush must
2954 * occur with the original context register
2957 do_flush_tlb_mm(mm
);
2959 /* Reload the context register of all processors
2960 * also executing in this address space.
2962 mm
->context
.sparc64_ctx_val
= ctx
;
2963 need_context_reload
= true;
2965 spin_unlock_irq(&ctx_alloc_lock
);
2967 if (need_context_reload
)
2968 on_each_cpu(context_reload
, mm
, 0);
2973 static struct resource code_resource
= {
2974 .name
= "Kernel code",
2975 .flags
= IORESOURCE_BUSY
| IORESOURCE_SYSTEM_RAM
2978 static struct resource data_resource
= {
2979 .name
= "Kernel data",
2980 .flags
= IORESOURCE_BUSY
| IORESOURCE_SYSTEM_RAM
2983 static struct resource bss_resource
= {
2984 .name
= "Kernel bss",
2985 .flags
= IORESOURCE_BUSY
| IORESOURCE_SYSTEM_RAM
2988 static inline resource_size_t
compute_kern_paddr(void *addr
)
2990 return (resource_size_t
) (addr
- KERNBASE
+ kern_base
);
2993 static void __init
kernel_lds_init(void)
2995 code_resource
.start
= compute_kern_paddr(_text
);
2996 code_resource
.end
= compute_kern_paddr(_etext
- 1);
2997 data_resource
.start
= compute_kern_paddr(_etext
);
2998 data_resource
.end
= compute_kern_paddr(_edata
- 1);
2999 bss_resource
.start
= compute_kern_paddr(__bss_start
);
3000 bss_resource
.end
= compute_kern_paddr(_end
- 1);
3003 static int __init
report_memory(void)
3006 struct resource
*res
;
3010 for (i
= 0; i
< pavail_ents
; i
++) {
3011 res
= kzalloc(sizeof(struct resource
), GFP_KERNEL
);
3014 pr_warn("Failed to allocate source.\n");
3018 res
->name
= "System RAM";
3019 res
->start
= pavail
[i
].phys_addr
;
3020 res
->end
= pavail
[i
].phys_addr
+ pavail
[i
].reg_size
- 1;
3021 res
->flags
= IORESOURCE_BUSY
| IORESOURCE_SYSTEM_RAM
;
3023 if (insert_resource(&iomem_resource
, res
) < 0) {
3024 pr_warn("Resource insertion failed.\n");
3028 insert_resource(res
, &code_resource
);
3029 insert_resource(res
, &data_resource
);
3030 insert_resource(res
, &bss_resource
);
3035 arch_initcall(report_memory
);
3038 #define do_flush_tlb_kernel_range smp_flush_tlb_kernel_range
3040 #define do_flush_tlb_kernel_range __flush_tlb_kernel_range
3043 void flush_tlb_kernel_range(unsigned long start
, unsigned long end
)
3045 if (start
< HI_OBP_ADDRESS
&& end
> LOW_OBP_ADDRESS
) {
3046 if (start
< LOW_OBP_ADDRESS
) {
3047 flush_tsb_kernel_range(start
, LOW_OBP_ADDRESS
);
3048 do_flush_tlb_kernel_range(start
, LOW_OBP_ADDRESS
);
3050 if (end
> HI_OBP_ADDRESS
) {
3051 flush_tsb_kernel_range(HI_OBP_ADDRESS
, end
);
3052 do_flush_tlb_kernel_range(HI_OBP_ADDRESS
, end
);
3055 flush_tsb_kernel_range(start
, end
);
3056 do_flush_tlb_kernel_range(start
, end
);