2 * arch/sparc64/mm/init.c
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 #include <linux/module.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/string.h>
12 #include <linux/init.h>
13 #include <linux/bootmem.h>
15 #include <linux/hugetlb.h>
16 #include <linux/initrd.h>
17 #include <linux/swap.h>
18 #include <linux/pagemap.h>
19 #include <linux/poison.h>
21 #include <linux/seq_file.h>
22 #include <linux/kprobes.h>
23 #include <linux/cache.h>
24 #include <linux/sort.h>
25 #include <linux/percpu.h>
26 #include <linux/memblock.h>
27 #include <linux/mmzone.h>
28 #include <linux/gfp.h>
32 #include <asm/pgalloc.h>
33 #include <asm/pgtable.h>
34 #include <asm/oplib.h>
35 #include <asm/iommu.h>
37 #include <asm/uaccess.h>
38 #include <asm/mmu_context.h>
39 #include <asm/tlbflush.h>
41 #include <asm/starfire.h>
43 #include <asm/spitfire.h>
44 #include <asm/sections.h>
46 #include <asm/hypervisor.h>
48 #include <asm/mdesc.h>
49 #include <asm/cpudata.h>
50 #include <asm/setup.h>
55 unsigned long kern_linear_pte_xor
[4] __read_mostly
;
57 /* A bitmap, two bits for every 256MB of physical memory. These two
58 * bits determine what page size we use for kernel linear
59 * translations. They form an index into kern_linear_pte_xor[]. The
60 * value in the indexed slot is XOR'd with the TLB miss virtual
61 * address to form the resulting TTE. The mapping is:
68 * All sun4v chips support 256MB pages. Only SPARC-T4 and later
69 * support 2GB pages, and hopefully future cpus will support the 16GB
70 * pages as well. For slots 2 and 3, we encode a 256MB TTE xor there
71 * if these larger page sizes are not supported by the cpu.
73 * It would be nice to determine this from the machine description
74 * 'cpu' properties, but we need to have this table setup before the
75 * MDESC is initialized.
77 unsigned long kpte_linear_bitmap
[KPTE_BITMAP_BYTES
/ sizeof(unsigned long)];
79 #ifndef CONFIG_DEBUG_PAGEALLOC
80 /* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings.
81 * Space is allocated for this right after the trap table in
82 * arch/sparc64/kernel/head.S
84 extern struct tsb swapper_4m_tsb
[KERNEL_TSB4M_NENTRIES
];
87 static unsigned long cpu_pgsz_mask
;
91 static struct linux_prom64_registers pavail
[MAX_BANKS
];
92 static int pavail_ents
;
94 static int cmp_p64(const void *a
, const void *b
)
96 const struct linux_prom64_registers
*x
= a
, *y
= b
;
98 if (x
->phys_addr
> y
->phys_addr
)
100 if (x
->phys_addr
< y
->phys_addr
)
105 static void __init
read_obp_memory(const char *property
,
106 struct linux_prom64_registers
*regs
,
109 phandle node
= prom_finddevice("/memory");
110 int prop_size
= prom_getproplen(node
, property
);
113 ents
= prop_size
/ sizeof(struct linux_prom64_registers
);
114 if (ents
> MAX_BANKS
) {
115 prom_printf("The machine has more %s property entries than "
116 "this kernel can support (%d).\n",
117 property
, MAX_BANKS
);
121 ret
= prom_getproperty(node
, property
, (char *) regs
, prop_size
);
123 prom_printf("Couldn't get %s property from /memory.\n",
128 /* Sanitize what we got from the firmware, by page aligning
131 for (i
= 0; i
< ents
; i
++) {
132 unsigned long base
, size
;
134 base
= regs
[i
].phys_addr
;
135 size
= regs
[i
].reg_size
;
138 if (base
& ~PAGE_MASK
) {
139 unsigned long new_base
= PAGE_ALIGN(base
);
141 size
-= new_base
- base
;
142 if ((long) size
< 0L)
147 /* If it is empty, simply get rid of it.
148 * This simplifies the logic of the other
149 * functions that process these arrays.
151 memmove(®s
[i
], ®s
[i
+ 1],
152 (ents
- i
- 1) * sizeof(regs
[0]));
157 regs
[i
].phys_addr
= base
;
158 regs
[i
].reg_size
= size
;
163 sort(regs
, ents
, sizeof(struct linux_prom64_registers
),
167 unsigned long sparc64_valid_addr_bitmap
[VALID_ADDR_BITMAP_BYTES
/
168 sizeof(unsigned long)];
169 EXPORT_SYMBOL(sparc64_valid_addr_bitmap
);
171 /* Kernel physical address base and size in bytes. */
172 unsigned long kern_base __read_mostly
;
173 unsigned long kern_size __read_mostly
;
175 /* Initial ramdisk setup */
176 extern unsigned long sparc_ramdisk_image64
;
177 extern unsigned int sparc_ramdisk_image
;
178 extern unsigned int sparc_ramdisk_size
;
180 struct page
*mem_map_zero __read_mostly
;
181 EXPORT_SYMBOL(mem_map_zero
);
183 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly
;
185 unsigned long sparc64_kern_pri_context __read_mostly
;
186 unsigned long sparc64_kern_pri_nuc_bits __read_mostly
;
187 unsigned long sparc64_kern_sec_context __read_mostly
;
189 int num_kernel_image_mappings
;
191 #ifdef CONFIG_DEBUG_DCFLUSH
192 atomic_t dcpage_flushes
= ATOMIC_INIT(0);
194 atomic_t dcpage_flushes_xcall
= ATOMIC_INIT(0);
198 inline void flush_dcache_page_impl(struct page
*page
)
200 BUG_ON(tlb_type
== hypervisor
);
201 #ifdef CONFIG_DEBUG_DCFLUSH
202 atomic_inc(&dcpage_flushes
);
205 #ifdef DCACHE_ALIASING_POSSIBLE
206 __flush_dcache_page(page_address(page
),
207 ((tlb_type
== spitfire
) &&
208 page_mapping(page
) != NULL
));
210 if (page_mapping(page
) != NULL
&&
211 tlb_type
== spitfire
)
212 __flush_icache_page(__pa(page_address(page
)));
216 #define PG_dcache_dirty PG_arch_1
217 #define PG_dcache_cpu_shift 32UL
218 #define PG_dcache_cpu_mask \
219 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
221 #define dcache_dirty_cpu(page) \
222 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
224 static inline void set_dcache_dirty(struct page
*page
, int this_cpu
)
226 unsigned long mask
= this_cpu
;
227 unsigned long non_cpu_bits
;
229 non_cpu_bits
= ~(PG_dcache_cpu_mask
<< PG_dcache_cpu_shift
);
230 mask
= (mask
<< PG_dcache_cpu_shift
) | (1UL << PG_dcache_dirty
);
232 __asm__
__volatile__("1:\n\t"
234 "and %%g7, %1, %%g1\n\t"
235 "or %%g1, %0, %%g1\n\t"
236 "casx [%2], %%g7, %%g1\n\t"
238 "bne,pn %%xcc, 1b\n\t"
241 : "r" (mask
), "r" (non_cpu_bits
), "r" (&page
->flags
)
245 static inline void clear_dcache_dirty_cpu(struct page
*page
, unsigned long cpu
)
247 unsigned long mask
= (1UL << PG_dcache_dirty
);
249 __asm__
__volatile__("! test_and_clear_dcache_dirty\n"
252 "srlx %%g7, %4, %%g1\n\t"
253 "and %%g1, %3, %%g1\n\t"
255 "bne,pn %%icc, 2f\n\t"
256 " andn %%g7, %1, %%g1\n\t"
257 "casx [%2], %%g7, %%g1\n\t"
259 "bne,pn %%xcc, 1b\n\t"
263 : "r" (cpu
), "r" (mask
), "r" (&page
->flags
),
264 "i" (PG_dcache_cpu_mask
),
265 "i" (PG_dcache_cpu_shift
)
269 static inline void tsb_insert(struct tsb
*ent
, unsigned long tag
, unsigned long pte
)
271 unsigned long tsb_addr
= (unsigned long) ent
;
273 if (tlb_type
== cheetah_plus
|| tlb_type
== hypervisor
)
274 tsb_addr
= __pa(tsb_addr
);
276 __tsb_insert(tsb_addr
, tag
, pte
);
279 unsigned long _PAGE_ALL_SZ_BITS __read_mostly
;
281 static void flush_dcache(unsigned long pfn
)
285 page
= pfn_to_page(pfn
);
287 unsigned long pg_flags
;
289 pg_flags
= page
->flags
;
290 if (pg_flags
& (1UL << PG_dcache_dirty
)) {
291 int cpu
= ((pg_flags
>> PG_dcache_cpu_shift
) &
293 int this_cpu
= get_cpu();
295 /* This is just to optimize away some function calls
299 flush_dcache_page_impl(page
);
301 smp_flush_dcache_page_impl(page
, cpu
);
303 clear_dcache_dirty_cpu(page
, cpu
);
310 /* mm->context.lock must be held */
311 static void __update_mmu_tsb_insert(struct mm_struct
*mm
, unsigned long tsb_index
,
312 unsigned long tsb_hash_shift
, unsigned long address
,
315 struct tsb
*tsb
= mm
->context
.tsb_block
[tsb_index
].tsb
;
321 tsb
+= ((address
>> tsb_hash_shift
) &
322 (mm
->context
.tsb_block
[tsb_index
].tsb_nentries
- 1UL));
323 tag
= (address
>> 22UL);
324 tsb_insert(tsb
, tag
, tte
);
327 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
328 static inline bool is_hugetlb_pte(pte_t pte
)
330 if ((tlb_type
== hypervisor
&&
331 (pte_val(pte
) & _PAGE_SZALL_4V
) == _PAGE_SZHUGE_4V
) ||
332 (tlb_type
!= hypervisor
&&
333 (pte_val(pte
) & _PAGE_SZALL_4U
) == _PAGE_SZHUGE_4U
))
339 void update_mmu_cache(struct vm_area_struct
*vma
, unsigned long address
, pte_t
*ptep
)
341 struct mm_struct
*mm
;
345 if (tlb_type
!= hypervisor
) {
346 unsigned long pfn
= pte_pfn(pte
);
354 spin_lock_irqsave(&mm
->context
.lock
, flags
);
356 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
357 if (mm
->context
.huge_pte_count
&& is_hugetlb_pte(pte
))
358 __update_mmu_tsb_insert(mm
, MM_TSB_HUGE
, REAL_HPAGE_SHIFT
,
359 address
, pte_val(pte
));
362 __update_mmu_tsb_insert(mm
, MM_TSB_BASE
, PAGE_SHIFT
,
363 address
, pte_val(pte
));
365 spin_unlock_irqrestore(&mm
->context
.lock
, flags
);
368 void flush_dcache_page(struct page
*page
)
370 struct address_space
*mapping
;
373 if (tlb_type
== hypervisor
)
376 /* Do not bother with the expensive D-cache flush if it
377 * is merely the zero page. The 'bigcore' testcase in GDB
378 * causes this case to run millions of times.
380 if (page
== ZERO_PAGE(0))
383 this_cpu
= get_cpu();
385 mapping
= page_mapping(page
);
386 if (mapping
&& !mapping_mapped(mapping
)) {
387 int dirty
= test_bit(PG_dcache_dirty
, &page
->flags
);
389 int dirty_cpu
= dcache_dirty_cpu(page
);
391 if (dirty_cpu
== this_cpu
)
393 smp_flush_dcache_page_impl(page
, dirty_cpu
);
395 set_dcache_dirty(page
, this_cpu
);
397 /* We could delay the flush for the !page_mapping
398 * case too. But that case is for exec env/arg
399 * pages and those are %99 certainly going to get
400 * faulted into the tlb (and thus flushed) anyways.
402 flush_dcache_page_impl(page
);
408 EXPORT_SYMBOL(flush_dcache_page
);
410 void __kprobes
flush_icache_range(unsigned long start
, unsigned long end
)
412 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
413 if (tlb_type
== spitfire
) {
416 /* This code only runs on Spitfire cpus so this is
417 * why we can assume _PAGE_PADDR_4U.
419 for (kaddr
= start
; kaddr
< end
; kaddr
+= PAGE_SIZE
) {
420 unsigned long paddr
, mask
= _PAGE_PADDR_4U
;
422 if (kaddr
>= PAGE_OFFSET
)
423 paddr
= kaddr
& mask
;
425 pgd_t
*pgdp
= pgd_offset_k(kaddr
);
426 pud_t
*pudp
= pud_offset(pgdp
, kaddr
);
427 pmd_t
*pmdp
= pmd_offset(pudp
, kaddr
);
428 pte_t
*ptep
= pte_offset_kernel(pmdp
, kaddr
);
430 paddr
= pte_val(*ptep
) & mask
;
432 __flush_icache_page(paddr
);
436 EXPORT_SYMBOL(flush_icache_range
);
438 void mmu_info(struct seq_file
*m
)
440 static const char *pgsz_strings
[] = {
441 "8K", "64K", "512K", "4MB", "32MB",
442 "256MB", "2GB", "16GB",
446 if (tlb_type
== cheetah
)
447 seq_printf(m
, "MMU Type\t: Cheetah\n");
448 else if (tlb_type
== cheetah_plus
)
449 seq_printf(m
, "MMU Type\t: Cheetah+\n");
450 else if (tlb_type
== spitfire
)
451 seq_printf(m
, "MMU Type\t: Spitfire\n");
452 else if (tlb_type
== hypervisor
)
453 seq_printf(m
, "MMU Type\t: Hypervisor (sun4v)\n");
455 seq_printf(m
, "MMU Type\t: ???\n");
457 seq_printf(m
, "MMU PGSZs\t: ");
459 for (i
= 0; i
< ARRAY_SIZE(pgsz_strings
); i
++) {
460 if (cpu_pgsz_mask
& (1UL << i
)) {
461 seq_printf(m
, "%s%s",
462 printed
? "," : "", pgsz_strings
[i
]);
468 #ifdef CONFIG_DEBUG_DCFLUSH
469 seq_printf(m
, "DCPageFlushes\t: %d\n",
470 atomic_read(&dcpage_flushes
));
472 seq_printf(m
, "DCPageFlushesXC\t: %d\n",
473 atomic_read(&dcpage_flushes_xcall
));
474 #endif /* CONFIG_SMP */
475 #endif /* CONFIG_DEBUG_DCFLUSH */
478 struct linux_prom_translation prom_trans
[512] __read_mostly
;
479 unsigned int prom_trans_ents __read_mostly
;
481 unsigned long kern_locked_tte_data
;
483 /* The obp translations are saved based on 8k pagesize, since obp can
484 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
485 * HI_OBP_ADDRESS range are handled in ktlb.S.
487 static inline int in_obp_range(unsigned long vaddr
)
489 return (vaddr
>= LOW_OBP_ADDRESS
&&
490 vaddr
< HI_OBP_ADDRESS
);
493 static int cmp_ptrans(const void *a
, const void *b
)
495 const struct linux_prom_translation
*x
= a
, *y
= b
;
497 if (x
->virt
> y
->virt
)
499 if (x
->virt
< y
->virt
)
504 /* Read OBP translations property into 'prom_trans[]'. */
505 static void __init
read_obp_translations(void)
507 int n
, node
, ents
, first
, last
, i
;
509 node
= prom_finddevice("/virtual-memory");
510 n
= prom_getproplen(node
, "translations");
511 if (unlikely(n
== 0 || n
== -1)) {
512 prom_printf("prom_mappings: Couldn't get size.\n");
515 if (unlikely(n
> sizeof(prom_trans
))) {
516 prom_printf("prom_mappings: Size %d is too big.\n", n
);
520 if ((n
= prom_getproperty(node
, "translations",
521 (char *)&prom_trans
[0],
522 sizeof(prom_trans
))) == -1) {
523 prom_printf("prom_mappings: Couldn't get property.\n");
527 n
= n
/ sizeof(struct linux_prom_translation
);
531 sort(prom_trans
, ents
, sizeof(struct linux_prom_translation
),
534 /* Now kick out all the non-OBP entries. */
535 for (i
= 0; i
< ents
; i
++) {
536 if (in_obp_range(prom_trans
[i
].virt
))
540 for (; i
< ents
; i
++) {
541 if (!in_obp_range(prom_trans
[i
].virt
))
546 for (i
= 0; i
< (last
- first
); i
++) {
547 struct linux_prom_translation
*src
= &prom_trans
[i
+ first
];
548 struct linux_prom_translation
*dest
= &prom_trans
[i
];
552 for (; i
< ents
; i
++) {
553 struct linux_prom_translation
*dest
= &prom_trans
[i
];
554 dest
->virt
= dest
->size
= dest
->data
= 0x0UL
;
557 prom_trans_ents
= last
- first
;
559 if (tlb_type
== spitfire
) {
560 /* Clear diag TTE bits. */
561 for (i
= 0; i
< prom_trans_ents
; i
++)
562 prom_trans
[i
].data
&= ~0x0003fe0000000000UL
;
565 /* Force execute bit on. */
566 for (i
= 0; i
< prom_trans_ents
; i
++)
567 prom_trans
[i
].data
|= (tlb_type
== hypervisor
?
568 _PAGE_EXEC_4V
: _PAGE_EXEC_4U
);
571 static void __init
hypervisor_tlb_lock(unsigned long vaddr
,
575 unsigned long ret
= sun4v_mmu_map_perm_addr(vaddr
, 0, pte
, mmu
);
578 prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: "
579 "errors with %lx\n", vaddr
, 0, pte
, mmu
, ret
);
584 static unsigned long kern_large_tte(unsigned long paddr
);
586 static void __init
remap_kernel(void)
588 unsigned long phys_page
, tte_vaddr
, tte_data
;
589 int i
, tlb_ent
= sparc64_highest_locked_tlbent();
591 tte_vaddr
= (unsigned long) KERNBASE
;
592 phys_page
= (prom_boot_mapping_phys_low
>> ILOG2_4MB
) << ILOG2_4MB
;
593 tte_data
= kern_large_tte(phys_page
);
595 kern_locked_tte_data
= tte_data
;
597 /* Now lock us into the TLBs via Hypervisor or OBP. */
598 if (tlb_type
== hypervisor
) {
599 for (i
= 0; i
< num_kernel_image_mappings
; i
++) {
600 hypervisor_tlb_lock(tte_vaddr
, tte_data
, HV_MMU_DMMU
);
601 hypervisor_tlb_lock(tte_vaddr
, tte_data
, HV_MMU_IMMU
);
602 tte_vaddr
+= 0x400000;
603 tte_data
+= 0x400000;
606 for (i
= 0; i
< num_kernel_image_mappings
; i
++) {
607 prom_dtlb_load(tlb_ent
- i
, tte_data
, tte_vaddr
);
608 prom_itlb_load(tlb_ent
- i
, tte_data
, tte_vaddr
);
609 tte_vaddr
+= 0x400000;
610 tte_data
+= 0x400000;
612 sparc64_highest_unlocked_tlb_ent
= tlb_ent
- i
;
614 if (tlb_type
== cheetah_plus
) {
615 sparc64_kern_pri_context
= (CTX_CHEETAH_PLUS_CTX0
|
616 CTX_CHEETAH_PLUS_NUC
);
617 sparc64_kern_pri_nuc_bits
= CTX_CHEETAH_PLUS_NUC
;
618 sparc64_kern_sec_context
= CTX_CHEETAH_PLUS_CTX0
;
623 static void __init
inherit_prom_mappings(void)
625 /* Now fixup OBP's idea about where we really are mapped. */
626 printk("Remapping the kernel... ");
631 void prom_world(int enter
)
636 __asm__
__volatile__("flushw");
639 void __flush_dcache_range(unsigned long start
, unsigned long end
)
643 if (tlb_type
== spitfire
) {
646 for (va
= start
; va
< end
; va
+= 32) {
647 spitfire_put_dcache_tag(va
& 0x3fe0, 0x0);
651 } else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
654 for (va
= start
; va
< end
; va
+= 32)
655 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
659 "i" (ASI_DCACHE_INVALIDATE
));
662 EXPORT_SYMBOL(__flush_dcache_range
);
664 /* get_new_mmu_context() uses "cache + 1". */
665 DEFINE_SPINLOCK(ctx_alloc_lock
);
666 unsigned long tlb_context_cache
= CTX_FIRST_VERSION
- 1;
667 #define MAX_CTX_NR (1UL << CTX_NR_BITS)
668 #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
669 DECLARE_BITMAP(mmu_context_bmap
, MAX_CTX_NR
);
671 /* Caller does TLB context flushing on local CPU if necessary.
672 * The caller also ensures that CTX_VALID(mm->context) is false.
674 * We must be careful about boundary cases so that we never
675 * let the user have CTX 0 (nucleus) or we ever use a CTX
676 * version of zero (and thus NO_CONTEXT would not be caught
677 * by version mis-match tests in mmu_context.h).
679 * Always invoked with interrupts disabled.
681 void get_new_mmu_context(struct mm_struct
*mm
)
683 unsigned long ctx
, new_ctx
;
684 unsigned long orig_pgsz_bits
;
687 spin_lock(&ctx_alloc_lock
);
688 orig_pgsz_bits
= (mm
->context
.sparc64_ctx_val
& CTX_PGSZ_MASK
);
689 ctx
= (tlb_context_cache
+ 1) & CTX_NR_MASK
;
690 new_ctx
= find_next_zero_bit(mmu_context_bmap
, 1 << CTX_NR_BITS
, ctx
);
692 if (new_ctx
>= (1 << CTX_NR_BITS
)) {
693 new_ctx
= find_next_zero_bit(mmu_context_bmap
, ctx
, 1);
694 if (new_ctx
>= ctx
) {
696 new_ctx
= (tlb_context_cache
& CTX_VERSION_MASK
) +
699 new_ctx
= CTX_FIRST_VERSION
;
701 /* Don't call memset, for 16 entries that's just
704 mmu_context_bmap
[0] = 3;
705 mmu_context_bmap
[1] = 0;
706 mmu_context_bmap
[2] = 0;
707 mmu_context_bmap
[3] = 0;
708 for (i
= 4; i
< CTX_BMAP_SLOTS
; i
+= 4) {
709 mmu_context_bmap
[i
+ 0] = 0;
710 mmu_context_bmap
[i
+ 1] = 0;
711 mmu_context_bmap
[i
+ 2] = 0;
712 mmu_context_bmap
[i
+ 3] = 0;
718 mmu_context_bmap
[new_ctx
>>6] |= (1UL << (new_ctx
& 63));
719 new_ctx
|= (tlb_context_cache
& CTX_VERSION_MASK
);
721 tlb_context_cache
= new_ctx
;
722 mm
->context
.sparc64_ctx_val
= new_ctx
| orig_pgsz_bits
;
723 spin_unlock(&ctx_alloc_lock
);
725 if (unlikely(new_version
))
726 smp_new_mmu_context_version();
729 static int numa_enabled
= 1;
730 static int numa_debug
;
732 static int __init
early_numa(char *p
)
737 if (strstr(p
, "off"))
740 if (strstr(p
, "debug"))
745 early_param("numa", early_numa
);
747 #define numadbg(f, a...) \
748 do { if (numa_debug) \
749 printk(KERN_INFO f, ## a); \
752 static void __init
find_ramdisk(unsigned long phys_base
)
754 #ifdef CONFIG_BLK_DEV_INITRD
755 if (sparc_ramdisk_image
|| sparc_ramdisk_image64
) {
756 unsigned long ramdisk_image
;
758 /* Older versions of the bootloader only supported a
759 * 32-bit physical address for the ramdisk image
760 * location, stored at sparc_ramdisk_image. Newer
761 * SILO versions set sparc_ramdisk_image to zero and
762 * provide a full 64-bit physical address at
763 * sparc_ramdisk_image64.
765 ramdisk_image
= sparc_ramdisk_image
;
767 ramdisk_image
= sparc_ramdisk_image64
;
769 /* Another bootloader quirk. The bootloader normalizes
770 * the physical address to KERNBASE, so we have to
771 * factor that back out and add in the lowest valid
772 * physical page address to get the true physical address.
774 ramdisk_image
-= KERNBASE
;
775 ramdisk_image
+= phys_base
;
777 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
778 ramdisk_image
, sparc_ramdisk_size
);
780 initrd_start
= ramdisk_image
;
781 initrd_end
= ramdisk_image
+ sparc_ramdisk_size
;
783 memblock_reserve(initrd_start
, sparc_ramdisk_size
);
785 initrd_start
+= PAGE_OFFSET
;
786 initrd_end
+= PAGE_OFFSET
;
791 struct node_mem_mask
{
795 static struct node_mem_mask node_masks
[MAX_NUMNODES
];
796 static int num_node_masks
;
798 #ifdef CONFIG_NEED_MULTIPLE_NODES
800 int numa_cpu_lookup_table
[NR_CPUS
];
801 cpumask_t numa_cpumask_lookup_table
[MAX_NUMNODES
];
803 struct mdesc_mblock
{
806 u64 offset
; /* RA-to-PA */
808 static struct mdesc_mblock
*mblocks
;
809 static int num_mblocks
;
811 static unsigned long ra_to_pa(unsigned long addr
)
815 for (i
= 0; i
< num_mblocks
; i
++) {
816 struct mdesc_mblock
*m
= &mblocks
[i
];
818 if (addr
>= m
->base
&&
819 addr
< (m
->base
+ m
->size
)) {
827 static int find_node(unsigned long addr
)
831 addr
= ra_to_pa(addr
);
832 for (i
= 0; i
< num_node_masks
; i
++) {
833 struct node_mem_mask
*p
= &node_masks
[i
];
835 if ((addr
& p
->mask
) == p
->val
)
841 static u64
memblock_nid_range(u64 start
, u64 end
, int *nid
)
843 *nid
= find_node(start
);
845 while (start
< end
) {
846 int n
= find_node(start
);
860 /* This must be invoked after performing all of the necessary
861 * memblock_set_node() calls for 'nid'. We need to be able to get
862 * correct data from get_pfn_range_for_nid().
864 static void __init
allocate_node_data(int nid
)
866 struct pglist_data
*p
;
867 unsigned long start_pfn
, end_pfn
;
868 #ifdef CONFIG_NEED_MULTIPLE_NODES
871 paddr
= memblock_alloc_try_nid(sizeof(struct pglist_data
), SMP_CACHE_BYTES
, nid
);
873 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid
);
876 NODE_DATA(nid
) = __va(paddr
);
877 memset(NODE_DATA(nid
), 0, sizeof(struct pglist_data
));
879 NODE_DATA(nid
)->node_id
= nid
;
884 get_pfn_range_for_nid(nid
, &start_pfn
, &end_pfn
);
885 p
->node_start_pfn
= start_pfn
;
886 p
->node_spanned_pages
= end_pfn
- start_pfn
;
889 static void init_node_masks_nonnuma(void)
891 #ifdef CONFIG_NEED_MULTIPLE_NODES
895 numadbg("Initializing tables for non-numa.\n");
897 node_masks
[0].mask
= node_masks
[0].val
= 0;
900 #ifdef CONFIG_NEED_MULTIPLE_NODES
901 for (i
= 0; i
< NR_CPUS
; i
++)
902 numa_cpu_lookup_table
[i
] = 0;
904 cpumask_setall(&numa_cpumask_lookup_table
[0]);
908 #ifdef CONFIG_NEED_MULTIPLE_NODES
909 struct pglist_data
*node_data
[MAX_NUMNODES
];
911 EXPORT_SYMBOL(numa_cpu_lookup_table
);
912 EXPORT_SYMBOL(numa_cpumask_lookup_table
);
913 EXPORT_SYMBOL(node_data
);
915 struct mdesc_mlgroup
{
921 static struct mdesc_mlgroup
*mlgroups
;
922 static int num_mlgroups
;
924 static int scan_pio_for_cfg_handle(struct mdesc_handle
*md
, u64 pio
,
929 mdesc_for_each_arc(arc
, md
, pio
, MDESC_ARC_TYPE_FWD
) {
930 u64 target
= mdesc_arc_target(md
, arc
);
933 val
= mdesc_get_property(md
, target
,
935 if (val
&& *val
== cfg_handle
)
941 static int scan_arcs_for_cfg_handle(struct mdesc_handle
*md
, u64 grp
,
944 u64 arc
, candidate
, best_latency
= ~(u64
)0;
946 candidate
= MDESC_NODE_NULL
;
947 mdesc_for_each_arc(arc
, md
, grp
, MDESC_ARC_TYPE_FWD
) {
948 u64 target
= mdesc_arc_target(md
, arc
);
949 const char *name
= mdesc_node_name(md
, target
);
952 if (strcmp(name
, "pio-latency-group"))
955 val
= mdesc_get_property(md
, target
, "latency", NULL
);
959 if (*val
< best_latency
) {
965 if (candidate
== MDESC_NODE_NULL
)
968 return scan_pio_for_cfg_handle(md
, candidate
, cfg_handle
);
971 int of_node_to_nid(struct device_node
*dp
)
973 const struct linux_prom64_registers
*regs
;
974 struct mdesc_handle
*md
;
979 /* This is the right thing to do on currently supported
980 * SUN4U NUMA platforms as well, as the PCI controller does
981 * not sit behind any particular memory controller.
986 regs
= of_get_property(dp
, "reg", NULL
);
990 cfg_handle
= (regs
->phys_addr
>> 32UL) & 0x0fffffff;
996 mdesc_for_each_node_by_name(md
, grp
, "group") {
997 if (!scan_arcs_for_cfg_handle(md
, grp
, cfg_handle
)) {
1009 static void __init
add_node_ranges(void)
1011 struct memblock_region
*reg
;
1013 for_each_memblock(memory
, reg
) {
1014 unsigned long size
= reg
->size
;
1015 unsigned long start
, end
;
1019 while (start
< end
) {
1020 unsigned long this_end
;
1023 this_end
= memblock_nid_range(start
, end
, &nid
);
1025 numadbg("Setting memblock NUMA node nid[%d] "
1026 "start[%lx] end[%lx]\n",
1027 nid
, start
, this_end
);
1029 memblock_set_node(start
, this_end
- start
,
1030 &memblock
.memory
, nid
);
1036 static int __init
grab_mlgroups(struct mdesc_handle
*md
)
1038 unsigned long paddr
;
1042 mdesc_for_each_node_by_name(md
, node
, "memory-latency-group")
1047 paddr
= memblock_alloc(count
* sizeof(struct mdesc_mlgroup
),
1052 mlgroups
= __va(paddr
);
1053 num_mlgroups
= count
;
1056 mdesc_for_each_node_by_name(md
, node
, "memory-latency-group") {
1057 struct mdesc_mlgroup
*m
= &mlgroups
[count
++];
1062 val
= mdesc_get_property(md
, node
, "latency", NULL
);
1064 val
= mdesc_get_property(md
, node
, "address-match", NULL
);
1066 val
= mdesc_get_property(md
, node
, "address-mask", NULL
);
1069 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
1070 "match[%llx] mask[%llx]\n",
1071 count
- 1, m
->node
, m
->latency
, m
->match
, m
->mask
);
1077 static int __init
grab_mblocks(struct mdesc_handle
*md
)
1079 unsigned long paddr
;
1083 mdesc_for_each_node_by_name(md
, node
, "mblock")
1088 paddr
= memblock_alloc(count
* sizeof(struct mdesc_mblock
),
1093 mblocks
= __va(paddr
);
1094 num_mblocks
= count
;
1097 mdesc_for_each_node_by_name(md
, node
, "mblock") {
1098 struct mdesc_mblock
*m
= &mblocks
[count
++];
1101 val
= mdesc_get_property(md
, node
, "base", NULL
);
1103 val
= mdesc_get_property(md
, node
, "size", NULL
);
1105 val
= mdesc_get_property(md
, node
,
1106 "address-congruence-offset", NULL
);
1108 /* The address-congruence-offset property is optional.
1109 * Explicity zero it be identifty this.
1116 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
1117 count
- 1, m
->base
, m
->size
, m
->offset
);
1123 static void __init
numa_parse_mdesc_group_cpus(struct mdesc_handle
*md
,
1124 u64 grp
, cpumask_t
*mask
)
1128 cpumask_clear(mask
);
1130 mdesc_for_each_arc(arc
, md
, grp
, MDESC_ARC_TYPE_BACK
) {
1131 u64 target
= mdesc_arc_target(md
, arc
);
1132 const char *name
= mdesc_node_name(md
, target
);
1135 if (strcmp(name
, "cpu"))
1137 id
= mdesc_get_property(md
, target
, "id", NULL
);
1138 if (*id
< nr_cpu_ids
)
1139 cpumask_set_cpu(*id
, mask
);
1143 static struct mdesc_mlgroup
* __init
find_mlgroup(u64 node
)
1147 for (i
= 0; i
< num_mlgroups
; i
++) {
1148 struct mdesc_mlgroup
*m
= &mlgroups
[i
];
1149 if (m
->node
== node
)
1155 static int __init
numa_attach_mlgroup(struct mdesc_handle
*md
, u64 grp
,
1158 struct mdesc_mlgroup
*candidate
= NULL
;
1159 u64 arc
, best_latency
= ~(u64
)0;
1160 struct node_mem_mask
*n
;
1162 mdesc_for_each_arc(arc
, md
, grp
, MDESC_ARC_TYPE_FWD
) {
1163 u64 target
= mdesc_arc_target(md
, arc
);
1164 struct mdesc_mlgroup
*m
= find_mlgroup(target
);
1167 if (m
->latency
< best_latency
) {
1169 best_latency
= m
->latency
;
1175 if (num_node_masks
!= index
) {
1176 printk(KERN_ERR
"Inconsistent NUMA state, "
1177 "index[%d] != num_node_masks[%d]\n",
1178 index
, num_node_masks
);
1182 n
= &node_masks
[num_node_masks
++];
1184 n
->mask
= candidate
->mask
;
1185 n
->val
= candidate
->match
;
1187 numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%llx])\n",
1188 index
, n
->mask
, n
->val
, candidate
->latency
);
1193 static int __init
numa_parse_mdesc_group(struct mdesc_handle
*md
, u64 grp
,
1199 numa_parse_mdesc_group_cpus(md
, grp
, &mask
);
1201 for_each_cpu(cpu
, &mask
)
1202 numa_cpu_lookup_table
[cpu
] = index
;
1203 cpumask_copy(&numa_cpumask_lookup_table
[index
], &mask
);
1206 printk(KERN_INFO
"NUMA GROUP[%d]: cpus [ ", index
);
1207 for_each_cpu(cpu
, &mask
)
1212 return numa_attach_mlgroup(md
, grp
, index
);
1215 static int __init
numa_parse_mdesc(void)
1217 struct mdesc_handle
*md
= mdesc_grab();
1221 node
= mdesc_node_by_name(md
, MDESC_NODE_NULL
, "latency-groups");
1222 if (node
== MDESC_NODE_NULL
) {
1227 err
= grab_mblocks(md
);
1231 err
= grab_mlgroups(md
);
1236 mdesc_for_each_node_by_name(md
, node
, "group") {
1237 err
= numa_parse_mdesc_group(md
, node
, count
);
1245 for (i
= 0; i
< num_node_masks
; i
++) {
1246 allocate_node_data(i
);
1256 static int __init
numa_parse_jbus(void)
1258 unsigned long cpu
, index
;
1260 /* NUMA node id is encoded in bits 36 and higher, and there is
1261 * a 1-to-1 mapping from CPU ID to NUMA node ID.
1264 for_each_present_cpu(cpu
) {
1265 numa_cpu_lookup_table
[cpu
] = index
;
1266 cpumask_copy(&numa_cpumask_lookup_table
[index
], cpumask_of(cpu
));
1267 node_masks
[index
].mask
= ~((1UL << 36UL) - 1UL);
1268 node_masks
[index
].val
= cpu
<< 36UL;
1272 num_node_masks
= index
;
1276 for (index
= 0; index
< num_node_masks
; index
++) {
1277 allocate_node_data(index
);
1278 node_set_online(index
);
1284 static int __init
numa_parse_sun4u(void)
1286 if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
1289 __asm__ ("rdpr %%ver, %0" : "=r" (ver
));
1290 if ((ver
>> 32UL) == __JALAPENO_ID
||
1291 (ver
>> 32UL) == __SERRANO_ID
)
1292 return numa_parse_jbus();
1297 static int __init
bootmem_init_numa(void)
1301 numadbg("bootmem_init_numa()\n");
1304 if (tlb_type
== hypervisor
)
1305 err
= numa_parse_mdesc();
1307 err
= numa_parse_sun4u();
1314 static int bootmem_init_numa(void)
1321 static void __init
bootmem_init_nonnuma(void)
1323 unsigned long top_of_ram
= memblock_end_of_DRAM();
1324 unsigned long total_ram
= memblock_phys_mem_size();
1326 numadbg("bootmem_init_nonnuma()\n");
1328 printk(KERN_INFO
"Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1329 top_of_ram
, total_ram
);
1330 printk(KERN_INFO
"Memory hole size: %ldMB\n",
1331 (top_of_ram
- total_ram
) >> 20);
1333 init_node_masks_nonnuma();
1334 memblock_set_node(0, (phys_addr_t
)ULLONG_MAX
, &memblock
.memory
, 0);
1335 allocate_node_data(0);
1339 static unsigned long __init
bootmem_init(unsigned long phys_base
)
1341 unsigned long end_pfn
;
1343 end_pfn
= memblock_end_of_DRAM() >> PAGE_SHIFT
;
1344 max_pfn
= max_low_pfn
= end_pfn
;
1345 min_low_pfn
= (phys_base
>> PAGE_SHIFT
);
1347 if (bootmem_init_numa() < 0)
1348 bootmem_init_nonnuma();
1350 /* Dump memblock with node info. */
1351 memblock_dump_all();
1353 /* XXX cpu notifier XXX */
1355 sparse_memory_present_with_active_regions(MAX_NUMNODES
);
1361 static struct linux_prom64_registers pall
[MAX_BANKS
] __initdata
;
1362 static int pall_ents __initdata
;
1364 #ifdef CONFIG_DEBUG_PAGEALLOC
1365 static unsigned long __ref
kernel_map_range(unsigned long pstart
,
1366 unsigned long pend
, pgprot_t prot
)
1368 unsigned long vstart
= PAGE_OFFSET
+ pstart
;
1369 unsigned long vend
= PAGE_OFFSET
+ pend
;
1370 unsigned long alloc_bytes
= 0UL;
1372 if ((vstart
& ~PAGE_MASK
) || (vend
& ~PAGE_MASK
)) {
1373 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1378 while (vstart
< vend
) {
1379 unsigned long this_end
, paddr
= __pa(vstart
);
1380 pgd_t
*pgd
= pgd_offset_k(vstart
);
1385 pud
= pud_offset(pgd
, vstart
);
1386 if (pud_none(*pud
)) {
1389 new = __alloc_bootmem(PAGE_SIZE
, PAGE_SIZE
, PAGE_SIZE
);
1390 alloc_bytes
+= PAGE_SIZE
;
1391 pud_populate(&init_mm
, pud
, new);
1394 pmd
= pmd_offset(pud
, vstart
);
1395 if (!pmd_present(*pmd
)) {
1398 new = __alloc_bootmem(PAGE_SIZE
, PAGE_SIZE
, PAGE_SIZE
);
1399 alloc_bytes
+= PAGE_SIZE
;
1400 pmd_populate_kernel(&init_mm
, pmd
, new);
1403 pte
= pte_offset_kernel(pmd
, vstart
);
1404 this_end
= (vstart
+ PMD_SIZE
) & PMD_MASK
;
1405 if (this_end
> vend
)
1408 while (vstart
< this_end
) {
1409 pte_val(*pte
) = (paddr
| pgprot_val(prot
));
1411 vstart
+= PAGE_SIZE
;
1420 extern unsigned int kvmap_linear_patch
[1];
1421 #endif /* CONFIG_DEBUG_PAGEALLOC */
1423 static void __init
kpte_set_val(unsigned long index
, unsigned long val
)
1425 unsigned long *ptr
= kpte_linear_bitmap
;
1427 val
<<= ((index
% (BITS_PER_LONG
/ 2)) * 2);
1428 ptr
+= (index
/ (BITS_PER_LONG
/ 2));
1433 static const unsigned long kpte_shift_min
= 28; /* 256MB */
1434 static const unsigned long kpte_shift_max
= 34; /* 16GB */
1435 static const unsigned long kpte_shift_incr
= 3;
1437 static unsigned long kpte_mark_using_shift(unsigned long start
, unsigned long end
,
1438 unsigned long shift
)
1440 unsigned long size
= (1UL << shift
);
1441 unsigned long mask
= (size
- 1UL);
1442 unsigned long remains
= end
- start
;
1445 if (remains
< size
|| (start
& mask
))
1450 * shift 28 --> kern_linear_pte_xor index 1
1451 * shift 31 --> kern_linear_pte_xor index 2
1452 * shift 34 --> kern_linear_pte_xor index 3
1454 val
= ((shift
- kpte_shift_min
) / kpte_shift_incr
) + 1;
1457 if (shift
!= kpte_shift_max
)
1461 unsigned long index
= start
>> kpte_shift_min
;
1463 kpte_set_val(index
, val
);
1465 start
+= 1UL << kpte_shift_min
;
1466 remains
-= 1UL << kpte_shift_min
;
1472 static void __init
mark_kpte_bitmap(unsigned long start
, unsigned long end
)
1474 unsigned long smallest_size
, smallest_mask
;
1477 smallest_size
= (1UL << kpte_shift_min
);
1478 smallest_mask
= (smallest_size
- 1UL);
1480 while (start
< end
) {
1481 unsigned long orig_start
= start
;
1483 for (s
= kpte_shift_max
; s
>= kpte_shift_min
; s
-= kpte_shift_incr
) {
1484 start
= kpte_mark_using_shift(start
, end
, s
);
1486 if (start
!= orig_start
)
1490 if (start
== orig_start
)
1491 start
= (start
+ smallest_size
) & ~smallest_mask
;
1495 static void __init
init_kpte_bitmap(void)
1499 for (i
= 0; i
< pall_ents
; i
++) {
1500 unsigned long phys_start
, phys_end
;
1502 phys_start
= pall
[i
].phys_addr
;
1503 phys_end
= phys_start
+ pall
[i
].reg_size
;
1505 mark_kpte_bitmap(phys_start
, phys_end
);
1509 static void __init
kernel_physical_mapping_init(void)
1511 #ifdef CONFIG_DEBUG_PAGEALLOC
1512 unsigned long i
, mem_alloced
= 0UL;
1514 for (i
= 0; i
< pall_ents
; i
++) {
1515 unsigned long phys_start
, phys_end
;
1517 phys_start
= pall
[i
].phys_addr
;
1518 phys_end
= phys_start
+ pall
[i
].reg_size
;
1520 mem_alloced
+= kernel_map_range(phys_start
, phys_end
,
1524 printk("Allocated %ld bytes for kernel page tables.\n",
1527 kvmap_linear_patch
[0] = 0x01000000; /* nop */
1528 flushi(&kvmap_linear_patch
[0]);
1534 #ifdef CONFIG_DEBUG_PAGEALLOC
1535 void kernel_map_pages(struct page
*page
, int numpages
, int enable
)
1537 unsigned long phys_start
= page_to_pfn(page
) << PAGE_SHIFT
;
1538 unsigned long phys_end
= phys_start
+ (numpages
* PAGE_SIZE
);
1540 kernel_map_range(phys_start
, phys_end
,
1541 (enable
? PAGE_KERNEL
: __pgprot(0)));
1543 flush_tsb_kernel_range(PAGE_OFFSET
+ phys_start
,
1544 PAGE_OFFSET
+ phys_end
);
1546 /* we should perform an IPI and flush all tlbs,
1547 * but that can deadlock->flush only current cpu.
1549 __flush_tlb_kernel_range(PAGE_OFFSET
+ phys_start
,
1550 PAGE_OFFSET
+ phys_end
);
1554 unsigned long __init
find_ecache_flush_span(unsigned long size
)
1558 for (i
= 0; i
< pavail_ents
; i
++) {
1559 if (pavail
[i
].reg_size
>= size
)
1560 return pavail
[i
].phys_addr
;
1566 unsigned long PAGE_OFFSET
;
1567 EXPORT_SYMBOL(PAGE_OFFSET
);
1569 static void __init
page_offset_shift_patch_one(unsigned int *insn
, unsigned long phys_bits
)
1571 unsigned long final_shift
;
1572 unsigned int val
= *insn
;
1575 /* We are patching in ilog2(max_supported_phys_address), and
1576 * we are doing so in a manner similar to a relocation addend.
1577 * That is, we are adding the shift value to whatever value
1578 * is in the shift instruction count field already.
1583 /* If we are trying to shift >= 64 bits, clear the destination
1584 * register. This can happen when phys_bits ends up being equal
1585 * to MAX_PHYS_ADDRESS_BITS.
1587 final_shift
= (cnt
+ (64 - phys_bits
));
1588 if (final_shift
>= 64) {
1589 unsigned int rd
= (val
>> 25) & 0x1f;
1591 val
= 0x80100000 | (rd
<< 25);
1597 __asm__
__volatile__("flush %0"
1602 static void __init
page_offset_shift_patch(unsigned long phys_bits
)
1604 extern unsigned int __page_offset_shift_patch
;
1605 extern unsigned int __page_offset_shift_patch_end
;
1608 p
= &__page_offset_shift_patch
;
1609 while (p
< &__page_offset_shift_patch_end
) {
1610 unsigned int *insn
= (unsigned int *)(unsigned long)*p
;
1612 page_offset_shift_patch_one(insn
, phys_bits
);
1618 static void __init
setup_page_offset(void)
1620 unsigned long max_phys_bits
= 40;
1622 if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
1624 } else if (tlb_type
== hypervisor
) {
1625 switch (sun4v_chip_type
) {
1626 case SUN4V_CHIP_NIAGARA1
:
1627 case SUN4V_CHIP_NIAGARA2
:
1630 case SUN4V_CHIP_NIAGARA3
:
1633 case SUN4V_CHIP_NIAGARA4
:
1634 case SUN4V_CHIP_NIAGARA5
:
1635 case SUN4V_CHIP_SPARC64X
:
1642 if (max_phys_bits
> MAX_PHYS_ADDRESS_BITS
) {
1643 prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n",
1648 PAGE_OFFSET
= PAGE_OFFSET_BY_BITS(max_phys_bits
);
1650 pr_info("PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n",
1651 PAGE_OFFSET
, max_phys_bits
);
1653 page_offset_shift_patch(max_phys_bits
);
1656 static void __init
tsb_phys_patch(void)
1658 struct tsb_ldquad_phys_patch_entry
*pquad
;
1659 struct tsb_phys_patch_entry
*p
;
1661 pquad
= &__tsb_ldquad_phys_patch
;
1662 while (pquad
< &__tsb_ldquad_phys_patch_end
) {
1663 unsigned long addr
= pquad
->addr
;
1665 if (tlb_type
== hypervisor
)
1666 *(unsigned int *) addr
= pquad
->sun4v_insn
;
1668 *(unsigned int *) addr
= pquad
->sun4u_insn
;
1670 __asm__
__volatile__("flush %0"
1677 p
= &__tsb_phys_patch
;
1678 while (p
< &__tsb_phys_patch_end
) {
1679 unsigned long addr
= p
->addr
;
1681 *(unsigned int *) addr
= p
->insn
;
1683 __asm__
__volatile__("flush %0"
1691 /* Don't mark as init, we give this to the Hypervisor. */
1692 #ifndef CONFIG_DEBUG_PAGEALLOC
1693 #define NUM_KTSB_DESCR 2
1695 #define NUM_KTSB_DESCR 1
1697 static struct hv_tsb_descr ktsb_descr
[NUM_KTSB_DESCR
];
1698 extern struct tsb swapper_tsb
[KERNEL_TSB_NENTRIES
];
1700 static void patch_one_ktsb_phys(unsigned int *start
, unsigned int *end
, unsigned long pa
)
1702 pa
>>= KTSB_PHYS_SHIFT
;
1704 while (start
< end
) {
1705 unsigned int *ia
= (unsigned int *)(unsigned long)*start
;
1707 ia
[0] = (ia
[0] & ~0x3fffff) | (pa
>> 10);
1708 __asm__
__volatile__("flush %0" : : "r" (ia
));
1710 ia
[1] = (ia
[1] & ~0x3ff) | (pa
& 0x3ff);
1711 __asm__
__volatile__("flush %0" : : "r" (ia
+ 1));
1717 static void ktsb_phys_patch(void)
1719 extern unsigned int __swapper_tsb_phys_patch
;
1720 extern unsigned int __swapper_tsb_phys_patch_end
;
1721 unsigned long ktsb_pa
;
1723 ktsb_pa
= kern_base
+ ((unsigned long)&swapper_tsb
[0] - KERNBASE
);
1724 patch_one_ktsb_phys(&__swapper_tsb_phys_patch
,
1725 &__swapper_tsb_phys_patch_end
, ktsb_pa
);
1726 #ifndef CONFIG_DEBUG_PAGEALLOC
1728 extern unsigned int __swapper_4m_tsb_phys_patch
;
1729 extern unsigned int __swapper_4m_tsb_phys_patch_end
;
1730 ktsb_pa
= (kern_base
+
1731 ((unsigned long)&swapper_4m_tsb
[0] - KERNBASE
));
1732 patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch
,
1733 &__swapper_4m_tsb_phys_patch_end
, ktsb_pa
);
1738 static void __init
sun4v_ktsb_init(void)
1740 unsigned long ktsb_pa
;
1742 /* First KTSB for PAGE_SIZE mappings. */
1743 ktsb_pa
= kern_base
+ ((unsigned long)&swapper_tsb
[0] - KERNBASE
);
1745 switch (PAGE_SIZE
) {
1748 ktsb_descr
[0].pgsz_idx
= HV_PGSZ_IDX_8K
;
1749 ktsb_descr
[0].pgsz_mask
= HV_PGSZ_MASK_8K
;
1753 ktsb_descr
[0].pgsz_idx
= HV_PGSZ_IDX_64K
;
1754 ktsb_descr
[0].pgsz_mask
= HV_PGSZ_MASK_64K
;
1758 ktsb_descr
[0].pgsz_idx
= HV_PGSZ_IDX_512K
;
1759 ktsb_descr
[0].pgsz_mask
= HV_PGSZ_MASK_512K
;
1762 case 4 * 1024 * 1024:
1763 ktsb_descr
[0].pgsz_idx
= HV_PGSZ_IDX_4MB
;
1764 ktsb_descr
[0].pgsz_mask
= HV_PGSZ_MASK_4MB
;
1768 ktsb_descr
[0].assoc
= 1;
1769 ktsb_descr
[0].num_ttes
= KERNEL_TSB_NENTRIES
;
1770 ktsb_descr
[0].ctx_idx
= 0;
1771 ktsb_descr
[0].tsb_base
= ktsb_pa
;
1772 ktsb_descr
[0].resv
= 0;
1774 #ifndef CONFIG_DEBUG_PAGEALLOC
1775 /* Second KTSB for 4MB/256MB/2GB/16GB mappings. */
1776 ktsb_pa
= (kern_base
+
1777 ((unsigned long)&swapper_4m_tsb
[0] - KERNBASE
));
1779 ktsb_descr
[1].pgsz_idx
= HV_PGSZ_IDX_4MB
;
1780 ktsb_descr
[1].pgsz_mask
= ((HV_PGSZ_MASK_4MB
|
1781 HV_PGSZ_MASK_256MB
|
1783 HV_PGSZ_MASK_16GB
) &
1785 ktsb_descr
[1].assoc
= 1;
1786 ktsb_descr
[1].num_ttes
= KERNEL_TSB4M_NENTRIES
;
1787 ktsb_descr
[1].ctx_idx
= 0;
1788 ktsb_descr
[1].tsb_base
= ktsb_pa
;
1789 ktsb_descr
[1].resv
= 0;
1793 void sun4v_ktsb_register(void)
1795 unsigned long pa
, ret
;
1797 pa
= kern_base
+ ((unsigned long)&ktsb_descr
[0] - KERNBASE
);
1799 ret
= sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR
, pa
);
1801 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1802 "errors with %lx\n", pa
, ret
);
1807 static void __init
sun4u_linear_pte_xor_finalize(void)
1809 #ifndef CONFIG_DEBUG_PAGEALLOC
1810 /* This is where we would add Panther support for
1811 * 32MB and 256MB pages.
1816 static void __init
sun4v_linear_pte_xor_finalize(void)
1818 #ifndef CONFIG_DEBUG_PAGEALLOC
1819 if (cpu_pgsz_mask
& HV_PGSZ_MASK_256MB
) {
1820 kern_linear_pte_xor
[1] = (_PAGE_VALID
| _PAGE_SZ256MB_4V
) ^
1822 kern_linear_pte_xor
[1] |= (_PAGE_CP_4V
| _PAGE_CV_4V
|
1823 _PAGE_P_4V
| _PAGE_W_4V
);
1825 kern_linear_pte_xor
[1] = kern_linear_pte_xor
[0];
1828 if (cpu_pgsz_mask
& HV_PGSZ_MASK_2GB
) {
1829 kern_linear_pte_xor
[2] = (_PAGE_VALID
| _PAGE_SZ2GB_4V
) ^
1831 kern_linear_pte_xor
[2] |= (_PAGE_CP_4V
| _PAGE_CV_4V
|
1832 _PAGE_P_4V
| _PAGE_W_4V
);
1834 kern_linear_pte_xor
[2] = kern_linear_pte_xor
[1];
1837 if (cpu_pgsz_mask
& HV_PGSZ_MASK_16GB
) {
1838 kern_linear_pte_xor
[3] = (_PAGE_VALID
| _PAGE_SZ16GB_4V
) ^
1840 kern_linear_pte_xor
[3] |= (_PAGE_CP_4V
| _PAGE_CV_4V
|
1841 _PAGE_P_4V
| _PAGE_W_4V
);
1843 kern_linear_pte_xor
[3] = kern_linear_pte_xor
[2];
1848 /* paging_init() sets up the page tables */
1850 static unsigned long last_valid_pfn
;
1851 pgd_t swapper_pg_dir
[PTRS_PER_PGD
];
1853 static void sun4u_pgprot_init(void);
1854 static void sun4v_pgprot_init(void);
1856 void __init
paging_init(void)
1858 unsigned long end_pfn
, shift
, phys_base
;
1859 unsigned long real_end
, i
;
1862 setup_page_offset();
1864 /* These build time checkes make sure that the dcache_dirty_cpu()
1865 * page->flags usage will work.
1867 * When a page gets marked as dcache-dirty, we store the
1868 * cpu number starting at bit 32 in the page->flags. Also,
1869 * functions like clear_dcache_dirty_cpu use the cpu mask
1870 * in 13-bit signed-immediate instruction fields.
1874 * Page flags must not reach into upper 32 bits that are used
1875 * for the cpu number
1877 BUILD_BUG_ON(NR_PAGEFLAGS
> 32);
1880 * The bit fields placed in the high range must not reach below
1881 * the 32 bit boundary. Otherwise we cannot place the cpu field
1882 * at the 32 bit boundary.
1884 BUILD_BUG_ON(SECTIONS_WIDTH
+ NODES_WIDTH
+ ZONES_WIDTH
+
1885 ilog2(roundup_pow_of_two(NR_CPUS
)) > 32);
1887 BUILD_BUG_ON(NR_CPUS
> 4096);
1889 kern_base
= (prom_boot_mapping_phys_low
>> ILOG2_4MB
) << ILOG2_4MB
;
1890 kern_size
= (unsigned long)&_end
- (unsigned long)KERNBASE
;
1892 /* Invalidate both kernel TSBs. */
1893 memset(swapper_tsb
, 0x40, sizeof(swapper_tsb
));
1894 #ifndef CONFIG_DEBUG_PAGEALLOC
1895 memset(swapper_4m_tsb
, 0x40, sizeof(swapper_4m_tsb
));
1898 if (tlb_type
== hypervisor
)
1899 sun4v_pgprot_init();
1901 sun4u_pgprot_init();
1903 if (tlb_type
== cheetah_plus
||
1904 tlb_type
== hypervisor
) {
1909 if (tlb_type
== hypervisor
)
1910 sun4v_patch_tlb_handlers();
1912 /* Find available physical memory...
1914 * Read it twice in order to work around a bug in openfirmware.
1915 * The call to grab this table itself can cause openfirmware to
1916 * allocate memory, which in turn can take away some space from
1917 * the list of available memory. Reading it twice makes sure
1918 * we really do get the final value.
1920 read_obp_translations();
1921 read_obp_memory("reg", &pall
[0], &pall_ents
);
1922 read_obp_memory("available", &pavail
[0], &pavail_ents
);
1923 read_obp_memory("available", &pavail
[0], &pavail_ents
);
1925 phys_base
= 0xffffffffffffffffUL
;
1926 for (i
= 0; i
< pavail_ents
; i
++) {
1927 phys_base
= min(phys_base
, pavail
[i
].phys_addr
);
1928 memblock_add(pavail
[i
].phys_addr
, pavail
[i
].reg_size
);
1931 memblock_reserve(kern_base
, kern_size
);
1933 find_ramdisk(phys_base
);
1935 memblock_enforce_memory_limit(cmdline_memory_size
);
1937 memblock_allow_resize();
1938 memblock_dump_all();
1940 set_bit(0, mmu_context_bmap
);
1942 shift
= kern_base
+ PAGE_OFFSET
- ((unsigned long)KERNBASE
);
1944 real_end
= (unsigned long)_end
;
1945 num_kernel_image_mappings
= DIV_ROUND_UP(real_end
- KERNBASE
, 1 << ILOG2_4MB
);
1946 printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
1947 num_kernel_image_mappings
);
1949 /* Set kernel pgd to upper alias so physical page computations
1952 init_mm
.pgd
+= ((shift
) / (sizeof(pgd_t
)));
1954 memset(swapper_low_pmd_dir
, 0, sizeof(swapper_low_pmd_dir
));
1956 /* Now can init the kernel/bad page tables. */
1957 pud_set(pud_offset(&swapper_pg_dir
[0], 0),
1958 swapper_low_pmd_dir
+ (shift
/ sizeof(pgd_t
)));
1960 inherit_prom_mappings();
1964 /* Ok, we can use our TLB miss and window trap handlers safely. */
1969 prom_build_devicetree();
1970 of_populate_present_mask();
1972 of_fill_in_cpu_data();
1975 if (tlb_type
== hypervisor
) {
1977 mdesc_populate_present_mask(cpu_all_mask
);
1979 mdesc_fill_in_cpu_data(cpu_all_mask
);
1981 mdesc_get_page_sizes(cpu_all_mask
, &cpu_pgsz_mask
);
1983 sun4v_linear_pte_xor_finalize();
1986 sun4v_ktsb_register();
1988 unsigned long impl
, ver
;
1990 cpu_pgsz_mask
= (HV_PGSZ_MASK_8K
| HV_PGSZ_MASK_64K
|
1991 HV_PGSZ_MASK_512K
| HV_PGSZ_MASK_4MB
);
1993 __asm__
__volatile__("rdpr %%ver, %0" : "=r" (ver
));
1994 impl
= ((ver
>> 32) & 0xffff);
1995 if (impl
== PANTHER_IMPL
)
1996 cpu_pgsz_mask
|= (HV_PGSZ_MASK_32MB
|
1997 HV_PGSZ_MASK_256MB
);
1999 sun4u_linear_pte_xor_finalize();
2002 /* Flush the TLBs and the 4M TSB so that the updated linear
2003 * pte XOR settings are realized for all mappings.
2006 #ifndef CONFIG_DEBUG_PAGEALLOC
2007 memset(swapper_4m_tsb
, 0x40, sizeof(swapper_4m_tsb
));
2011 /* Setup bootmem... */
2012 last_valid_pfn
= end_pfn
= bootmem_init(phys_base
);
2014 /* Once the OF device tree and MDESC have been setup, we know
2015 * the list of possible cpus. Therefore we can allocate the
2018 for_each_possible_cpu(i
) {
2019 node
= cpu_to_node(i
);
2021 softirq_stack
[i
] = __alloc_bootmem_node(NODE_DATA(node
),
2024 hardirq_stack
[i
] = __alloc_bootmem_node(NODE_DATA(node
),
2029 kernel_physical_mapping_init();
2032 unsigned long max_zone_pfns
[MAX_NR_ZONES
];
2034 memset(max_zone_pfns
, 0, sizeof(max_zone_pfns
));
2036 max_zone_pfns
[ZONE_NORMAL
] = end_pfn
;
2038 free_area_init_nodes(max_zone_pfns
);
2041 printk("Booting Linux...\n");
2044 int page_in_phys_avail(unsigned long paddr
)
2050 for (i
= 0; i
< pavail_ents
; i
++) {
2051 unsigned long start
, end
;
2053 start
= pavail
[i
].phys_addr
;
2054 end
= start
+ pavail
[i
].reg_size
;
2056 if (paddr
>= start
&& paddr
< end
)
2059 if (paddr
>= kern_base
&& paddr
< (kern_base
+ kern_size
))
2061 #ifdef CONFIG_BLK_DEV_INITRD
2062 if (paddr
>= __pa(initrd_start
) &&
2063 paddr
< __pa(PAGE_ALIGN(initrd_end
)))
2070 static struct linux_prom64_registers pavail_rescan
[MAX_BANKS
] __initdata
;
2071 static int pavail_rescan_ents __initdata
;
2073 /* Certain OBP calls, such as fetching "available" properties, can
2074 * claim physical memory. So, along with initializing the valid
2075 * address bitmap, what we do here is refetch the physical available
2076 * memory list again, and make sure it provides at least as much
2077 * memory as 'pavail' does.
2079 static void __init
setup_valid_addr_bitmap_from_pavail(unsigned long *bitmap
)
2083 read_obp_memory("available", &pavail_rescan
[0], &pavail_rescan_ents
);
2085 for (i
= 0; i
< pavail_ents
; i
++) {
2086 unsigned long old_start
, old_end
;
2088 old_start
= pavail
[i
].phys_addr
;
2089 old_end
= old_start
+ pavail
[i
].reg_size
;
2090 while (old_start
< old_end
) {
2093 for (n
= 0; n
< pavail_rescan_ents
; n
++) {
2094 unsigned long new_start
, new_end
;
2096 new_start
= pavail_rescan
[n
].phys_addr
;
2097 new_end
= new_start
+
2098 pavail_rescan
[n
].reg_size
;
2100 if (new_start
<= old_start
&&
2101 new_end
>= (old_start
+ PAGE_SIZE
)) {
2102 set_bit(old_start
>> ILOG2_4MB
, bitmap
);
2107 prom_printf("mem_init: Lost memory in pavail\n");
2108 prom_printf("mem_init: OLD start[%lx] size[%lx]\n",
2109 pavail
[i
].phys_addr
,
2110 pavail
[i
].reg_size
);
2111 prom_printf("mem_init: NEW start[%lx] size[%lx]\n",
2112 pavail_rescan
[i
].phys_addr
,
2113 pavail_rescan
[i
].reg_size
);
2114 prom_printf("mem_init: Cannot continue, aborting.\n");
2118 old_start
+= PAGE_SIZE
;
2123 static void __init
patch_tlb_miss_handler_bitmap(void)
2125 extern unsigned int valid_addr_bitmap_insn
[];
2126 extern unsigned int valid_addr_bitmap_patch
[];
2128 valid_addr_bitmap_insn
[1] = valid_addr_bitmap_patch
[1];
2130 valid_addr_bitmap_insn
[0] = valid_addr_bitmap_patch
[0];
2131 flushi(&valid_addr_bitmap_insn
[0]);
2134 static void __init
register_page_bootmem_info(void)
2136 #ifdef CONFIG_NEED_MULTIPLE_NODES
2139 for_each_online_node(i
)
2140 if (NODE_DATA(i
)->node_spanned_pages
)
2141 register_page_bootmem_info_node(NODE_DATA(i
));
2144 void __init
mem_init(void)
2146 unsigned long addr
, last
;
2148 addr
= PAGE_OFFSET
+ kern_base
;
2149 last
= PAGE_ALIGN(kern_size
) + addr
;
2150 while (addr
< last
) {
2151 set_bit(__pa(addr
) >> ILOG2_4MB
, sparc64_valid_addr_bitmap
);
2155 setup_valid_addr_bitmap_from_pavail(sparc64_valid_addr_bitmap
);
2156 patch_tlb_miss_handler_bitmap();
2158 high_memory
= __va(last_valid_pfn
<< PAGE_SHIFT
);
2160 register_page_bootmem_info();
2164 * Set up the zero page, mark it reserved, so that page count
2165 * is not manipulated when freeing the page from user ptes.
2167 mem_map_zero
= alloc_pages(GFP_KERNEL
|__GFP_ZERO
, 0);
2168 if (mem_map_zero
== NULL
) {
2169 prom_printf("paging_init: Cannot alloc zero page.\n");
2172 mark_page_reserved(mem_map_zero
);
2174 mem_init_print_info(NULL
);
2176 if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
)
2177 cheetah_ecache_flush_init();
2180 void free_initmem(void)
2182 unsigned long addr
, initend
;
2185 /* If the physical memory maps were trimmed by kernel command
2186 * line options, don't even try freeing this initmem stuff up.
2187 * The kernel image could have been in the trimmed out region
2188 * and if so the freeing below will free invalid page structs.
2190 if (cmdline_memory_size
)
2194 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2196 addr
= PAGE_ALIGN((unsigned long)(__init_begin
));
2197 initend
= (unsigned long)(__init_end
) & PAGE_MASK
;
2198 for (; addr
< initend
; addr
+= PAGE_SIZE
) {
2202 ((unsigned long) __va(kern_base
)) -
2203 ((unsigned long) KERNBASE
));
2204 memset((void *)addr
, POISON_FREE_INITMEM
, PAGE_SIZE
);
2207 free_reserved_page(virt_to_page(page
));
2211 #ifdef CONFIG_BLK_DEV_INITRD
2212 void free_initrd_mem(unsigned long start
, unsigned long end
)
2214 free_reserved_area((void *)start
, (void *)end
, POISON_FREE_INITMEM
,
2219 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
2220 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
2221 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2222 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2223 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2224 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2226 pgprot_t PAGE_KERNEL __read_mostly
;
2227 EXPORT_SYMBOL(PAGE_KERNEL
);
2229 pgprot_t PAGE_KERNEL_LOCKED __read_mostly
;
2230 pgprot_t PAGE_COPY __read_mostly
;
2232 pgprot_t PAGE_SHARED __read_mostly
;
2233 EXPORT_SYMBOL(PAGE_SHARED
);
2235 unsigned long pg_iobits __read_mostly
;
2237 unsigned long _PAGE_IE __read_mostly
;
2238 EXPORT_SYMBOL(_PAGE_IE
);
2240 unsigned long _PAGE_E __read_mostly
;
2241 EXPORT_SYMBOL(_PAGE_E
);
2243 unsigned long _PAGE_CACHE __read_mostly
;
2244 EXPORT_SYMBOL(_PAGE_CACHE
);
2246 #ifdef CONFIG_SPARSEMEM_VMEMMAP
2247 unsigned long vmemmap_table
[VMEMMAP_SIZE
];
2249 static long __meminitdata addr_start
, addr_end
;
2250 static int __meminitdata node_start
;
2252 int __meminit
vmemmap_populate(unsigned long vstart
, unsigned long vend
,
2255 unsigned long phys_start
= (vstart
- VMEMMAP_BASE
);
2256 unsigned long phys_end
= (vend
- VMEMMAP_BASE
);
2257 unsigned long addr
= phys_start
& VMEMMAP_CHUNK_MASK
;
2258 unsigned long end
= VMEMMAP_ALIGN(phys_end
);
2259 unsigned long pte_base
;
2261 pte_base
= (_PAGE_VALID
| _PAGE_SZ4MB_4U
|
2262 _PAGE_CP_4U
| _PAGE_CV_4U
|
2263 _PAGE_P_4U
| _PAGE_W_4U
);
2264 if (tlb_type
== hypervisor
)
2265 pte_base
= (_PAGE_VALID
| _PAGE_SZ4MB_4V
|
2266 _PAGE_CP_4V
| _PAGE_CV_4V
|
2267 _PAGE_P_4V
| _PAGE_W_4V
);
2269 for (; addr
< end
; addr
+= VMEMMAP_CHUNK
) {
2270 unsigned long *vmem_pp
=
2271 vmemmap_table
+ (addr
>> VMEMMAP_CHUNK_SHIFT
);
2274 if (!(*vmem_pp
& _PAGE_VALID
)) {
2275 block
= vmemmap_alloc_block(1UL << ILOG2_4MB
, node
);
2279 *vmem_pp
= pte_base
| __pa(block
);
2281 /* check to see if we have contiguous blocks */
2282 if (addr_end
!= addr
|| node_start
!= node
) {
2284 printk(KERN_DEBUG
" [%lx-%lx] on node %d\n",
2285 addr_start
, addr_end
-1, node_start
);
2289 addr_end
= addr
+ VMEMMAP_CHUNK
;
2295 void __meminit
vmemmap_populate_print_last(void)
2298 printk(KERN_DEBUG
" [%lx-%lx] on node %d\n",
2299 addr_start
, addr_end
-1, node_start
);
2306 void vmemmap_free(unsigned long start
, unsigned long end
)
2310 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
2312 static void prot_init_common(unsigned long page_none
,
2313 unsigned long page_shared
,
2314 unsigned long page_copy
,
2315 unsigned long page_readonly
,
2316 unsigned long page_exec_bit
)
2318 PAGE_COPY
= __pgprot(page_copy
);
2319 PAGE_SHARED
= __pgprot(page_shared
);
2321 protection_map
[0x0] = __pgprot(page_none
);
2322 protection_map
[0x1] = __pgprot(page_readonly
& ~page_exec_bit
);
2323 protection_map
[0x2] = __pgprot(page_copy
& ~page_exec_bit
);
2324 protection_map
[0x3] = __pgprot(page_copy
& ~page_exec_bit
);
2325 protection_map
[0x4] = __pgprot(page_readonly
);
2326 protection_map
[0x5] = __pgprot(page_readonly
);
2327 protection_map
[0x6] = __pgprot(page_copy
);
2328 protection_map
[0x7] = __pgprot(page_copy
);
2329 protection_map
[0x8] = __pgprot(page_none
);
2330 protection_map
[0x9] = __pgprot(page_readonly
& ~page_exec_bit
);
2331 protection_map
[0xa] = __pgprot(page_shared
& ~page_exec_bit
);
2332 protection_map
[0xb] = __pgprot(page_shared
& ~page_exec_bit
);
2333 protection_map
[0xc] = __pgprot(page_readonly
);
2334 protection_map
[0xd] = __pgprot(page_readonly
);
2335 protection_map
[0xe] = __pgprot(page_shared
);
2336 protection_map
[0xf] = __pgprot(page_shared
);
2339 static void __init
sun4u_pgprot_init(void)
2341 unsigned long page_none
, page_shared
, page_copy
, page_readonly
;
2342 unsigned long page_exec_bit
;
2345 PAGE_KERNEL
= __pgprot (_PAGE_PRESENT_4U
| _PAGE_VALID
|
2346 _PAGE_CACHE_4U
| _PAGE_P_4U
|
2347 __ACCESS_BITS_4U
| __DIRTY_BITS_4U
|
2349 PAGE_KERNEL_LOCKED
= __pgprot (_PAGE_PRESENT_4U
| _PAGE_VALID
|
2350 _PAGE_CACHE_4U
| _PAGE_P_4U
|
2351 __ACCESS_BITS_4U
| __DIRTY_BITS_4U
|
2352 _PAGE_EXEC_4U
| _PAGE_L_4U
);
2354 _PAGE_IE
= _PAGE_IE_4U
;
2355 _PAGE_E
= _PAGE_E_4U
;
2356 _PAGE_CACHE
= _PAGE_CACHE_4U
;
2358 pg_iobits
= (_PAGE_VALID
| _PAGE_PRESENT_4U
| __DIRTY_BITS_4U
|
2359 __ACCESS_BITS_4U
| _PAGE_E_4U
);
2361 #ifdef CONFIG_DEBUG_PAGEALLOC
2362 kern_linear_pte_xor
[0] = _PAGE_VALID
^ PAGE_OFFSET
;
2364 kern_linear_pte_xor
[0] = (_PAGE_VALID
| _PAGE_SZ4MB_4U
) ^
2367 kern_linear_pte_xor
[0] |= (_PAGE_CP_4U
| _PAGE_CV_4U
|
2368 _PAGE_P_4U
| _PAGE_W_4U
);
2370 for (i
= 1; i
< 4; i
++)
2371 kern_linear_pte_xor
[i
] = kern_linear_pte_xor
[0];
2373 _PAGE_ALL_SZ_BITS
= (_PAGE_SZ4MB_4U
| _PAGE_SZ512K_4U
|
2374 _PAGE_SZ64K_4U
| _PAGE_SZ8K_4U
|
2375 _PAGE_SZ32MB_4U
| _PAGE_SZ256MB_4U
);
2378 page_none
= _PAGE_PRESENT_4U
| _PAGE_ACCESSED_4U
| _PAGE_CACHE_4U
;
2379 page_shared
= (_PAGE_VALID
| _PAGE_PRESENT_4U
| _PAGE_CACHE_4U
|
2380 __ACCESS_BITS_4U
| _PAGE_WRITE_4U
| _PAGE_EXEC_4U
);
2381 page_copy
= (_PAGE_VALID
| _PAGE_PRESENT_4U
| _PAGE_CACHE_4U
|
2382 __ACCESS_BITS_4U
| _PAGE_EXEC_4U
);
2383 page_readonly
= (_PAGE_VALID
| _PAGE_PRESENT_4U
| _PAGE_CACHE_4U
|
2384 __ACCESS_BITS_4U
| _PAGE_EXEC_4U
);
2386 page_exec_bit
= _PAGE_EXEC_4U
;
2388 prot_init_common(page_none
, page_shared
, page_copy
, page_readonly
,
2392 static void __init
sun4v_pgprot_init(void)
2394 unsigned long page_none
, page_shared
, page_copy
, page_readonly
;
2395 unsigned long page_exec_bit
;
2398 PAGE_KERNEL
= __pgprot (_PAGE_PRESENT_4V
| _PAGE_VALID
|
2399 _PAGE_CACHE_4V
| _PAGE_P_4V
|
2400 __ACCESS_BITS_4V
| __DIRTY_BITS_4V
|
2402 PAGE_KERNEL_LOCKED
= PAGE_KERNEL
;
2404 _PAGE_IE
= _PAGE_IE_4V
;
2405 _PAGE_E
= _PAGE_E_4V
;
2406 _PAGE_CACHE
= _PAGE_CACHE_4V
;
2408 #ifdef CONFIG_DEBUG_PAGEALLOC
2409 kern_linear_pte_xor
[0] = _PAGE_VALID
^ PAGE_OFFSET
;
2411 kern_linear_pte_xor
[0] = (_PAGE_VALID
| _PAGE_SZ4MB_4V
) ^
2414 kern_linear_pte_xor
[0] |= (_PAGE_CP_4V
| _PAGE_CV_4V
|
2415 _PAGE_P_4V
| _PAGE_W_4V
);
2417 for (i
= 1; i
< 4; i
++)
2418 kern_linear_pte_xor
[i
] = kern_linear_pte_xor
[0];
2420 pg_iobits
= (_PAGE_VALID
| _PAGE_PRESENT_4V
| __DIRTY_BITS_4V
|
2421 __ACCESS_BITS_4V
| _PAGE_E_4V
);
2423 _PAGE_ALL_SZ_BITS
= (_PAGE_SZ16GB_4V
| _PAGE_SZ2GB_4V
|
2424 _PAGE_SZ256MB_4V
| _PAGE_SZ32MB_4V
|
2425 _PAGE_SZ4MB_4V
| _PAGE_SZ512K_4V
|
2426 _PAGE_SZ64K_4V
| _PAGE_SZ8K_4V
);
2428 page_none
= _PAGE_PRESENT_4V
| _PAGE_ACCESSED_4V
| _PAGE_CACHE_4V
;
2429 page_shared
= (_PAGE_VALID
| _PAGE_PRESENT_4V
| _PAGE_CACHE_4V
|
2430 __ACCESS_BITS_4V
| _PAGE_WRITE_4V
| _PAGE_EXEC_4V
);
2431 page_copy
= (_PAGE_VALID
| _PAGE_PRESENT_4V
| _PAGE_CACHE_4V
|
2432 __ACCESS_BITS_4V
| _PAGE_EXEC_4V
);
2433 page_readonly
= (_PAGE_VALID
| _PAGE_PRESENT_4V
| _PAGE_CACHE_4V
|
2434 __ACCESS_BITS_4V
| _PAGE_EXEC_4V
);
2436 page_exec_bit
= _PAGE_EXEC_4V
;
2438 prot_init_common(page_none
, page_shared
, page_copy
, page_readonly
,
2442 unsigned long pte_sz_bits(unsigned long sz
)
2444 if (tlb_type
== hypervisor
) {
2448 return _PAGE_SZ8K_4V
;
2450 return _PAGE_SZ64K_4V
;
2452 return _PAGE_SZ512K_4V
;
2453 case 4 * 1024 * 1024:
2454 return _PAGE_SZ4MB_4V
;
2460 return _PAGE_SZ8K_4U
;
2462 return _PAGE_SZ64K_4U
;
2464 return _PAGE_SZ512K_4U
;
2465 case 4 * 1024 * 1024:
2466 return _PAGE_SZ4MB_4U
;
2471 pte_t
mk_pte_io(unsigned long page
, pgprot_t prot
, int space
, unsigned long page_size
)
2475 pte_val(pte
) = page
| pgprot_val(pgprot_noncached(prot
));
2476 pte_val(pte
) |= (((unsigned long)space
) << 32);
2477 pte_val(pte
) |= pte_sz_bits(page_size
);
2482 static unsigned long kern_large_tte(unsigned long paddr
)
2486 val
= (_PAGE_VALID
| _PAGE_SZ4MB_4U
|
2487 _PAGE_CP_4U
| _PAGE_CV_4U
| _PAGE_P_4U
|
2488 _PAGE_EXEC_4U
| _PAGE_L_4U
| _PAGE_W_4U
);
2489 if (tlb_type
== hypervisor
)
2490 val
= (_PAGE_VALID
| _PAGE_SZ4MB_4V
|
2491 _PAGE_CP_4V
| _PAGE_CV_4V
| _PAGE_P_4V
|
2492 _PAGE_EXEC_4V
| _PAGE_W_4V
);
2497 /* If not locked, zap it. */
2498 void __flush_tlb_all(void)
2500 unsigned long pstate
;
2503 __asm__
__volatile__("flushw\n\t"
2504 "rdpr %%pstate, %0\n\t"
2505 "wrpr %0, %1, %%pstate"
2508 if (tlb_type
== hypervisor
) {
2509 sun4v_mmu_demap_all();
2510 } else if (tlb_type
== spitfire
) {
2511 for (i
= 0; i
< 64; i
++) {
2512 /* Spitfire Errata #32 workaround */
2513 /* NOTE: Always runs on spitfire, so no
2514 * cheetah+ page size encodings.
2516 __asm__
__volatile__("stxa %0, [%1] %2\n\t"
2520 "r" (PRIMARY_CONTEXT
), "i" (ASI_DMMU
));
2522 if (!(spitfire_get_dtlb_data(i
) & _PAGE_L_4U
)) {
2523 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
2526 : "r" (TLB_TAG_ACCESS
), "i" (ASI_DMMU
));
2527 spitfire_put_dtlb_data(i
, 0x0UL
);
2530 /* Spitfire Errata #32 workaround */
2531 /* NOTE: Always runs on spitfire, so no
2532 * cheetah+ page size encodings.
2534 __asm__
__volatile__("stxa %0, [%1] %2\n\t"
2538 "r" (PRIMARY_CONTEXT
), "i" (ASI_DMMU
));
2540 if (!(spitfire_get_itlb_data(i
) & _PAGE_L_4U
)) {
2541 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
2544 : "r" (TLB_TAG_ACCESS
), "i" (ASI_IMMU
));
2545 spitfire_put_itlb_data(i
, 0x0UL
);
2548 } else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
2549 cheetah_flush_dtlb_all();
2550 cheetah_flush_itlb_all();
2552 __asm__
__volatile__("wrpr %0, 0, %%pstate"
2556 pte_t
*pte_alloc_one_kernel(struct mm_struct
*mm
,
2557 unsigned long address
)
2559 struct page
*page
= alloc_page(GFP_KERNEL
| __GFP_NOTRACK
|
2560 __GFP_REPEAT
| __GFP_ZERO
);
2564 pte
= (pte_t
*) page_address(page
);
2569 pgtable_t
pte_alloc_one(struct mm_struct
*mm
,
2570 unsigned long address
)
2572 struct page
*page
= alloc_page(GFP_KERNEL
| __GFP_NOTRACK
|
2573 __GFP_REPEAT
| __GFP_ZERO
);
2576 if (!pgtable_page_ctor(page
)) {
2577 free_hot_cold_page(page
, 0);
2580 return (pte_t
*) page_address(page
);
2583 void pte_free_kernel(struct mm_struct
*mm
, pte_t
*pte
)
2585 free_page((unsigned long)pte
);
2588 static void __pte_free(pgtable_t pte
)
2590 struct page
*page
= virt_to_page(pte
);
2592 pgtable_page_dtor(page
);
2596 void pte_free(struct mm_struct
*mm
, pgtable_t pte
)
2601 void pgtable_free(void *table
, bool is_page
)
2606 kmem_cache_free(pgtable_cache
, table
);
2609 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
2610 void update_mmu_cache_pmd(struct vm_area_struct
*vma
, unsigned long addr
,
2613 unsigned long pte
, flags
;
2614 struct mm_struct
*mm
;
2617 if (!pmd_large(entry
) || !pmd_young(entry
))
2620 pte
= pmd_val(entry
);
2622 /* We are fabricating 8MB pages using 4MB real hw pages. */
2623 pte
|= (addr
& (1UL << REAL_HPAGE_SHIFT
));
2627 spin_lock_irqsave(&mm
->context
.lock
, flags
);
2629 if (mm
->context
.tsb_block
[MM_TSB_HUGE
].tsb
!= NULL
)
2630 __update_mmu_tsb_insert(mm
, MM_TSB_HUGE
, REAL_HPAGE_SHIFT
,
2633 spin_unlock_irqrestore(&mm
->context
.lock
, flags
);
2635 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
2637 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
2638 static void context_reload(void *__data
)
2640 struct mm_struct
*mm
= __data
;
2642 if (mm
== current
->mm
)
2643 load_secondary_context(mm
);
2646 void hugetlb_setup(struct pt_regs
*regs
)
2648 struct mm_struct
*mm
= current
->mm
;
2649 struct tsb_config
*tp
;
2651 if (in_atomic() || !mm
) {
2652 const struct exception_table_entry
*entry
;
2654 entry
= search_exception_tables(regs
->tpc
);
2656 regs
->tpc
= entry
->fixup
;
2657 regs
->tnpc
= regs
->tpc
+ 4;
2660 pr_alert("Unexpected HugeTLB setup in atomic context.\n");
2661 die_if_kernel("HugeTSB in atomic", regs
);
2664 tp
= &mm
->context
.tsb_block
[MM_TSB_HUGE
];
2665 if (likely(tp
->tsb
== NULL
))
2666 tsb_grow(mm
, MM_TSB_HUGE
, 0);
2668 tsb_context_switch(mm
);
2671 /* On UltraSPARC-III+ and later, configure the second half of
2672 * the Data-TLB for huge pages.
2674 if (tlb_type
== cheetah_plus
) {
2677 spin_lock(&ctx_alloc_lock
);
2678 ctx
= mm
->context
.sparc64_ctx_val
;
2679 ctx
&= ~CTX_PGSZ_MASK
;
2680 ctx
|= CTX_PGSZ_BASE
<< CTX_PGSZ0_SHIFT
;
2681 ctx
|= CTX_PGSZ_HUGE
<< CTX_PGSZ1_SHIFT
;
2683 if (ctx
!= mm
->context
.sparc64_ctx_val
) {
2684 /* When changing the page size fields, we
2685 * must perform a context flush so that no
2686 * stale entries match. This flush must
2687 * occur with the original context register
2690 do_flush_tlb_mm(mm
);
2692 /* Reload the context register of all processors
2693 * also executing in this address space.
2695 mm
->context
.sparc64_ctx_val
= ctx
;
2696 on_each_cpu(context_reload
, mm
, 0);
2698 spin_unlock(&ctx_alloc_lock
);