2 * arch/sparc64/mm/init.c
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 #include <linux/module.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/string.h>
12 #include <linux/init.h>
13 #include <linux/bootmem.h>
15 #include <linux/hugetlb.h>
16 #include <linux/slab.h>
17 #include <linux/initrd.h>
18 #include <linux/swap.h>
19 #include <linux/pagemap.h>
20 #include <linux/poison.h>
22 #include <linux/seq_file.h>
23 #include <linux/kprobes.h>
24 #include <linux/cache.h>
25 #include <linux/sort.h>
26 #include <linux/percpu.h>
27 #include <linux/lmb.h>
28 #include <linux/mmzone.h>
31 #include <asm/system.h>
33 #include <asm/pgalloc.h>
34 #include <asm/pgtable.h>
35 #include <asm/oplib.h>
36 #include <asm/iommu.h>
38 #include <asm/uaccess.h>
39 #include <asm/mmu_context.h>
40 #include <asm/tlbflush.h>
42 #include <asm/starfire.h>
44 #include <asm/spitfire.h>
45 #include <asm/sections.h>
47 #include <asm/hypervisor.h>
49 #include <asm/mdesc.h>
50 #include <asm/cpudata.h>
55 unsigned long kern_linear_pte_xor
[2] __read_mostly
;
57 /* A bitmap, one bit for every 256MB of physical memory. If the bit
58 * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
59 * if set we should use a 256MB page (via kern_linear_pte_xor[1]).
61 unsigned long kpte_linear_bitmap
[KPTE_BITMAP_BYTES
/ sizeof(unsigned long)];
63 #ifndef CONFIG_DEBUG_PAGEALLOC
64 /* A special kernel TSB for 4MB and 256MB linear mappings.
65 * Space is allocated for this right after the trap table
66 * in arch/sparc64/kernel/head.S
68 extern struct tsb swapper_4m_tsb
[KERNEL_TSB4M_NENTRIES
];
73 static struct linux_prom64_registers pavail
[MAX_BANKS
] __devinitdata
;
74 static int pavail_ents __devinitdata
;
76 static int cmp_p64(const void *a
, const void *b
)
78 const struct linux_prom64_registers
*x
= a
, *y
= b
;
80 if (x
->phys_addr
> y
->phys_addr
)
82 if (x
->phys_addr
< y
->phys_addr
)
87 static void __init
read_obp_memory(const char *property
,
88 struct linux_prom64_registers
*regs
,
91 int node
= prom_finddevice("/memory");
92 int prop_size
= prom_getproplen(node
, property
);
95 ents
= prop_size
/ sizeof(struct linux_prom64_registers
);
96 if (ents
> MAX_BANKS
) {
97 prom_printf("The machine has more %s property entries than "
98 "this kernel can support (%d).\n",
103 ret
= prom_getproperty(node
, property
, (char *) regs
, prop_size
);
105 prom_printf("Couldn't get %s property from /memory.\n");
109 /* Sanitize what we got from the firmware, by page aligning
112 for (i
= 0; i
< ents
; i
++) {
113 unsigned long base
, size
;
115 base
= regs
[i
].phys_addr
;
116 size
= regs
[i
].reg_size
;
119 if (base
& ~PAGE_MASK
) {
120 unsigned long new_base
= PAGE_ALIGN(base
);
122 size
-= new_base
- base
;
123 if ((long) size
< 0L)
128 /* If it is empty, simply get rid of it.
129 * This simplifies the logic of the other
130 * functions that process these arrays.
132 memmove(®s
[i
], ®s
[i
+ 1],
133 (ents
- i
- 1) * sizeof(regs
[0]));
138 regs
[i
].phys_addr
= base
;
139 regs
[i
].reg_size
= size
;
144 sort(regs
, ents
, sizeof(struct linux_prom64_registers
),
148 unsigned long *sparc64_valid_addr_bitmap __read_mostly
;
149 EXPORT_SYMBOL(sparc64_valid_addr_bitmap
);
151 /* Kernel physical address base and size in bytes. */
152 unsigned long kern_base __read_mostly
;
153 unsigned long kern_size __read_mostly
;
155 /* Initial ramdisk setup */
156 extern unsigned long sparc_ramdisk_image64
;
157 extern unsigned int sparc_ramdisk_image
;
158 extern unsigned int sparc_ramdisk_size
;
160 struct page
*mem_map_zero __read_mostly
;
161 EXPORT_SYMBOL(mem_map_zero
);
163 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly
;
165 unsigned long sparc64_kern_pri_context __read_mostly
;
166 unsigned long sparc64_kern_pri_nuc_bits __read_mostly
;
167 unsigned long sparc64_kern_sec_context __read_mostly
;
169 int num_kernel_image_mappings
;
171 #ifdef CONFIG_DEBUG_DCFLUSH
172 atomic_t dcpage_flushes
= ATOMIC_INIT(0);
174 atomic_t dcpage_flushes_xcall
= ATOMIC_INIT(0);
178 inline void flush_dcache_page_impl(struct page
*page
)
180 BUG_ON(tlb_type
== hypervisor
);
181 #ifdef CONFIG_DEBUG_DCFLUSH
182 atomic_inc(&dcpage_flushes
);
185 #ifdef DCACHE_ALIASING_POSSIBLE
186 __flush_dcache_page(page_address(page
),
187 ((tlb_type
== spitfire
) &&
188 page_mapping(page
) != NULL
));
190 if (page_mapping(page
) != NULL
&&
191 tlb_type
== spitfire
)
192 __flush_icache_page(__pa(page_address(page
)));
196 #define PG_dcache_dirty PG_arch_1
197 #define PG_dcache_cpu_shift 32UL
198 #define PG_dcache_cpu_mask \
199 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
201 #define dcache_dirty_cpu(page) \
202 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
204 static inline void set_dcache_dirty(struct page
*page
, int this_cpu
)
206 unsigned long mask
= this_cpu
;
207 unsigned long non_cpu_bits
;
209 non_cpu_bits
= ~(PG_dcache_cpu_mask
<< PG_dcache_cpu_shift
);
210 mask
= (mask
<< PG_dcache_cpu_shift
) | (1UL << PG_dcache_dirty
);
212 __asm__
__volatile__("1:\n\t"
214 "and %%g7, %1, %%g1\n\t"
215 "or %%g1, %0, %%g1\n\t"
216 "casx [%2], %%g7, %%g1\n\t"
218 "bne,pn %%xcc, 1b\n\t"
221 : "r" (mask
), "r" (non_cpu_bits
), "r" (&page
->flags
)
225 static inline void clear_dcache_dirty_cpu(struct page
*page
, unsigned long cpu
)
227 unsigned long mask
= (1UL << PG_dcache_dirty
);
229 __asm__
__volatile__("! test_and_clear_dcache_dirty\n"
232 "srlx %%g7, %4, %%g1\n\t"
233 "and %%g1, %3, %%g1\n\t"
235 "bne,pn %%icc, 2f\n\t"
236 " andn %%g7, %1, %%g1\n\t"
237 "casx [%2], %%g7, %%g1\n\t"
239 "bne,pn %%xcc, 1b\n\t"
243 : "r" (cpu
), "r" (mask
), "r" (&page
->flags
),
244 "i" (PG_dcache_cpu_mask
),
245 "i" (PG_dcache_cpu_shift
)
249 static inline void tsb_insert(struct tsb
*ent
, unsigned long tag
, unsigned long pte
)
251 unsigned long tsb_addr
= (unsigned long) ent
;
253 if (tlb_type
== cheetah_plus
|| tlb_type
== hypervisor
)
254 tsb_addr
= __pa(tsb_addr
);
256 __tsb_insert(tsb_addr
, tag
, pte
);
259 unsigned long _PAGE_ALL_SZ_BITS __read_mostly
;
260 unsigned long _PAGE_SZBITS __read_mostly
;
262 static void flush_dcache(unsigned long pfn
)
266 page
= pfn_to_page(pfn
);
267 if (page
&& page_mapping(page
)) {
268 unsigned long pg_flags
;
270 pg_flags
= page
->flags
;
271 if (pg_flags
& (1UL << PG_dcache_dirty
)) {
272 int cpu
= ((pg_flags
>> PG_dcache_cpu_shift
) &
274 int this_cpu
= get_cpu();
276 /* This is just to optimize away some function calls
280 flush_dcache_page_impl(page
);
282 smp_flush_dcache_page_impl(page
, cpu
);
284 clear_dcache_dirty_cpu(page
, cpu
);
291 void update_mmu_cache(struct vm_area_struct
*vma
, unsigned long address
, pte_t pte
)
293 struct mm_struct
*mm
;
295 unsigned long tag
, flags
;
296 unsigned long tsb_index
, tsb_hash_shift
;
298 if (tlb_type
!= hypervisor
) {
299 unsigned long pfn
= pte_pfn(pte
);
307 tsb_index
= MM_TSB_BASE
;
308 tsb_hash_shift
= PAGE_SHIFT
;
310 spin_lock_irqsave(&mm
->context
.lock
, flags
);
312 #ifdef CONFIG_HUGETLB_PAGE
313 if (mm
->context
.tsb_block
[MM_TSB_HUGE
].tsb
!= NULL
) {
314 if ((tlb_type
== hypervisor
&&
315 (pte_val(pte
) & _PAGE_SZALL_4V
) == _PAGE_SZHUGE_4V
) ||
316 (tlb_type
!= hypervisor
&&
317 (pte_val(pte
) & _PAGE_SZALL_4U
) == _PAGE_SZHUGE_4U
)) {
318 tsb_index
= MM_TSB_HUGE
;
319 tsb_hash_shift
= HPAGE_SHIFT
;
324 tsb
= mm
->context
.tsb_block
[tsb_index
].tsb
;
325 tsb
+= ((address
>> tsb_hash_shift
) &
326 (mm
->context
.tsb_block
[tsb_index
].tsb_nentries
- 1UL));
327 tag
= (address
>> 22UL);
328 tsb_insert(tsb
, tag
, pte_val(pte
));
330 spin_unlock_irqrestore(&mm
->context
.lock
, flags
);
333 void flush_dcache_page(struct page
*page
)
335 struct address_space
*mapping
;
338 if (tlb_type
== hypervisor
)
341 /* Do not bother with the expensive D-cache flush if it
342 * is merely the zero page. The 'bigcore' testcase in GDB
343 * causes this case to run millions of times.
345 if (page
== ZERO_PAGE(0))
348 this_cpu
= get_cpu();
350 mapping
= page_mapping(page
);
351 if (mapping
&& !mapping_mapped(mapping
)) {
352 int dirty
= test_bit(PG_dcache_dirty
, &page
->flags
);
354 int dirty_cpu
= dcache_dirty_cpu(page
);
356 if (dirty_cpu
== this_cpu
)
358 smp_flush_dcache_page_impl(page
, dirty_cpu
);
360 set_dcache_dirty(page
, this_cpu
);
362 /* We could delay the flush for the !page_mapping
363 * case too. But that case is for exec env/arg
364 * pages and those are %99 certainly going to get
365 * faulted into the tlb (and thus flushed) anyways.
367 flush_dcache_page_impl(page
);
373 EXPORT_SYMBOL(flush_dcache_page
);
375 void __kprobes
flush_icache_range(unsigned long start
, unsigned long end
)
377 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
378 if (tlb_type
== spitfire
) {
381 /* This code only runs on Spitfire cpus so this is
382 * why we can assume _PAGE_PADDR_4U.
384 for (kaddr
= start
; kaddr
< end
; kaddr
+= PAGE_SIZE
) {
385 unsigned long paddr
, mask
= _PAGE_PADDR_4U
;
387 if (kaddr
>= PAGE_OFFSET
)
388 paddr
= kaddr
& mask
;
390 pgd_t
*pgdp
= pgd_offset_k(kaddr
);
391 pud_t
*pudp
= pud_offset(pgdp
, kaddr
);
392 pmd_t
*pmdp
= pmd_offset(pudp
, kaddr
);
393 pte_t
*ptep
= pte_offset_kernel(pmdp
, kaddr
);
395 paddr
= pte_val(*ptep
) & mask
;
397 __flush_icache_page(paddr
);
401 EXPORT_SYMBOL(flush_icache_range
);
403 void mmu_info(struct seq_file
*m
)
405 if (tlb_type
== cheetah
)
406 seq_printf(m
, "MMU Type\t: Cheetah\n");
407 else if (tlb_type
== cheetah_plus
)
408 seq_printf(m
, "MMU Type\t: Cheetah+\n");
409 else if (tlb_type
== spitfire
)
410 seq_printf(m
, "MMU Type\t: Spitfire\n");
411 else if (tlb_type
== hypervisor
)
412 seq_printf(m
, "MMU Type\t: Hypervisor (sun4v)\n");
414 seq_printf(m
, "MMU Type\t: ???\n");
416 #ifdef CONFIG_DEBUG_DCFLUSH
417 seq_printf(m
, "DCPageFlushes\t: %d\n",
418 atomic_read(&dcpage_flushes
));
420 seq_printf(m
, "DCPageFlushesXC\t: %d\n",
421 atomic_read(&dcpage_flushes_xcall
));
422 #endif /* CONFIG_SMP */
423 #endif /* CONFIG_DEBUG_DCFLUSH */
426 struct linux_prom_translation prom_trans
[512] __read_mostly
;
427 unsigned int prom_trans_ents __read_mostly
;
429 unsigned long kern_locked_tte_data
;
431 /* The obp translations are saved based on 8k pagesize, since obp can
432 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
433 * HI_OBP_ADDRESS range are handled in ktlb.S.
435 static inline int in_obp_range(unsigned long vaddr
)
437 return (vaddr
>= LOW_OBP_ADDRESS
&&
438 vaddr
< HI_OBP_ADDRESS
);
441 static int cmp_ptrans(const void *a
, const void *b
)
443 const struct linux_prom_translation
*x
= a
, *y
= b
;
445 if (x
->virt
> y
->virt
)
447 if (x
->virt
< y
->virt
)
452 /* Read OBP translations property into 'prom_trans[]'. */
453 static void __init
read_obp_translations(void)
455 int n
, node
, ents
, first
, last
, i
;
457 node
= prom_finddevice("/virtual-memory");
458 n
= prom_getproplen(node
, "translations");
459 if (unlikely(n
== 0 || n
== -1)) {
460 prom_printf("prom_mappings: Couldn't get size.\n");
463 if (unlikely(n
> sizeof(prom_trans
))) {
464 prom_printf("prom_mappings: Size %Zd is too big.\n", n
);
468 if ((n
= prom_getproperty(node
, "translations",
469 (char *)&prom_trans
[0],
470 sizeof(prom_trans
))) == -1) {
471 prom_printf("prom_mappings: Couldn't get property.\n");
475 n
= n
/ sizeof(struct linux_prom_translation
);
479 sort(prom_trans
, ents
, sizeof(struct linux_prom_translation
),
482 /* Now kick out all the non-OBP entries. */
483 for (i
= 0; i
< ents
; i
++) {
484 if (in_obp_range(prom_trans
[i
].virt
))
488 for (; i
< ents
; i
++) {
489 if (!in_obp_range(prom_trans
[i
].virt
))
494 for (i
= 0; i
< (last
- first
); i
++) {
495 struct linux_prom_translation
*src
= &prom_trans
[i
+ first
];
496 struct linux_prom_translation
*dest
= &prom_trans
[i
];
500 for (; i
< ents
; i
++) {
501 struct linux_prom_translation
*dest
= &prom_trans
[i
];
502 dest
->virt
= dest
->size
= dest
->data
= 0x0UL
;
505 prom_trans_ents
= last
- first
;
507 if (tlb_type
== spitfire
) {
508 /* Clear diag TTE bits. */
509 for (i
= 0; i
< prom_trans_ents
; i
++)
510 prom_trans
[i
].data
&= ~0x0003fe0000000000UL
;
514 static void __init
hypervisor_tlb_lock(unsigned long vaddr
,
518 unsigned long ret
= sun4v_mmu_map_perm_addr(vaddr
, 0, pte
, mmu
);
521 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
522 "errors with %lx\n", vaddr
, 0, pte
, mmu
, ret
);
527 static unsigned long kern_large_tte(unsigned long paddr
);
529 static void __init
remap_kernel(void)
531 unsigned long phys_page
, tte_vaddr
, tte_data
;
532 int i
, tlb_ent
= sparc64_highest_locked_tlbent();
534 tte_vaddr
= (unsigned long) KERNBASE
;
535 phys_page
= (prom_boot_mapping_phys_low
>> 22UL) << 22UL;
536 tte_data
= kern_large_tte(phys_page
);
538 kern_locked_tte_data
= tte_data
;
540 /* Now lock us into the TLBs via Hypervisor or OBP. */
541 if (tlb_type
== hypervisor
) {
542 for (i
= 0; i
< num_kernel_image_mappings
; i
++) {
543 hypervisor_tlb_lock(tte_vaddr
, tte_data
, HV_MMU_DMMU
);
544 hypervisor_tlb_lock(tte_vaddr
, tte_data
, HV_MMU_IMMU
);
545 tte_vaddr
+= 0x400000;
546 tte_data
+= 0x400000;
549 for (i
= 0; i
< num_kernel_image_mappings
; i
++) {
550 prom_dtlb_load(tlb_ent
- i
, tte_data
, tte_vaddr
);
551 prom_itlb_load(tlb_ent
- i
, tte_data
, tte_vaddr
);
552 tte_vaddr
+= 0x400000;
553 tte_data
+= 0x400000;
555 sparc64_highest_unlocked_tlb_ent
= tlb_ent
- i
;
557 if (tlb_type
== cheetah_plus
) {
558 sparc64_kern_pri_context
= (CTX_CHEETAH_PLUS_CTX0
|
559 CTX_CHEETAH_PLUS_NUC
);
560 sparc64_kern_pri_nuc_bits
= CTX_CHEETAH_PLUS_NUC
;
561 sparc64_kern_sec_context
= CTX_CHEETAH_PLUS_CTX0
;
566 static void __init
inherit_prom_mappings(void)
568 /* Now fixup OBP's idea about where we really are mapped. */
569 printk("Remapping the kernel... ");
574 void prom_world(int enter
)
577 set_fs((mm_segment_t
) { get_thread_current_ds() });
579 __asm__
__volatile__("flushw");
582 void __flush_dcache_range(unsigned long start
, unsigned long end
)
586 if (tlb_type
== spitfire
) {
589 for (va
= start
; va
< end
; va
+= 32) {
590 spitfire_put_dcache_tag(va
& 0x3fe0, 0x0);
594 } else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
597 for (va
= start
; va
< end
; va
+= 32)
598 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
602 "i" (ASI_DCACHE_INVALIDATE
));
605 EXPORT_SYMBOL(__flush_dcache_range
);
607 /* get_new_mmu_context() uses "cache + 1". */
608 DEFINE_SPINLOCK(ctx_alloc_lock
);
609 unsigned long tlb_context_cache
= CTX_FIRST_VERSION
- 1;
610 #define MAX_CTX_NR (1UL << CTX_NR_BITS)
611 #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
612 DECLARE_BITMAP(mmu_context_bmap
, MAX_CTX_NR
);
614 /* Caller does TLB context flushing on local CPU if necessary.
615 * The caller also ensures that CTX_VALID(mm->context) is false.
617 * We must be careful about boundary cases so that we never
618 * let the user have CTX 0 (nucleus) or we ever use a CTX
619 * version of zero (and thus NO_CONTEXT would not be caught
620 * by version mis-match tests in mmu_context.h).
622 * Always invoked with interrupts disabled.
624 void get_new_mmu_context(struct mm_struct
*mm
)
626 unsigned long ctx
, new_ctx
;
627 unsigned long orig_pgsz_bits
;
631 spin_lock_irqsave(&ctx_alloc_lock
, flags
);
632 orig_pgsz_bits
= (mm
->context
.sparc64_ctx_val
& CTX_PGSZ_MASK
);
633 ctx
= (tlb_context_cache
+ 1) & CTX_NR_MASK
;
634 new_ctx
= find_next_zero_bit(mmu_context_bmap
, 1 << CTX_NR_BITS
, ctx
);
636 if (new_ctx
>= (1 << CTX_NR_BITS
)) {
637 new_ctx
= find_next_zero_bit(mmu_context_bmap
, ctx
, 1);
638 if (new_ctx
>= ctx
) {
640 new_ctx
= (tlb_context_cache
& CTX_VERSION_MASK
) +
643 new_ctx
= CTX_FIRST_VERSION
;
645 /* Don't call memset, for 16 entries that's just
648 mmu_context_bmap
[0] = 3;
649 mmu_context_bmap
[1] = 0;
650 mmu_context_bmap
[2] = 0;
651 mmu_context_bmap
[3] = 0;
652 for (i
= 4; i
< CTX_BMAP_SLOTS
; i
+= 4) {
653 mmu_context_bmap
[i
+ 0] = 0;
654 mmu_context_bmap
[i
+ 1] = 0;
655 mmu_context_bmap
[i
+ 2] = 0;
656 mmu_context_bmap
[i
+ 3] = 0;
662 mmu_context_bmap
[new_ctx
>>6] |= (1UL << (new_ctx
& 63));
663 new_ctx
|= (tlb_context_cache
& CTX_VERSION_MASK
);
665 tlb_context_cache
= new_ctx
;
666 mm
->context
.sparc64_ctx_val
= new_ctx
| orig_pgsz_bits
;
667 spin_unlock_irqrestore(&ctx_alloc_lock
, flags
);
669 if (unlikely(new_version
))
670 smp_new_mmu_context_version();
673 static int numa_enabled
= 1;
674 static int numa_debug
;
676 static int __init
early_numa(char *p
)
681 if (strstr(p
, "off"))
684 if (strstr(p
, "debug"))
689 early_param("numa", early_numa
);
691 #define numadbg(f, a...) \
692 do { if (numa_debug) \
693 printk(KERN_INFO f, ## a); \
696 static void __init
find_ramdisk(unsigned long phys_base
)
698 #ifdef CONFIG_BLK_DEV_INITRD
699 if (sparc_ramdisk_image
|| sparc_ramdisk_image64
) {
700 unsigned long ramdisk_image
;
702 /* Older versions of the bootloader only supported a
703 * 32-bit physical address for the ramdisk image
704 * location, stored at sparc_ramdisk_image. Newer
705 * SILO versions set sparc_ramdisk_image to zero and
706 * provide a full 64-bit physical address at
707 * sparc_ramdisk_image64.
709 ramdisk_image
= sparc_ramdisk_image
;
711 ramdisk_image
= sparc_ramdisk_image64
;
713 /* Another bootloader quirk. The bootloader normalizes
714 * the physical address to KERNBASE, so we have to
715 * factor that back out and add in the lowest valid
716 * physical page address to get the true physical address.
718 ramdisk_image
-= KERNBASE
;
719 ramdisk_image
+= phys_base
;
721 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
722 ramdisk_image
, sparc_ramdisk_size
);
724 initrd_start
= ramdisk_image
;
725 initrd_end
= ramdisk_image
+ sparc_ramdisk_size
;
727 lmb_reserve(initrd_start
, sparc_ramdisk_size
);
729 initrd_start
+= PAGE_OFFSET
;
730 initrd_end
+= PAGE_OFFSET
;
735 struct node_mem_mask
{
738 unsigned long bootmem_paddr
;
740 static struct node_mem_mask node_masks
[MAX_NUMNODES
];
741 static int num_node_masks
;
743 int numa_cpu_lookup_table
[NR_CPUS
];
744 cpumask_t numa_cpumask_lookup_table
[MAX_NUMNODES
];
746 #ifdef CONFIG_NEED_MULTIPLE_NODES
748 struct mdesc_mblock
{
751 u64 offset
; /* RA-to-PA */
753 static struct mdesc_mblock
*mblocks
;
754 static int num_mblocks
;
756 static unsigned long ra_to_pa(unsigned long addr
)
760 for (i
= 0; i
< num_mblocks
; i
++) {
761 struct mdesc_mblock
*m
= &mblocks
[i
];
763 if (addr
>= m
->base
&&
764 addr
< (m
->base
+ m
->size
)) {
772 static int find_node(unsigned long addr
)
776 addr
= ra_to_pa(addr
);
777 for (i
= 0; i
< num_node_masks
; i
++) {
778 struct node_mem_mask
*p
= &node_masks
[i
];
780 if ((addr
& p
->mask
) == p
->val
)
786 static unsigned long long nid_range(unsigned long long start
,
787 unsigned long long end
, int *nid
)
789 *nid
= find_node(start
);
791 while (start
< end
) {
792 int n
= find_node(start
);
805 static unsigned long long nid_range(unsigned long long start
,
806 unsigned long long end
, int *nid
)
813 /* This must be invoked after performing all of the necessary
814 * add_active_range() calls for 'nid'. We need to be able to get
815 * correct data from get_pfn_range_for_nid().
817 static void __init
allocate_node_data(int nid
)
819 unsigned long paddr
, num_pages
, start_pfn
, end_pfn
;
820 struct pglist_data
*p
;
822 #ifdef CONFIG_NEED_MULTIPLE_NODES
823 paddr
= lmb_alloc_nid(sizeof(struct pglist_data
),
824 SMP_CACHE_BYTES
, nid
, nid_range
);
826 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid
);
829 NODE_DATA(nid
) = __va(paddr
);
830 memset(NODE_DATA(nid
), 0, sizeof(struct pglist_data
));
832 NODE_DATA(nid
)->bdata
= &bootmem_node_data
[nid
];
837 get_pfn_range_for_nid(nid
, &start_pfn
, &end_pfn
);
838 p
->node_start_pfn
= start_pfn
;
839 p
->node_spanned_pages
= end_pfn
- start_pfn
;
841 if (p
->node_spanned_pages
) {
842 num_pages
= bootmem_bootmap_pages(p
->node_spanned_pages
);
844 paddr
= lmb_alloc_nid(num_pages
<< PAGE_SHIFT
, PAGE_SIZE
, nid
,
847 prom_printf("Cannot allocate bootmap for nid[%d]\n",
851 node_masks
[nid
].bootmem_paddr
= paddr
;
855 static void init_node_masks_nonnuma(void)
859 numadbg("Initializing tables for non-numa.\n");
861 node_masks
[0].mask
= node_masks
[0].val
= 0;
864 for (i
= 0; i
< NR_CPUS
; i
++)
865 numa_cpu_lookup_table
[i
] = 0;
867 numa_cpumask_lookup_table
[0] = CPU_MASK_ALL
;
870 #ifdef CONFIG_NEED_MULTIPLE_NODES
871 struct pglist_data
*node_data
[MAX_NUMNODES
];
873 EXPORT_SYMBOL(numa_cpu_lookup_table
);
874 EXPORT_SYMBOL(numa_cpumask_lookup_table
);
875 EXPORT_SYMBOL(node_data
);
877 struct mdesc_mlgroup
{
883 static struct mdesc_mlgroup
*mlgroups
;
884 static int num_mlgroups
;
886 static int scan_pio_for_cfg_handle(struct mdesc_handle
*md
, u64 pio
,
891 mdesc_for_each_arc(arc
, md
, pio
, MDESC_ARC_TYPE_FWD
) {
892 u64 target
= mdesc_arc_target(md
, arc
);
895 val
= mdesc_get_property(md
, target
,
897 if (val
&& *val
== cfg_handle
)
903 static int scan_arcs_for_cfg_handle(struct mdesc_handle
*md
, u64 grp
,
906 u64 arc
, candidate
, best_latency
= ~(u64
)0;
908 candidate
= MDESC_NODE_NULL
;
909 mdesc_for_each_arc(arc
, md
, grp
, MDESC_ARC_TYPE_FWD
) {
910 u64 target
= mdesc_arc_target(md
, arc
);
911 const char *name
= mdesc_node_name(md
, target
);
914 if (strcmp(name
, "pio-latency-group"))
917 val
= mdesc_get_property(md
, target
, "latency", NULL
);
921 if (*val
< best_latency
) {
927 if (candidate
== MDESC_NODE_NULL
)
930 return scan_pio_for_cfg_handle(md
, candidate
, cfg_handle
);
933 int of_node_to_nid(struct device_node
*dp
)
935 const struct linux_prom64_registers
*regs
;
936 struct mdesc_handle
*md
;
941 /* This is the right thing to do on currently supported
942 * SUN4U NUMA platforms as well, as the PCI controller does
943 * not sit behind any particular memory controller.
948 regs
= of_get_property(dp
, "reg", NULL
);
952 cfg_handle
= (regs
->phys_addr
>> 32UL) & 0x0fffffff;
958 mdesc_for_each_node_by_name(md
, grp
, "group") {
959 if (!scan_arcs_for_cfg_handle(md
, grp
, cfg_handle
)) {
971 static void add_node_ranges(void)
975 for (i
= 0; i
< lmb
.memory
.cnt
; i
++) {
976 unsigned long size
= lmb_size_bytes(&lmb
.memory
, i
);
977 unsigned long start
, end
;
979 start
= lmb
.memory
.region
[i
].base
;
981 while (start
< end
) {
982 unsigned long this_end
;
985 this_end
= nid_range(start
, end
, &nid
);
987 numadbg("Adding active range nid[%d] "
988 "start[%lx] end[%lx]\n",
989 nid
, start
, this_end
);
991 add_active_range(nid
,
993 this_end
>> PAGE_SHIFT
);
1000 static int __init
grab_mlgroups(struct mdesc_handle
*md
)
1002 unsigned long paddr
;
1006 mdesc_for_each_node_by_name(md
, node
, "memory-latency-group")
1011 paddr
= lmb_alloc(count
* sizeof(struct mdesc_mlgroup
),
1016 mlgroups
= __va(paddr
);
1017 num_mlgroups
= count
;
1020 mdesc_for_each_node_by_name(md
, node
, "memory-latency-group") {
1021 struct mdesc_mlgroup
*m
= &mlgroups
[count
++];
1026 val
= mdesc_get_property(md
, node
, "latency", NULL
);
1028 val
= mdesc_get_property(md
, node
, "address-match", NULL
);
1030 val
= mdesc_get_property(md
, node
, "address-mask", NULL
);
1033 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
1034 "match[%llx] mask[%llx]\n",
1035 count
- 1, m
->node
, m
->latency
, m
->match
, m
->mask
);
1041 static int __init
grab_mblocks(struct mdesc_handle
*md
)
1043 unsigned long paddr
;
1047 mdesc_for_each_node_by_name(md
, node
, "mblock")
1052 paddr
= lmb_alloc(count
* sizeof(struct mdesc_mblock
),
1057 mblocks
= __va(paddr
);
1058 num_mblocks
= count
;
1061 mdesc_for_each_node_by_name(md
, node
, "mblock") {
1062 struct mdesc_mblock
*m
= &mblocks
[count
++];
1065 val
= mdesc_get_property(md
, node
, "base", NULL
);
1067 val
= mdesc_get_property(md
, node
, "size", NULL
);
1069 val
= mdesc_get_property(md
, node
,
1070 "address-congruence-offset", NULL
);
1073 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
1074 count
- 1, m
->base
, m
->size
, m
->offset
);
1080 static void __init
numa_parse_mdesc_group_cpus(struct mdesc_handle
*md
,
1081 u64 grp
, cpumask_t
*mask
)
1087 mdesc_for_each_arc(arc
, md
, grp
, MDESC_ARC_TYPE_BACK
) {
1088 u64 target
= mdesc_arc_target(md
, arc
);
1089 const char *name
= mdesc_node_name(md
, target
);
1092 if (strcmp(name
, "cpu"))
1094 id
= mdesc_get_property(md
, target
, "id", NULL
);
1095 if (*id
< nr_cpu_ids
)
1096 cpu_set(*id
, *mask
);
1100 static struct mdesc_mlgroup
* __init
find_mlgroup(u64 node
)
1104 for (i
= 0; i
< num_mlgroups
; i
++) {
1105 struct mdesc_mlgroup
*m
= &mlgroups
[i
];
1106 if (m
->node
== node
)
1112 static int __init
numa_attach_mlgroup(struct mdesc_handle
*md
, u64 grp
,
1115 struct mdesc_mlgroup
*candidate
= NULL
;
1116 u64 arc
, best_latency
= ~(u64
)0;
1117 struct node_mem_mask
*n
;
1119 mdesc_for_each_arc(arc
, md
, grp
, MDESC_ARC_TYPE_FWD
) {
1120 u64 target
= mdesc_arc_target(md
, arc
);
1121 struct mdesc_mlgroup
*m
= find_mlgroup(target
);
1124 if (m
->latency
< best_latency
) {
1126 best_latency
= m
->latency
;
1132 if (num_node_masks
!= index
) {
1133 printk(KERN_ERR
"Inconsistent NUMA state, "
1134 "index[%d] != num_node_masks[%d]\n",
1135 index
, num_node_masks
);
1139 n
= &node_masks
[num_node_masks
++];
1141 n
->mask
= candidate
->mask
;
1142 n
->val
= candidate
->match
;
1144 numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%llx])\n",
1145 index
, n
->mask
, n
->val
, candidate
->latency
);
1150 static int __init
numa_parse_mdesc_group(struct mdesc_handle
*md
, u64 grp
,
1156 numa_parse_mdesc_group_cpus(md
, grp
, &mask
);
1158 for_each_cpu_mask(cpu
, mask
)
1159 numa_cpu_lookup_table
[cpu
] = index
;
1160 numa_cpumask_lookup_table
[index
] = mask
;
1163 printk(KERN_INFO
"NUMA GROUP[%d]: cpus [ ", index
);
1164 for_each_cpu_mask(cpu
, mask
)
1169 return numa_attach_mlgroup(md
, grp
, index
);
1172 static int __init
numa_parse_mdesc(void)
1174 struct mdesc_handle
*md
= mdesc_grab();
1178 node
= mdesc_node_by_name(md
, MDESC_NODE_NULL
, "latency-groups");
1179 if (node
== MDESC_NODE_NULL
) {
1184 err
= grab_mblocks(md
);
1188 err
= grab_mlgroups(md
);
1193 mdesc_for_each_node_by_name(md
, node
, "group") {
1194 err
= numa_parse_mdesc_group(md
, node
, count
);
1202 for (i
= 0; i
< num_node_masks
; i
++) {
1203 allocate_node_data(i
);
1213 static int __init
numa_parse_jbus(void)
1215 unsigned long cpu
, index
;
1217 /* NUMA node id is encoded in bits 36 and higher, and there is
1218 * a 1-to-1 mapping from CPU ID to NUMA node ID.
1221 for_each_present_cpu(cpu
) {
1222 numa_cpu_lookup_table
[cpu
] = index
;
1223 numa_cpumask_lookup_table
[index
] = cpumask_of_cpu(cpu
);
1224 node_masks
[index
].mask
= ~((1UL << 36UL) - 1UL);
1225 node_masks
[index
].val
= cpu
<< 36UL;
1229 num_node_masks
= index
;
1233 for (index
= 0; index
< num_node_masks
; index
++) {
1234 allocate_node_data(index
);
1235 node_set_online(index
);
1241 static int __init
numa_parse_sun4u(void)
1243 if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
1246 __asm__ ("rdpr %%ver, %0" : "=r" (ver
));
1247 if ((ver
>> 32UL) == __JALAPENO_ID
||
1248 (ver
>> 32UL) == __SERRANO_ID
)
1249 return numa_parse_jbus();
1254 static int __init
bootmem_init_numa(void)
1258 numadbg("bootmem_init_numa()\n");
1261 if (tlb_type
== hypervisor
)
1262 err
= numa_parse_mdesc();
1264 err
= numa_parse_sun4u();
1271 static int bootmem_init_numa(void)
1278 static void __init
bootmem_init_nonnuma(void)
1280 unsigned long top_of_ram
= lmb_end_of_DRAM();
1281 unsigned long total_ram
= lmb_phys_mem_size();
1284 numadbg("bootmem_init_nonnuma()\n");
1286 printk(KERN_INFO
"Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1287 top_of_ram
, total_ram
);
1288 printk(KERN_INFO
"Memory hole size: %ldMB\n",
1289 (top_of_ram
- total_ram
) >> 20);
1291 init_node_masks_nonnuma();
1293 for (i
= 0; i
< lmb
.memory
.cnt
; i
++) {
1294 unsigned long size
= lmb_size_bytes(&lmb
.memory
, i
);
1295 unsigned long start_pfn
, end_pfn
;
1300 start_pfn
= lmb
.memory
.region
[i
].base
>> PAGE_SHIFT
;
1301 end_pfn
= start_pfn
+ lmb_size_pages(&lmb
.memory
, i
);
1302 add_active_range(0, start_pfn
, end_pfn
);
1305 allocate_node_data(0);
1310 static void __init
reserve_range_in_node(int nid
, unsigned long start
,
1313 numadbg(" reserve_range_in_node(nid[%d],start[%lx],end[%lx]\n",
1315 while (start
< end
) {
1316 unsigned long this_end
;
1319 this_end
= nid_range(start
, end
, &n
);
1321 numadbg(" MATCH reserving range [%lx:%lx]\n",
1323 reserve_bootmem_node(NODE_DATA(nid
), start
,
1324 (this_end
- start
), BOOTMEM_DEFAULT
);
1326 numadbg(" NO MATCH, advancing start to %lx\n",
1333 static void __init
trim_reserved_in_node(int nid
)
1337 numadbg(" trim_reserved_in_node(%d)\n", nid
);
1339 for (i
= 0; i
< lmb
.reserved
.cnt
; i
++) {
1340 unsigned long start
= lmb
.reserved
.region
[i
].base
;
1341 unsigned long size
= lmb_size_bytes(&lmb
.reserved
, i
);
1342 unsigned long end
= start
+ size
;
1344 reserve_range_in_node(nid
, start
, end
);
1348 static void __init
bootmem_init_one_node(int nid
)
1350 struct pglist_data
*p
;
1352 numadbg("bootmem_init_one_node(%d)\n", nid
);
1356 if (p
->node_spanned_pages
) {
1357 unsigned long paddr
= node_masks
[nid
].bootmem_paddr
;
1358 unsigned long end_pfn
;
1360 end_pfn
= p
->node_start_pfn
+ p
->node_spanned_pages
;
1362 numadbg(" init_bootmem_node(%d, %lx, %lx, %lx)\n",
1363 nid
, paddr
>> PAGE_SHIFT
, p
->node_start_pfn
, end_pfn
);
1365 init_bootmem_node(p
, paddr
>> PAGE_SHIFT
,
1366 p
->node_start_pfn
, end_pfn
);
1368 numadbg(" free_bootmem_with_active_regions(%d, %lx)\n",
1370 free_bootmem_with_active_regions(nid
, end_pfn
);
1372 trim_reserved_in_node(nid
);
1374 numadbg(" sparse_memory_present_with_active_regions(%d)\n",
1376 sparse_memory_present_with_active_regions(nid
);
1380 static unsigned long __init
bootmem_init(unsigned long phys_base
)
1382 unsigned long end_pfn
;
1385 end_pfn
= lmb_end_of_DRAM() >> PAGE_SHIFT
;
1386 max_pfn
= max_low_pfn
= end_pfn
;
1387 min_low_pfn
= (phys_base
>> PAGE_SHIFT
);
1389 if (bootmem_init_numa() < 0)
1390 bootmem_init_nonnuma();
1392 /* XXX cpu notifier XXX */
1394 for_each_online_node(nid
)
1395 bootmem_init_one_node(nid
);
1402 static struct linux_prom64_registers pall
[MAX_BANKS
] __initdata
;
1403 static int pall_ents __initdata
;
1405 #ifdef CONFIG_DEBUG_PAGEALLOC
1406 static unsigned long __ref
kernel_map_range(unsigned long pstart
,
1407 unsigned long pend
, pgprot_t prot
)
1409 unsigned long vstart
= PAGE_OFFSET
+ pstart
;
1410 unsigned long vend
= PAGE_OFFSET
+ pend
;
1411 unsigned long alloc_bytes
= 0UL;
1413 if ((vstart
& ~PAGE_MASK
) || (vend
& ~PAGE_MASK
)) {
1414 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1419 while (vstart
< vend
) {
1420 unsigned long this_end
, paddr
= __pa(vstart
);
1421 pgd_t
*pgd
= pgd_offset_k(vstart
);
1426 pud
= pud_offset(pgd
, vstart
);
1427 if (pud_none(*pud
)) {
1430 new = __alloc_bootmem(PAGE_SIZE
, PAGE_SIZE
, PAGE_SIZE
);
1431 alloc_bytes
+= PAGE_SIZE
;
1432 pud_populate(&init_mm
, pud
, new);
1435 pmd
= pmd_offset(pud
, vstart
);
1436 if (!pmd_present(*pmd
)) {
1439 new = __alloc_bootmem(PAGE_SIZE
, PAGE_SIZE
, PAGE_SIZE
);
1440 alloc_bytes
+= PAGE_SIZE
;
1441 pmd_populate_kernel(&init_mm
, pmd
, new);
1444 pte
= pte_offset_kernel(pmd
, vstart
);
1445 this_end
= (vstart
+ PMD_SIZE
) & PMD_MASK
;
1446 if (this_end
> vend
)
1449 while (vstart
< this_end
) {
1450 pte_val(*pte
) = (paddr
| pgprot_val(prot
));
1452 vstart
+= PAGE_SIZE
;
1461 extern unsigned int kvmap_linear_patch
[1];
1462 #endif /* CONFIG_DEBUG_PAGEALLOC */
1464 static void __init
mark_kpte_bitmap(unsigned long start
, unsigned long end
)
1466 const unsigned long shift_256MB
= 28;
1467 const unsigned long mask_256MB
= ((1UL << shift_256MB
) - 1UL);
1468 const unsigned long size_256MB
= (1UL << shift_256MB
);
1470 while (start
< end
) {
1473 remains
= end
- start
;
1474 if (remains
< size_256MB
)
1477 if (start
& mask_256MB
) {
1478 start
= (start
+ size_256MB
) & ~mask_256MB
;
1482 while (remains
>= size_256MB
) {
1483 unsigned long index
= start
>> shift_256MB
;
1485 __set_bit(index
, kpte_linear_bitmap
);
1487 start
+= size_256MB
;
1488 remains
-= size_256MB
;
1493 static void __init
init_kpte_bitmap(void)
1497 for (i
= 0; i
< pall_ents
; i
++) {
1498 unsigned long phys_start
, phys_end
;
1500 phys_start
= pall
[i
].phys_addr
;
1501 phys_end
= phys_start
+ pall
[i
].reg_size
;
1503 mark_kpte_bitmap(phys_start
, phys_end
);
1507 static void __init
kernel_physical_mapping_init(void)
1509 #ifdef CONFIG_DEBUG_PAGEALLOC
1510 unsigned long i
, mem_alloced
= 0UL;
1512 for (i
= 0; i
< pall_ents
; i
++) {
1513 unsigned long phys_start
, phys_end
;
1515 phys_start
= pall
[i
].phys_addr
;
1516 phys_end
= phys_start
+ pall
[i
].reg_size
;
1518 mem_alloced
+= kernel_map_range(phys_start
, phys_end
,
1522 printk("Allocated %ld bytes for kernel page tables.\n",
1525 kvmap_linear_patch
[0] = 0x01000000; /* nop */
1526 flushi(&kvmap_linear_patch
[0]);
1532 #ifdef CONFIG_DEBUG_PAGEALLOC
1533 void kernel_map_pages(struct page
*page
, int numpages
, int enable
)
1535 unsigned long phys_start
= page_to_pfn(page
) << PAGE_SHIFT
;
1536 unsigned long phys_end
= phys_start
+ (numpages
* PAGE_SIZE
);
1538 kernel_map_range(phys_start
, phys_end
,
1539 (enable
? PAGE_KERNEL
: __pgprot(0)));
1541 flush_tsb_kernel_range(PAGE_OFFSET
+ phys_start
,
1542 PAGE_OFFSET
+ phys_end
);
1544 /* we should perform an IPI and flush all tlbs,
1545 * but that can deadlock->flush only current cpu.
1547 __flush_tlb_kernel_range(PAGE_OFFSET
+ phys_start
,
1548 PAGE_OFFSET
+ phys_end
);
1552 unsigned long __init
find_ecache_flush_span(unsigned long size
)
1556 for (i
= 0; i
< pavail_ents
; i
++) {
1557 if (pavail
[i
].reg_size
>= size
)
1558 return pavail
[i
].phys_addr
;
1564 static void __init
tsb_phys_patch(void)
1566 struct tsb_ldquad_phys_patch_entry
*pquad
;
1567 struct tsb_phys_patch_entry
*p
;
1569 pquad
= &__tsb_ldquad_phys_patch
;
1570 while (pquad
< &__tsb_ldquad_phys_patch_end
) {
1571 unsigned long addr
= pquad
->addr
;
1573 if (tlb_type
== hypervisor
)
1574 *(unsigned int *) addr
= pquad
->sun4v_insn
;
1576 *(unsigned int *) addr
= pquad
->sun4u_insn
;
1578 __asm__
__volatile__("flush %0"
1585 p
= &__tsb_phys_patch
;
1586 while (p
< &__tsb_phys_patch_end
) {
1587 unsigned long addr
= p
->addr
;
1589 *(unsigned int *) addr
= p
->insn
;
1591 __asm__
__volatile__("flush %0"
1599 /* Don't mark as init, we give this to the Hypervisor. */
1600 #ifndef CONFIG_DEBUG_PAGEALLOC
1601 #define NUM_KTSB_DESCR 2
1603 #define NUM_KTSB_DESCR 1
1605 static struct hv_tsb_descr ktsb_descr
[NUM_KTSB_DESCR
];
1606 extern struct tsb swapper_tsb
[KERNEL_TSB_NENTRIES
];
1608 static void __init
sun4v_ktsb_init(void)
1610 unsigned long ktsb_pa
;
1612 /* First KTSB for PAGE_SIZE mappings. */
1613 ktsb_pa
= kern_base
+ ((unsigned long)&swapper_tsb
[0] - KERNBASE
);
1615 switch (PAGE_SIZE
) {
1618 ktsb_descr
[0].pgsz_idx
= HV_PGSZ_IDX_8K
;
1619 ktsb_descr
[0].pgsz_mask
= HV_PGSZ_MASK_8K
;
1623 ktsb_descr
[0].pgsz_idx
= HV_PGSZ_IDX_64K
;
1624 ktsb_descr
[0].pgsz_mask
= HV_PGSZ_MASK_64K
;
1628 ktsb_descr
[0].pgsz_idx
= HV_PGSZ_IDX_512K
;
1629 ktsb_descr
[0].pgsz_mask
= HV_PGSZ_MASK_512K
;
1632 case 4 * 1024 * 1024:
1633 ktsb_descr
[0].pgsz_idx
= HV_PGSZ_IDX_4MB
;
1634 ktsb_descr
[0].pgsz_mask
= HV_PGSZ_MASK_4MB
;
1638 ktsb_descr
[0].assoc
= 1;
1639 ktsb_descr
[0].num_ttes
= KERNEL_TSB_NENTRIES
;
1640 ktsb_descr
[0].ctx_idx
= 0;
1641 ktsb_descr
[0].tsb_base
= ktsb_pa
;
1642 ktsb_descr
[0].resv
= 0;
1644 #ifndef CONFIG_DEBUG_PAGEALLOC
1645 /* Second KTSB for 4MB/256MB mappings. */
1646 ktsb_pa
= (kern_base
+
1647 ((unsigned long)&swapper_4m_tsb
[0] - KERNBASE
));
1649 ktsb_descr
[1].pgsz_idx
= HV_PGSZ_IDX_4MB
;
1650 ktsb_descr
[1].pgsz_mask
= (HV_PGSZ_MASK_4MB
|
1651 HV_PGSZ_MASK_256MB
);
1652 ktsb_descr
[1].assoc
= 1;
1653 ktsb_descr
[1].num_ttes
= KERNEL_TSB4M_NENTRIES
;
1654 ktsb_descr
[1].ctx_idx
= 0;
1655 ktsb_descr
[1].tsb_base
= ktsb_pa
;
1656 ktsb_descr
[1].resv
= 0;
1660 void __cpuinit
sun4v_ktsb_register(void)
1662 unsigned long pa
, ret
;
1664 pa
= kern_base
+ ((unsigned long)&ktsb_descr
[0] - KERNBASE
);
1666 ret
= sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR
, pa
);
1668 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1669 "errors with %lx\n", pa
, ret
);
1674 /* paging_init() sets up the page tables */
1676 static unsigned long last_valid_pfn
;
1677 pgd_t swapper_pg_dir
[2048];
1679 static void sun4u_pgprot_init(void);
1680 static void sun4v_pgprot_init(void);
1682 /* Dummy function */
1683 void __init
setup_per_cpu_areas(void)
1687 void __init
paging_init(void)
1689 unsigned long end_pfn
, shift
, phys_base
;
1690 unsigned long real_end
, i
;
1692 /* These build time checkes make sure that the dcache_dirty_cpu()
1693 * page->flags usage will work.
1695 * When a page gets marked as dcache-dirty, we store the
1696 * cpu number starting at bit 32 in the page->flags. Also,
1697 * functions like clear_dcache_dirty_cpu use the cpu mask
1698 * in 13-bit signed-immediate instruction fields.
1702 * Page flags must not reach into upper 32 bits that are used
1703 * for the cpu number
1705 BUILD_BUG_ON(NR_PAGEFLAGS
> 32);
1708 * The bit fields placed in the high range must not reach below
1709 * the 32 bit boundary. Otherwise we cannot place the cpu field
1710 * at the 32 bit boundary.
1712 BUILD_BUG_ON(SECTIONS_WIDTH
+ NODES_WIDTH
+ ZONES_WIDTH
+
1713 ilog2(roundup_pow_of_two(NR_CPUS
)) > 32);
1715 BUILD_BUG_ON(NR_CPUS
> 4096);
1717 kern_base
= (prom_boot_mapping_phys_low
>> 22UL) << 22UL;
1718 kern_size
= (unsigned long)&_end
- (unsigned long)KERNBASE
;
1720 /* Invalidate both kernel TSBs. */
1721 memset(swapper_tsb
, 0x40, sizeof(swapper_tsb
));
1722 #ifndef CONFIG_DEBUG_PAGEALLOC
1723 memset(swapper_4m_tsb
, 0x40, sizeof(swapper_4m_tsb
));
1726 if (tlb_type
== hypervisor
)
1727 sun4v_pgprot_init();
1729 sun4u_pgprot_init();
1731 if (tlb_type
== cheetah_plus
||
1732 tlb_type
== hypervisor
)
1735 if (tlb_type
== hypervisor
) {
1736 sun4v_patch_tlb_handlers();
1742 /* Find available physical memory...
1744 * Read it twice in order to work around a bug in openfirmware.
1745 * The call to grab this table itself can cause openfirmware to
1746 * allocate memory, which in turn can take away some space from
1747 * the list of available memory. Reading it twice makes sure
1748 * we really do get the final value.
1750 read_obp_translations();
1751 read_obp_memory("reg", &pall
[0], &pall_ents
);
1752 read_obp_memory("available", &pavail
[0], &pavail_ents
);
1753 read_obp_memory("available", &pavail
[0], &pavail_ents
);
1755 phys_base
= 0xffffffffffffffffUL
;
1756 for (i
= 0; i
< pavail_ents
; i
++) {
1757 phys_base
= min(phys_base
, pavail
[i
].phys_addr
);
1758 lmb_add(pavail
[i
].phys_addr
, pavail
[i
].reg_size
);
1761 lmb_reserve(kern_base
, kern_size
);
1763 find_ramdisk(phys_base
);
1765 lmb_enforce_memory_limit(cmdline_memory_size
);
1770 set_bit(0, mmu_context_bmap
);
1772 shift
= kern_base
+ PAGE_OFFSET
- ((unsigned long)KERNBASE
);
1774 real_end
= (unsigned long)_end
;
1775 num_kernel_image_mappings
= DIV_ROUND_UP(real_end
- KERNBASE
, 1 << 22);
1776 printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
1777 num_kernel_image_mappings
);
1779 /* Set kernel pgd to upper alias so physical page computations
1782 init_mm
.pgd
+= ((shift
) / (sizeof(pgd_t
)));
1784 memset(swapper_low_pmd_dir
, 0, sizeof(swapper_low_pmd_dir
));
1786 /* Now can init the kernel/bad page tables. */
1787 pud_set(pud_offset(&swapper_pg_dir
[0], 0),
1788 swapper_low_pmd_dir
+ (shift
/ sizeof(pgd_t
)));
1790 inherit_prom_mappings();
1794 /* Ok, we can use our TLB miss and window trap handlers safely. */
1799 if (tlb_type
== hypervisor
)
1800 sun4v_ktsb_register();
1802 /* We must setup the per-cpu areas before we pull in the
1803 * PROM and the MDESC. The code there fills in cpu and
1804 * other information into per-cpu data structures.
1806 real_setup_per_cpu_areas();
1808 prom_build_devicetree();
1810 if (tlb_type
== hypervisor
)
1813 /* Once the OF device tree and MDESC have been setup, we know
1814 * the list of possible cpus. Therefore we can allocate the
1817 for_each_possible_cpu(i
) {
1818 /* XXX Use node local allocations... XXX */
1819 softirq_stack
[i
] = __va(lmb_alloc(THREAD_SIZE
, THREAD_SIZE
));
1820 hardirq_stack
[i
] = __va(lmb_alloc(THREAD_SIZE
, THREAD_SIZE
));
1823 /* Setup bootmem... */
1824 last_valid_pfn
= end_pfn
= bootmem_init(phys_base
);
1826 #ifndef CONFIG_NEED_MULTIPLE_NODES
1827 max_mapnr
= last_valid_pfn
;
1829 kernel_physical_mapping_init();
1832 unsigned long max_zone_pfns
[MAX_NR_ZONES
];
1834 memset(max_zone_pfns
, 0, sizeof(max_zone_pfns
));
1836 max_zone_pfns
[ZONE_NORMAL
] = end_pfn
;
1838 free_area_init_nodes(max_zone_pfns
);
1841 printk("Booting Linux...\n");
1844 int __devinit
page_in_phys_avail(unsigned long paddr
)
1850 for (i
= 0; i
< pavail_ents
; i
++) {
1851 unsigned long start
, end
;
1853 start
= pavail
[i
].phys_addr
;
1854 end
= start
+ pavail
[i
].reg_size
;
1856 if (paddr
>= start
&& paddr
< end
)
1859 if (paddr
>= kern_base
&& paddr
< (kern_base
+ kern_size
))
1861 #ifdef CONFIG_BLK_DEV_INITRD
1862 if (paddr
>= __pa(initrd_start
) &&
1863 paddr
< __pa(PAGE_ALIGN(initrd_end
)))
1870 static struct linux_prom64_registers pavail_rescan
[MAX_BANKS
] __initdata
;
1871 static int pavail_rescan_ents __initdata
;
1873 /* Certain OBP calls, such as fetching "available" properties, can
1874 * claim physical memory. So, along with initializing the valid
1875 * address bitmap, what we do here is refetch the physical available
1876 * memory list again, and make sure it provides at least as much
1877 * memory as 'pavail' does.
1879 static void __init
setup_valid_addr_bitmap_from_pavail(void)
1883 read_obp_memory("available", &pavail_rescan
[0], &pavail_rescan_ents
);
1885 for (i
= 0; i
< pavail_ents
; i
++) {
1886 unsigned long old_start
, old_end
;
1888 old_start
= pavail
[i
].phys_addr
;
1889 old_end
= old_start
+ pavail
[i
].reg_size
;
1890 while (old_start
< old_end
) {
1893 for (n
= 0; n
< pavail_rescan_ents
; n
++) {
1894 unsigned long new_start
, new_end
;
1896 new_start
= pavail_rescan
[n
].phys_addr
;
1897 new_end
= new_start
+
1898 pavail_rescan
[n
].reg_size
;
1900 if (new_start
<= old_start
&&
1901 new_end
>= (old_start
+ PAGE_SIZE
)) {
1902 set_bit(old_start
>> 22,
1903 sparc64_valid_addr_bitmap
);
1908 prom_printf("mem_init: Lost memory in pavail\n");
1909 prom_printf("mem_init: OLD start[%lx] size[%lx]\n",
1910 pavail
[i
].phys_addr
,
1911 pavail
[i
].reg_size
);
1912 prom_printf("mem_init: NEW start[%lx] size[%lx]\n",
1913 pavail_rescan
[i
].phys_addr
,
1914 pavail_rescan
[i
].reg_size
);
1915 prom_printf("mem_init: Cannot continue, aborting.\n");
1919 old_start
+= PAGE_SIZE
;
1924 void __init
mem_init(void)
1926 unsigned long codepages
, datapages
, initpages
;
1927 unsigned long addr
, last
;
1930 i
= last_valid_pfn
>> ((22 - PAGE_SHIFT
) + 6);
1932 sparc64_valid_addr_bitmap
= (unsigned long *) alloc_bootmem(i
<< 3);
1933 if (sparc64_valid_addr_bitmap
== NULL
) {
1934 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1937 memset(sparc64_valid_addr_bitmap
, 0, i
<< 3);
1939 addr
= PAGE_OFFSET
+ kern_base
;
1940 last
= PAGE_ALIGN(kern_size
) + addr
;
1941 while (addr
< last
) {
1942 set_bit(__pa(addr
) >> 22, sparc64_valid_addr_bitmap
);
1946 setup_valid_addr_bitmap_from_pavail();
1948 high_memory
= __va(last_valid_pfn
<< PAGE_SHIFT
);
1950 #ifdef CONFIG_NEED_MULTIPLE_NODES
1951 for_each_online_node(i
) {
1952 if (NODE_DATA(i
)->node_spanned_pages
!= 0) {
1954 free_all_bootmem_node(NODE_DATA(i
));
1958 totalram_pages
= free_all_bootmem();
1961 /* We subtract one to account for the mem_map_zero page
1964 totalram_pages
-= 1;
1965 num_physpages
= totalram_pages
;
1968 * Set up the zero page, mark it reserved, so that page count
1969 * is not manipulated when freeing the page from user ptes.
1971 mem_map_zero
= alloc_pages(GFP_KERNEL
|__GFP_ZERO
, 0);
1972 if (mem_map_zero
== NULL
) {
1973 prom_printf("paging_init: Cannot alloc zero page.\n");
1976 SetPageReserved(mem_map_zero
);
1978 codepages
= (((unsigned long) _etext
) - ((unsigned long) _start
));
1979 codepages
= PAGE_ALIGN(codepages
) >> PAGE_SHIFT
;
1980 datapages
= (((unsigned long) _edata
) - ((unsigned long) _etext
));
1981 datapages
= PAGE_ALIGN(datapages
) >> PAGE_SHIFT
;
1982 initpages
= (((unsigned long) __init_end
) - ((unsigned long) __init_begin
));
1983 initpages
= PAGE_ALIGN(initpages
) >> PAGE_SHIFT
;
1985 printk("Memory: %luk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1986 nr_free_pages() << (PAGE_SHIFT
-10),
1987 codepages
<< (PAGE_SHIFT
-10),
1988 datapages
<< (PAGE_SHIFT
-10),
1989 initpages
<< (PAGE_SHIFT
-10),
1990 PAGE_OFFSET
, (last_valid_pfn
<< PAGE_SHIFT
));
1992 if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
)
1993 cheetah_ecache_flush_init();
1996 void free_initmem(void)
1998 unsigned long addr
, initend
;
2001 /* If the physical memory maps were trimmed by kernel command
2002 * line options, don't even try freeing this initmem stuff up.
2003 * The kernel image could have been in the trimmed out region
2004 * and if so the freeing below will free invalid page structs.
2006 if (cmdline_memory_size
)
2010 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2012 addr
= PAGE_ALIGN((unsigned long)(__init_begin
));
2013 initend
= (unsigned long)(__init_end
) & PAGE_MASK
;
2014 for (; addr
< initend
; addr
+= PAGE_SIZE
) {
2019 ((unsigned long) __va(kern_base
)) -
2020 ((unsigned long) KERNBASE
));
2021 memset((void *)addr
, POISON_FREE_INITMEM
, PAGE_SIZE
);
2024 p
= virt_to_page(page
);
2026 ClearPageReserved(p
);
2035 #ifdef CONFIG_BLK_DEV_INITRD
2036 void free_initrd_mem(unsigned long start
, unsigned long end
)
2039 printk ("Freeing initrd memory: %ldk freed\n", (end
- start
) >> 10);
2040 for (; start
< end
; start
+= PAGE_SIZE
) {
2041 struct page
*p
= virt_to_page(start
);
2043 ClearPageReserved(p
);
2052 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
2053 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
2054 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2055 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2056 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2057 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2059 pgprot_t PAGE_KERNEL __read_mostly
;
2060 EXPORT_SYMBOL(PAGE_KERNEL
);
2062 pgprot_t PAGE_KERNEL_LOCKED __read_mostly
;
2063 pgprot_t PAGE_COPY __read_mostly
;
2065 pgprot_t PAGE_SHARED __read_mostly
;
2066 EXPORT_SYMBOL(PAGE_SHARED
);
2068 unsigned long pg_iobits __read_mostly
;
2070 unsigned long _PAGE_IE __read_mostly
;
2071 EXPORT_SYMBOL(_PAGE_IE
);
2073 unsigned long _PAGE_E __read_mostly
;
2074 EXPORT_SYMBOL(_PAGE_E
);
2076 unsigned long _PAGE_CACHE __read_mostly
;
2077 EXPORT_SYMBOL(_PAGE_CACHE
);
2079 #ifdef CONFIG_SPARSEMEM_VMEMMAP
2080 unsigned long vmemmap_table
[VMEMMAP_SIZE
];
2082 int __meminit
vmemmap_populate(struct page
*start
, unsigned long nr
, int node
)
2084 unsigned long vstart
= (unsigned long) start
;
2085 unsigned long vend
= (unsigned long) (start
+ nr
);
2086 unsigned long phys_start
= (vstart
- VMEMMAP_BASE
);
2087 unsigned long phys_end
= (vend
- VMEMMAP_BASE
);
2088 unsigned long addr
= phys_start
& VMEMMAP_CHUNK_MASK
;
2089 unsigned long end
= VMEMMAP_ALIGN(phys_end
);
2090 unsigned long pte_base
;
2092 pte_base
= (_PAGE_VALID
| _PAGE_SZ4MB_4U
|
2093 _PAGE_CP_4U
| _PAGE_CV_4U
|
2094 _PAGE_P_4U
| _PAGE_W_4U
);
2095 if (tlb_type
== hypervisor
)
2096 pte_base
= (_PAGE_VALID
| _PAGE_SZ4MB_4V
|
2097 _PAGE_CP_4V
| _PAGE_CV_4V
|
2098 _PAGE_P_4V
| _PAGE_W_4V
);
2100 for (; addr
< end
; addr
+= VMEMMAP_CHUNK
) {
2101 unsigned long *vmem_pp
=
2102 vmemmap_table
+ (addr
>> VMEMMAP_CHUNK_SHIFT
);
2105 if (!(*vmem_pp
& _PAGE_VALID
)) {
2106 block
= vmemmap_alloc_block(1UL << 22, node
);
2110 *vmem_pp
= pte_base
| __pa(block
);
2112 printk(KERN_INFO
"[%p-%p] page_structs=%lu "
2113 "node=%d entry=%lu/%lu\n", start
, block
, nr
,
2115 addr
>> VMEMMAP_CHUNK_SHIFT
,
2116 VMEMMAP_SIZE
>> VMEMMAP_CHUNK_SHIFT
);
2121 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
2123 static void prot_init_common(unsigned long page_none
,
2124 unsigned long page_shared
,
2125 unsigned long page_copy
,
2126 unsigned long page_readonly
,
2127 unsigned long page_exec_bit
)
2129 PAGE_COPY
= __pgprot(page_copy
);
2130 PAGE_SHARED
= __pgprot(page_shared
);
2132 protection_map
[0x0] = __pgprot(page_none
);
2133 protection_map
[0x1] = __pgprot(page_readonly
& ~page_exec_bit
);
2134 protection_map
[0x2] = __pgprot(page_copy
& ~page_exec_bit
);
2135 protection_map
[0x3] = __pgprot(page_copy
& ~page_exec_bit
);
2136 protection_map
[0x4] = __pgprot(page_readonly
);
2137 protection_map
[0x5] = __pgprot(page_readonly
);
2138 protection_map
[0x6] = __pgprot(page_copy
);
2139 protection_map
[0x7] = __pgprot(page_copy
);
2140 protection_map
[0x8] = __pgprot(page_none
);
2141 protection_map
[0x9] = __pgprot(page_readonly
& ~page_exec_bit
);
2142 protection_map
[0xa] = __pgprot(page_shared
& ~page_exec_bit
);
2143 protection_map
[0xb] = __pgprot(page_shared
& ~page_exec_bit
);
2144 protection_map
[0xc] = __pgprot(page_readonly
);
2145 protection_map
[0xd] = __pgprot(page_readonly
);
2146 protection_map
[0xe] = __pgprot(page_shared
);
2147 protection_map
[0xf] = __pgprot(page_shared
);
2150 static void __init
sun4u_pgprot_init(void)
2152 unsigned long page_none
, page_shared
, page_copy
, page_readonly
;
2153 unsigned long page_exec_bit
;
2155 PAGE_KERNEL
= __pgprot (_PAGE_PRESENT_4U
| _PAGE_VALID
|
2156 _PAGE_CACHE_4U
| _PAGE_P_4U
|
2157 __ACCESS_BITS_4U
| __DIRTY_BITS_4U
|
2159 PAGE_KERNEL_LOCKED
= __pgprot (_PAGE_PRESENT_4U
| _PAGE_VALID
|
2160 _PAGE_CACHE_4U
| _PAGE_P_4U
|
2161 __ACCESS_BITS_4U
| __DIRTY_BITS_4U
|
2162 _PAGE_EXEC_4U
| _PAGE_L_4U
);
2164 _PAGE_IE
= _PAGE_IE_4U
;
2165 _PAGE_E
= _PAGE_E_4U
;
2166 _PAGE_CACHE
= _PAGE_CACHE_4U
;
2168 pg_iobits
= (_PAGE_VALID
| _PAGE_PRESENT_4U
| __DIRTY_BITS_4U
|
2169 __ACCESS_BITS_4U
| _PAGE_E_4U
);
2171 #ifdef CONFIG_DEBUG_PAGEALLOC
2172 kern_linear_pte_xor
[0] = (_PAGE_VALID
| _PAGE_SZBITS_4U
) ^
2173 0xfffff80000000000UL
;
2175 kern_linear_pte_xor
[0] = (_PAGE_VALID
| _PAGE_SZ4MB_4U
) ^
2176 0xfffff80000000000UL
;
2178 kern_linear_pte_xor
[0] |= (_PAGE_CP_4U
| _PAGE_CV_4U
|
2179 _PAGE_P_4U
| _PAGE_W_4U
);
2181 /* XXX Should use 256MB on Panther. XXX */
2182 kern_linear_pte_xor
[1] = kern_linear_pte_xor
[0];
2184 _PAGE_SZBITS
= _PAGE_SZBITS_4U
;
2185 _PAGE_ALL_SZ_BITS
= (_PAGE_SZ4MB_4U
| _PAGE_SZ512K_4U
|
2186 _PAGE_SZ64K_4U
| _PAGE_SZ8K_4U
|
2187 _PAGE_SZ32MB_4U
| _PAGE_SZ256MB_4U
);
2190 page_none
= _PAGE_PRESENT_4U
| _PAGE_ACCESSED_4U
| _PAGE_CACHE_4U
;
2191 page_shared
= (_PAGE_VALID
| _PAGE_PRESENT_4U
| _PAGE_CACHE_4U
|
2192 __ACCESS_BITS_4U
| _PAGE_WRITE_4U
| _PAGE_EXEC_4U
);
2193 page_copy
= (_PAGE_VALID
| _PAGE_PRESENT_4U
| _PAGE_CACHE_4U
|
2194 __ACCESS_BITS_4U
| _PAGE_EXEC_4U
);
2195 page_readonly
= (_PAGE_VALID
| _PAGE_PRESENT_4U
| _PAGE_CACHE_4U
|
2196 __ACCESS_BITS_4U
| _PAGE_EXEC_4U
);
2198 page_exec_bit
= _PAGE_EXEC_4U
;
2200 prot_init_common(page_none
, page_shared
, page_copy
, page_readonly
,
2204 static void __init
sun4v_pgprot_init(void)
2206 unsigned long page_none
, page_shared
, page_copy
, page_readonly
;
2207 unsigned long page_exec_bit
;
2209 PAGE_KERNEL
= __pgprot (_PAGE_PRESENT_4V
| _PAGE_VALID
|
2210 _PAGE_CACHE_4V
| _PAGE_P_4V
|
2211 __ACCESS_BITS_4V
| __DIRTY_BITS_4V
|
2213 PAGE_KERNEL_LOCKED
= PAGE_KERNEL
;
2215 _PAGE_IE
= _PAGE_IE_4V
;
2216 _PAGE_E
= _PAGE_E_4V
;
2217 _PAGE_CACHE
= _PAGE_CACHE_4V
;
2219 #ifdef CONFIG_DEBUG_PAGEALLOC
2220 kern_linear_pte_xor
[0] = (_PAGE_VALID
| _PAGE_SZBITS_4V
) ^
2221 0xfffff80000000000UL
;
2223 kern_linear_pte_xor
[0] = (_PAGE_VALID
| _PAGE_SZ4MB_4V
) ^
2224 0xfffff80000000000UL
;
2226 kern_linear_pte_xor
[0] |= (_PAGE_CP_4V
| _PAGE_CV_4V
|
2227 _PAGE_P_4V
| _PAGE_W_4V
);
2229 #ifdef CONFIG_DEBUG_PAGEALLOC
2230 kern_linear_pte_xor
[1] = (_PAGE_VALID
| _PAGE_SZBITS_4V
) ^
2231 0xfffff80000000000UL
;
2233 kern_linear_pte_xor
[1] = (_PAGE_VALID
| _PAGE_SZ256MB_4V
) ^
2234 0xfffff80000000000UL
;
2236 kern_linear_pte_xor
[1] |= (_PAGE_CP_4V
| _PAGE_CV_4V
|
2237 _PAGE_P_4V
| _PAGE_W_4V
);
2239 pg_iobits
= (_PAGE_VALID
| _PAGE_PRESENT_4V
| __DIRTY_BITS_4V
|
2240 __ACCESS_BITS_4V
| _PAGE_E_4V
);
2242 _PAGE_SZBITS
= _PAGE_SZBITS_4V
;
2243 _PAGE_ALL_SZ_BITS
= (_PAGE_SZ16GB_4V
| _PAGE_SZ2GB_4V
|
2244 _PAGE_SZ256MB_4V
| _PAGE_SZ32MB_4V
|
2245 _PAGE_SZ4MB_4V
| _PAGE_SZ512K_4V
|
2246 _PAGE_SZ64K_4V
| _PAGE_SZ8K_4V
);
2248 page_none
= _PAGE_PRESENT_4V
| _PAGE_ACCESSED_4V
| _PAGE_CACHE_4V
;
2249 page_shared
= (_PAGE_VALID
| _PAGE_PRESENT_4V
| _PAGE_CACHE_4V
|
2250 __ACCESS_BITS_4V
| _PAGE_WRITE_4V
| _PAGE_EXEC_4V
);
2251 page_copy
= (_PAGE_VALID
| _PAGE_PRESENT_4V
| _PAGE_CACHE_4V
|
2252 __ACCESS_BITS_4V
| _PAGE_EXEC_4V
);
2253 page_readonly
= (_PAGE_VALID
| _PAGE_PRESENT_4V
| _PAGE_CACHE_4V
|
2254 __ACCESS_BITS_4V
| _PAGE_EXEC_4V
);
2256 page_exec_bit
= _PAGE_EXEC_4V
;
2258 prot_init_common(page_none
, page_shared
, page_copy
, page_readonly
,
2262 unsigned long pte_sz_bits(unsigned long sz
)
2264 if (tlb_type
== hypervisor
) {
2268 return _PAGE_SZ8K_4V
;
2270 return _PAGE_SZ64K_4V
;
2272 return _PAGE_SZ512K_4V
;
2273 case 4 * 1024 * 1024:
2274 return _PAGE_SZ4MB_4V
;
2280 return _PAGE_SZ8K_4U
;
2282 return _PAGE_SZ64K_4U
;
2284 return _PAGE_SZ512K_4U
;
2285 case 4 * 1024 * 1024:
2286 return _PAGE_SZ4MB_4U
;
2291 pte_t
mk_pte_io(unsigned long page
, pgprot_t prot
, int space
, unsigned long page_size
)
2295 pte_val(pte
) = page
| pgprot_val(pgprot_noncached(prot
));
2296 pte_val(pte
) |= (((unsigned long)space
) << 32);
2297 pte_val(pte
) |= pte_sz_bits(page_size
);
2302 static unsigned long kern_large_tte(unsigned long paddr
)
2306 val
= (_PAGE_VALID
| _PAGE_SZ4MB_4U
|
2307 _PAGE_CP_4U
| _PAGE_CV_4U
| _PAGE_P_4U
|
2308 _PAGE_EXEC_4U
| _PAGE_L_4U
| _PAGE_W_4U
);
2309 if (tlb_type
== hypervisor
)
2310 val
= (_PAGE_VALID
| _PAGE_SZ4MB_4V
|
2311 _PAGE_CP_4V
| _PAGE_CV_4V
| _PAGE_P_4V
|
2312 _PAGE_EXEC_4V
| _PAGE_W_4V
);
2317 /* If not locked, zap it. */
2318 void __flush_tlb_all(void)
2320 unsigned long pstate
;
2323 __asm__
__volatile__("flushw\n\t"
2324 "rdpr %%pstate, %0\n\t"
2325 "wrpr %0, %1, %%pstate"
2328 if (tlb_type
== hypervisor
) {
2329 sun4v_mmu_demap_all();
2330 } else if (tlb_type
== spitfire
) {
2331 for (i
= 0; i
< 64; i
++) {
2332 /* Spitfire Errata #32 workaround */
2333 /* NOTE: Always runs on spitfire, so no
2334 * cheetah+ page size encodings.
2336 __asm__
__volatile__("stxa %0, [%1] %2\n\t"
2340 "r" (PRIMARY_CONTEXT
), "i" (ASI_DMMU
));
2342 if (!(spitfire_get_dtlb_data(i
) & _PAGE_L_4U
)) {
2343 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
2346 : "r" (TLB_TAG_ACCESS
), "i" (ASI_DMMU
));
2347 spitfire_put_dtlb_data(i
, 0x0UL
);
2350 /* Spitfire Errata #32 workaround */
2351 /* NOTE: Always runs on spitfire, so no
2352 * cheetah+ page size encodings.
2354 __asm__
__volatile__("stxa %0, [%1] %2\n\t"
2358 "r" (PRIMARY_CONTEXT
), "i" (ASI_DMMU
));
2360 if (!(spitfire_get_itlb_data(i
) & _PAGE_L_4U
)) {
2361 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
2364 : "r" (TLB_TAG_ACCESS
), "i" (ASI_IMMU
));
2365 spitfire_put_itlb_data(i
, 0x0UL
);
2368 } else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
2369 cheetah_flush_dtlb_all();
2370 cheetah_flush_itlb_all();
2372 __asm__
__volatile__("wrpr %0, 0, %%pstate"