2 * ultra.S: Don't expand these all over the place...
4 * Copyright (C) 1997, 2000, 2008 David S. Miller (davem@davemloft.net)
8 #include <asm/pgtable.h>
10 #include <asm/spitfire.h>
11 #include <asm/mmu_context.h>
15 #include <asm/thread_info.h>
16 #include <asm/cacheflush.h>
17 #include <asm/hypervisor.h>
18 #include <asm/cpudata.h>
20 /* Basically, most of the Spitfire vs. Cheetah madness
21 * has to do with the fact that Cheetah does not support
22 * IMMU flushes out of the secondary context. Someone needs
23 * to throw a south lake birthday party for the folks
24 * in Microelectronics who refused to fix this shit.
27 /* This file is meant to be read efficiently by the CPU, not humans.
28 * Staraj sie tego nikomu nie pierdolnac...
33 __flush_tlb_mm: /* 18 insns */
34 /* %o0=(ctx & TAG_CONTEXT_BITS), %o1=SECONDARY_CONTEXT */
35 ldxa [%o1] ASI_DMMU, %g2
37 bne,pn %icc, __spitfire_flush_tlb_mm_slow
39 stxa %g0, [%g3] ASI_DMMU_DEMAP
40 stxa %g0, [%g3] ASI_IMMU_DEMAP
41 sethi %hi(KERNBASE), %g3
56 .globl __flush_tlb_pending
57 __flush_tlb_pending: /* 26 insns */
58 /* %o0 = context, %o1 = nr, %o2 = vaddrs[] */
61 andn %g7, PSTATE_IE, %g2
63 mov SECONDARY_CONTEXT, %o4
64 ldxa [%o4] ASI_DMMU, %g2
65 stxa %o0, [%o4] ASI_DMMU
66 1: sub %o1, (1 << 3), %o1
72 stxa %g0, [%o3] ASI_IMMU_DEMAP
73 2: stxa %g0, [%o3] ASI_DMMU_DEMAP
77 stxa %g2, [%o4] ASI_DMMU
78 sethi %hi(KERNBASE), %o4
81 wrpr %g7, 0x0, %pstate
88 .globl __flush_tlb_kernel_range
89 __flush_tlb_kernel_range: /* 16 insns */
90 /* %o0=start, %o1=end */
93 sethi %hi(PAGE_SIZE), %o4
96 or %o0, 0x20, %o0 ! Nucleus
97 1: stxa %g0, [%o0 + %o3] ASI_DMMU_DEMAP
98 stxa %g0, [%o0 + %o3] ASI_IMMU_DEMAP
102 2: sethi %hi(KERNBASE), %o3
108 __spitfire_flush_tlb_mm_slow:
110 wrpr %g1, PSTATE_IE, %pstate
111 stxa %o0, [%o1] ASI_DMMU
112 stxa %g0, [%g3] ASI_DMMU_DEMAP
113 stxa %g0, [%g3] ASI_IMMU_DEMAP
115 stxa %g2, [%o1] ASI_DMMU
116 sethi %hi(KERNBASE), %o1
122 * The following code flushes one page_size worth.
124 .section .kprobes.text, "ax"
126 .globl __flush_icache_page
127 __flush_icache_page: /* %o0 = phys_page */
128 srlx %o0, PAGE_SHIFT, %o0
129 sethi %uhi(PAGE_OFFSET), %g1
130 sllx %o0, PAGE_SHIFT, %o0
131 sethi %hi(PAGE_SIZE), %g2
134 1: subcc %g2, 32, %g2
140 #ifdef DCACHE_ALIASING_POSSIBLE
142 #if (PAGE_SHIFT != 13)
143 #error only page shift of 13 is supported by dcache flush
146 #define DTAG_MASK 0x3
148 /* This routine is Spitfire specific so the hardcoded
149 * D-cache size and line-size are OK.
152 .globl __flush_dcache_page
153 __flush_dcache_page: /* %o0=kaddr, %o1=flush_icache */
154 sethi %uhi(PAGE_OFFSET), %g1
156 sub %o0, %g1, %o0 ! physical address
157 srlx %o0, 11, %o0 ! make D-cache TAG
158 sethi %hi(1 << 14), %o2 ! D-cache size
159 sub %o2, (1 << 5), %o2 ! D-cache line size
160 1: ldxa [%o2] ASI_DCACHE_TAG, %o3 ! load D-cache TAG
161 andcc %o3, DTAG_MASK, %g0 ! Valid?
162 be,pn %xcc, 2f ! Nope, branch
163 andn %o3, DTAG_MASK, %o3 ! Clear valid bits
164 cmp %o3, %o0 ! TAG match?
165 bne,pt %xcc, 2f ! Nope, branch
167 stxa %g0, [%o2] ASI_DCACHE_TAG ! Invalidate TAG
170 sub %o2, (1 << 5), %o2 ! D-cache line size
172 /* The I-cache does not snoop local stores so we
173 * better flush that too when necessary.
175 brnz,pt %o1, __flush_icache_page
180 #endif /* DCACHE_ALIASING_POSSIBLE */
184 /* Cheetah specific versions, patched at boot time. */
185 __cheetah_flush_tlb_mm: /* 19 insns */
187 andn %g7, PSTATE_IE, %g2
188 wrpr %g2, 0x0, %pstate
190 mov PRIMARY_CONTEXT, %o2
192 ldxa [%o2] ASI_DMMU, %g2
193 srlx %g2, CTX_PGSZ1_NUC_SHIFT, %o1
194 sllx %o1, CTX_PGSZ1_NUC_SHIFT, %o1
195 or %o0, %o1, %o0 /* Preserve nucleus page size fields */
196 stxa %o0, [%o2] ASI_DMMU
197 stxa %g0, [%g3] ASI_DMMU_DEMAP
198 stxa %g0, [%g3] ASI_IMMU_DEMAP
199 stxa %g2, [%o2] ASI_DMMU
200 sethi %hi(KERNBASE), %o2
204 wrpr %g7, 0x0, %pstate
206 __cheetah_flush_tlb_pending: /* 27 insns */
207 /* %o0 = context, %o1 = nr, %o2 = vaddrs[] */
210 andn %g7, PSTATE_IE, %g2
211 wrpr %g2, 0x0, %pstate
213 mov PRIMARY_CONTEXT, %o4
214 ldxa [%o4] ASI_DMMU, %g2
215 srlx %g2, CTX_PGSZ1_NUC_SHIFT, %o3
216 sllx %o3, CTX_PGSZ1_NUC_SHIFT, %o3
217 or %o0, %o3, %o0 /* Preserve nucleus page size fields */
218 stxa %o0, [%o4] ASI_DMMU
219 1: sub %o1, (1 << 3), %o1
224 stxa %g0, [%o3] ASI_IMMU_DEMAP
225 2: stxa %g0, [%o3] ASI_DMMU_DEMAP
229 stxa %g2, [%o4] ASI_DMMU
230 sethi %hi(KERNBASE), %o4
234 wrpr %g7, 0x0, %pstate
236 #ifdef DCACHE_ALIASING_POSSIBLE
237 __cheetah_flush_dcache_page: /* 11 insns */
238 sethi %uhi(PAGE_OFFSET), %g1
241 sethi %hi(PAGE_SIZE), %o4
242 1: subcc %o4, (1 << 5), %o4
243 stxa %g0, [%o0 + %o4] ASI_DCACHE_INVALIDATE
247 retl /* I-cache flush never needed on Cheetah, see callers. */
249 #endif /* DCACHE_ALIASING_POSSIBLE */
251 /* Hypervisor specific versions, patched at boot time. */
252 __hypervisor_tlb_tl0_error:
255 call hypervisor_tlbop_error
260 __hypervisor_flush_tlb_mm: /* 10 insns */
261 mov %o0, %o2 /* ARG2: mmu context */
262 mov 0, %o0 /* ARG0: CPU lists unimplemented */
263 mov 0, %o1 /* ARG1: CPU lists unimplemented */
264 mov HV_MMU_ALL, %o3 /* ARG3: flags */
265 mov HV_FAST_MMU_DEMAP_CTX, %o5
267 brnz,pn %o0, __hypervisor_tlb_tl0_error
268 mov HV_FAST_MMU_DEMAP_CTX, %o1
272 __hypervisor_flush_tlb_pending: /* 16 insns */
273 /* %o0 = context, %o1 = nr, %o2 = vaddrs[] */
277 1: sub %g1, (1 << 3), %g1
278 ldx [%g2 + %g1], %o0 /* ARG0: vaddr + IMMU-bit */
279 mov %g3, %o1 /* ARG1: mmu context */
280 mov HV_MMU_ALL, %o2 /* ARG2: flags */
281 srlx %o0, PAGE_SHIFT, %o0
282 sllx %o0, PAGE_SHIFT, %o0
283 ta HV_MMU_UNMAP_ADDR_TRAP
284 brnz,pn %o0, __hypervisor_tlb_tl0_error
285 mov HV_MMU_UNMAP_ADDR_TRAP, %o1
291 __hypervisor_flush_tlb_kernel_range: /* 16 insns */
292 /* %o0=start, %o1=end */
295 sethi %hi(PAGE_SIZE), %g3
299 1: add %g1, %g2, %o0 /* ARG0: virtual address */
300 mov 0, %o1 /* ARG1: mmu context */
301 mov HV_MMU_ALL, %o2 /* ARG2: flags */
302 ta HV_MMU_UNMAP_ADDR_TRAP
303 brnz,pn %o0, __hypervisor_tlb_tl0_error
304 mov HV_MMU_UNMAP_ADDR_TRAP, %o1
310 #ifdef DCACHE_ALIASING_POSSIBLE
311 /* XXX Niagara and friends have an 8K cache, so no aliasing is
312 * XXX possible, but nothing explicit in the Hypervisor API
313 * XXX guarantees this.
315 __hypervisor_flush_dcache_page: /* 2 insns */
331 .globl cheetah_patch_cachetlbops
332 cheetah_patch_cachetlbops:
335 sethi %hi(__flush_tlb_mm), %o0
336 or %o0, %lo(__flush_tlb_mm), %o0
337 sethi %hi(__cheetah_flush_tlb_mm), %o1
338 or %o1, %lo(__cheetah_flush_tlb_mm), %o1
342 sethi %hi(__flush_tlb_pending), %o0
343 or %o0, %lo(__flush_tlb_pending), %o0
344 sethi %hi(__cheetah_flush_tlb_pending), %o1
345 or %o1, %lo(__cheetah_flush_tlb_pending), %o1
349 #ifdef DCACHE_ALIASING_POSSIBLE
350 sethi %hi(__flush_dcache_page), %o0
351 or %o0, %lo(__flush_dcache_page), %o0
352 sethi %hi(__cheetah_flush_dcache_page), %o1
353 or %o1, %lo(__cheetah_flush_dcache_page), %o1
356 #endif /* DCACHE_ALIASING_POSSIBLE */
362 /* These are all called by the slaves of a cross call, at
363 * trap level 1, with interrupts fully disabled.
366 * %g5 mm->context (all tlb flushes)
367 * %g1 address arg 1 (tlb page and range flushes)
368 * %g7 address arg 2 (tlb range flush only)
376 .globl xcall_flush_tlb_mm
377 xcall_flush_tlb_mm: /* 21 insns */
378 mov PRIMARY_CONTEXT, %g2
379 ldxa [%g2] ASI_DMMU, %g3
380 srlx %g3, CTX_PGSZ1_NUC_SHIFT, %g4
381 sllx %g4, CTX_PGSZ1_NUC_SHIFT, %g4
382 or %g5, %g4, %g5 /* Preserve nucleus page size fields */
383 stxa %g5, [%g2] ASI_DMMU
385 stxa %g0, [%g4] ASI_DMMU_DEMAP
386 stxa %g0, [%g4] ASI_IMMU_DEMAP
387 stxa %g3, [%g2] ASI_DMMU
400 .globl xcall_flush_tlb_pending
401 xcall_flush_tlb_pending: /* 21 insns */
402 /* %g5=context, %g1=nr, %g7=vaddrs[] */
404 mov PRIMARY_CONTEXT, %g4
405 ldxa [%g4] ASI_DMMU, %g2
406 srlx %g2, CTX_PGSZ1_NUC_SHIFT, %g4
407 sllx %g4, CTX_PGSZ1_NUC_SHIFT, %g4
409 mov PRIMARY_CONTEXT, %g4
410 stxa %g5, [%g4] ASI_DMMU
411 1: sub %g1, (1 << 3), %g1
417 stxa %g0, [%g5] ASI_IMMU_DEMAP
418 2: stxa %g0, [%g5] ASI_DMMU_DEMAP
422 stxa %g2, [%g4] ASI_DMMU
426 .globl xcall_flush_tlb_kernel_range
427 xcall_flush_tlb_kernel_range: /* 25 insns */
428 sethi %hi(PAGE_SIZE - 1), %g2
429 or %g2, %lo(PAGE_SIZE - 1), %g2
435 or %g1, 0x20, %g1 ! Nucleus
436 1: stxa %g0, [%g1 + %g3] ASI_DMMU_DEMAP
437 stxa %g0, [%g1 + %g3] ASI_IMMU_DEMAP
454 /* This runs in a very controlled environment, so we do
455 * not need to worry about BH races etc.
457 .globl xcall_sync_tick
460 661: rdpr %pstate, %g2
461 wrpr %g2, PSTATE_IG | PSTATE_AG, %pstate
462 .section .sun4v_2insn_patch, "ax"
469 wrpr %g0, PIL_NORMAL_MAX, %pil
472 109: or %g7, %lo(109b), %g7
473 #ifdef CONFIG_TRACE_IRQFLAGS
474 call trace_hardirqs_off
477 call smp_synchronize_tick_client
480 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
482 .globl xcall_fetch_glob_regs
483 xcall_fetch_glob_regs:
484 sethi %hi(global_cpu_snapshot), %g1
485 or %g1, %lo(global_cpu_snapshot), %g1
490 stx %g7, [%g1 + GR_SNAP_TSTATE]
492 stx %g7, [%g1 + GR_SNAP_TPC]
494 stx %g7, [%g1 + GR_SNAP_TNPC]
495 stx %o7, [%g1 + GR_SNAP_O7]
496 stx %i7, [%g1 + GR_SNAP_I7]
497 /* Don't try this at home kids... */
503 stx %g7, [%g1 + GR_SNAP_RPC]
504 sethi %hi(trap_block), %g7
505 or %g7, %lo(trap_block), %g7
506 sllx %g2, TRAP_BLOCK_SZ_SHIFT, %g2
508 ldx [%g7 + TRAP_PER_CPU_THREAD], %g3
509 stx %g3, [%g1 + GR_SNAP_THREAD]
512 .globl xcall_fetch_glob_pmu
513 xcall_fetch_glob_pmu:
514 sethi %hi(global_cpu_snapshot), %g1
515 or %g1, %lo(global_cpu_snapshot), %g1
520 stx %g7, [%g1 + (4 * 8)]
522 stx %g7, [%g1 + (0 * 8)]
525 .globl xcall_fetch_glob_pmu_n4
526 xcall_fetch_glob_pmu_n4:
527 sethi %hi(global_cpu_snapshot), %g1
528 or %g1, %lo(global_cpu_snapshot), %g1
533 ldxa [%g0] ASI_PIC, %g7
534 stx %g7, [%g1 + (4 * 8)]
536 ldxa [%g3] ASI_PIC, %g7
537 stx %g7, [%g1 + (5 * 8)]
539 ldxa [%g3] ASI_PIC, %g7
540 stx %g7, [%g1 + (6 * 8)]
542 ldxa [%g3] ASI_PIC, %g7
543 stx %g7, [%g1 + (7 * 8)]
549 mov HV_FAST_VT_GET_PERFREG, %o5
552 stx %o1, [%g1 + (3 * 8)]
553 mov HV_FAST_VT_GET_PERFREG, %o5
556 stx %o1, [%g1 + (2 * 8)]
557 mov HV_FAST_VT_GET_PERFREG, %o5
560 stx %o1, [%g1 + (1 * 8)]
561 mov HV_FAST_VT_GET_PERFREG, %o5
564 stx %o1, [%g1 + (0 * 8)]
572 #ifdef DCACHE_ALIASING_POSSIBLE
574 .globl xcall_flush_dcache_page_cheetah
575 xcall_flush_dcache_page_cheetah: /* %g1 == physical page address */
576 sethi %hi(PAGE_SIZE), %g3
577 1: subcc %g3, (1 << 5), %g3
578 stxa %g0, [%g1 + %g3] ASI_DCACHE_INVALIDATE
584 #endif /* DCACHE_ALIASING_POSSIBLE */
586 .globl xcall_flush_dcache_page_spitfire
587 xcall_flush_dcache_page_spitfire: /* %g1 == physical page address
588 %g7 == kernel page virtual address
589 %g5 == (page->mapping != NULL) */
590 #ifdef DCACHE_ALIASING_POSSIBLE
591 srlx %g1, (13 - 2), %g1 ! Form tag comparitor
592 sethi %hi(L1DCACHE_SIZE), %g3 ! D$ size == 16K
593 sub %g3, (1 << 5), %g3 ! D$ linesize == 32
594 1: ldxa [%g3] ASI_DCACHE_TAG, %g2
602 stxa %g0, [%g3] ASI_DCACHE_TAG
606 sub %g3, (1 << 5), %g3
609 #endif /* DCACHE_ALIASING_POSSIBLE */
610 sethi %hi(PAGE_SIZE), %g3
613 subcc %g3, (1 << 5), %g3
615 add %g7, (1 << 5), %g7
624 __hypervisor_tlb_xcall_error:
630 call hypervisor_tlbop_error_xcall
634 .globl __hypervisor_xcall_flush_tlb_mm
635 __hypervisor_xcall_flush_tlb_mm: /* 21 insns */
636 /* %g5=ctx, g1,g2,g3,g4,g7=scratch, %g6=unusable */
642 clr %o0 /* ARG0: CPU lists unimplemented */
643 clr %o1 /* ARG1: CPU lists unimplemented */
644 mov %g5, %o2 /* ARG2: mmu context */
645 mov HV_MMU_ALL, %o3 /* ARG3: flags */
646 mov HV_FAST_MMU_DEMAP_CTX, %o5
648 mov HV_FAST_MMU_DEMAP_CTX, %g6
649 brnz,pn %o0, __hypervisor_tlb_xcall_error
659 .globl __hypervisor_xcall_flush_tlb_pending
660 __hypervisor_xcall_flush_tlb_pending: /* 21 insns */
661 /* %g5=ctx, %g1=nr, %g7=vaddrs[], %g2,%g3,%g4,g6=scratch */
666 1: sub %g1, (1 << 3), %g1
667 ldx [%g7 + %g1], %o0 /* ARG0: virtual address */
668 mov %g5, %o1 /* ARG1: mmu context */
669 mov HV_MMU_ALL, %o2 /* ARG2: flags */
670 srlx %o0, PAGE_SHIFT, %o0
671 sllx %o0, PAGE_SHIFT, %o0
672 ta HV_MMU_UNMAP_ADDR_TRAP
673 mov HV_MMU_UNMAP_ADDR_TRAP, %g6
674 brnz,a,pn %o0, __hypervisor_tlb_xcall_error
684 .globl __hypervisor_xcall_flush_tlb_kernel_range
685 __hypervisor_xcall_flush_tlb_kernel_range: /* 25 insns */
686 /* %g1=start, %g7=end, g2,g3,g4,g5,g6=scratch */
687 sethi %hi(PAGE_SIZE - 1), %g2
688 or %g2, %lo(PAGE_SIZE - 1), %g2
697 1: add %g1, %g3, %o0 /* ARG0: virtual address */
698 mov 0, %o1 /* ARG1: mmu context */
699 mov HV_MMU_ALL, %o2 /* ARG2: flags */
700 ta HV_MMU_UNMAP_ADDR_TRAP
701 mov HV_MMU_UNMAP_ADDR_TRAP, %g6
702 brnz,pn %o0, __hypervisor_tlb_xcall_error
704 sethi %hi(PAGE_SIZE), %o2
713 /* These just get rescheduled to PIL vectors. */
714 .globl xcall_call_function
716 wr %g0, (1 << PIL_SMP_CALL_FUNC), %set_softint
719 .globl xcall_call_function_single
720 xcall_call_function_single:
721 wr %g0, (1 << PIL_SMP_CALL_FUNC_SNGL), %set_softint
724 .globl xcall_receive_signal
725 xcall_receive_signal:
726 wr %g0, (1 << PIL_SMP_RECEIVE_SIGNAL), %set_softint
731 wr %g0, (1 << PIL_SMP_CAPTURE), %set_softint
734 .globl xcall_new_mmu_context_version
735 xcall_new_mmu_context_version:
736 wr %g0, (1 << PIL_SMP_CTX_NEW_VERSION), %set_softint
740 .globl xcall_kgdb_capture
742 wr %g0, (1 << PIL_KGDB_CAPTURE), %set_softint
746 #endif /* CONFIG_SMP */
749 .globl hypervisor_patch_cachetlbops
750 hypervisor_patch_cachetlbops:
753 sethi %hi(__flush_tlb_mm), %o0
754 or %o0, %lo(__flush_tlb_mm), %o0
755 sethi %hi(__hypervisor_flush_tlb_mm), %o1
756 or %o1, %lo(__hypervisor_flush_tlb_mm), %o1
760 sethi %hi(__flush_tlb_pending), %o0
761 or %o0, %lo(__flush_tlb_pending), %o0
762 sethi %hi(__hypervisor_flush_tlb_pending), %o1
763 or %o1, %lo(__hypervisor_flush_tlb_pending), %o1
767 sethi %hi(__flush_tlb_kernel_range), %o0
768 or %o0, %lo(__flush_tlb_kernel_range), %o0
769 sethi %hi(__hypervisor_flush_tlb_kernel_range), %o1
770 or %o1, %lo(__hypervisor_flush_tlb_kernel_range), %o1
774 #ifdef DCACHE_ALIASING_POSSIBLE
775 sethi %hi(__flush_dcache_page), %o0
776 or %o0, %lo(__flush_dcache_page), %o0
777 sethi %hi(__hypervisor_flush_dcache_page), %o1
778 or %o1, %lo(__hypervisor_flush_dcache_page), %o1
781 #endif /* DCACHE_ALIASING_POSSIBLE */
784 sethi %hi(xcall_flush_tlb_mm), %o0
785 or %o0, %lo(xcall_flush_tlb_mm), %o0
786 sethi %hi(__hypervisor_xcall_flush_tlb_mm), %o1
787 or %o1, %lo(__hypervisor_xcall_flush_tlb_mm), %o1
791 sethi %hi(xcall_flush_tlb_pending), %o0
792 or %o0, %lo(xcall_flush_tlb_pending), %o0
793 sethi %hi(__hypervisor_xcall_flush_tlb_pending), %o1
794 or %o1, %lo(__hypervisor_xcall_flush_tlb_pending), %o1
798 sethi %hi(xcall_flush_tlb_kernel_range), %o0
799 or %o0, %lo(xcall_flush_tlb_kernel_range), %o0
800 sethi %hi(__hypervisor_xcall_flush_tlb_kernel_range), %o1
801 or %o1, %lo(__hypervisor_xcall_flush_tlb_kernel_range), %o1
804 #endif /* CONFIG_SMP */