1 /* $Id: irq.c,v 1.114 2002/01/11 08:45:38 davem Exp $
2 * irq.c: UltraSparc IRQ handling/init/registry.
4 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
6 * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
9 #include <linux/config.h>
10 #include <linux/module.h>
11 #include <linux/sched.h>
12 #include <linux/ptrace.h>
13 #include <linux/errno.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/signal.h>
17 #include <linux/interrupt.h>
18 #include <linux/slab.h>
19 #include <linux/random.h>
20 #include <linux/init.h>
21 #include <linux/delay.h>
22 #include <linux/proc_fs.h>
23 #include <linux/seq_file.h>
24 #include <linux/bootmem.h>
25 #include <linux/irq.h>
27 #include <asm/ptrace.h>
28 #include <asm/processor.h>
29 #include <asm/atomic.h>
30 #include <asm/system.h>
34 #include <asm/iommu.h>
36 #include <asm/oplib.h>
38 #include <asm/timer.h>
40 #include <asm/starfire.h>
41 #include <asm/uaccess.h>
42 #include <asm/cache.h>
43 #include <asm/cpudata.h>
44 #include <asm/auxio.h>
47 /* UPA nodes send interrupt packet to UltraSparc with first data reg
48 * value low 5 (7 on Starfire) bits holding the IRQ identifier being
49 * delivered. We must translate this into a non-vector IRQ so we can
50 * set the softint on this cpu.
52 * To make processing these packets efficient and race free we use
53 * an array of irq buckets below. The interrupt vector handler in
54 * entry.S feeds incoming packets into per-cpu pil-indexed lists.
55 * The IVEC handler does not need to act atomically, the PIL dispatch
56 * code uses CAS to get an atomic snapshot of the list and clear it
59 * If you make changes to ino_bucket, please update hand coded assembler
60 * of the vectored interrupt trap handler(s) in entry.S and sun4v_ivec.S
63 /* Next handler in per-CPU IRQ worklist. We know that
64 * bucket pointers have the high 32-bits clear, so to
65 * save space we only store the bits we need.
67 /*0x00*/unsigned int irq_chain
;
69 /* Virtual interrupt number assigned to this INO. */
70 /*0x04*/unsigned int virt_irq
;
73 #define NUM_IVECS (IMAP_INR + 1)
74 struct ino_bucket ivector_table
[NUM_IVECS
] __attribute__ ((aligned (SMP_CACHE_BYTES
)));
76 #define __irq_ino(irq) \
77 (((struct ino_bucket *)(unsigned long)(irq)) - &ivector_table[0])
78 #define __bucket(irq) ((struct ino_bucket *)(unsigned long)(irq))
79 #define __irq(bucket) ((unsigned int)(unsigned long)(bucket))
81 /* This has to be in the main kernel image, it cannot be
82 * turned into per-cpu data. The reason is that the main
83 * kernel image is locked into the TLB and this structure
84 * is accessed from the vectored interrupt trap handler. If
85 * access to this structure takes a TLB miss it could cause
86 * the 5-level sparc v9 trap stack to overflow.
88 #define irq_work(__cpu) &(trap_block[(__cpu)].irq_worklist)
90 static unsigned int virt_to_real_irq_table
[NR_IRQS
];
91 static unsigned char virt_irq_cur
= 1;
93 static unsigned char virt_irq_alloc(unsigned int real_irq
)
97 BUILD_BUG_ON(NR_IRQS
>= 256);
100 if (ent
>= NR_IRQS
) {
101 printk(KERN_ERR
"IRQ: Out of virtual IRQs.\n");
105 virt_irq_cur
= ent
+ 1;
106 virt_to_real_irq_table
[ent
] = real_irq
;
111 #if 0 /* Currently unused. */
112 static unsigned char real_to_virt_irq(unsigned int real_irq
)
114 struct ino_bucket
*bucket
= __bucket(real_irq
);
116 return bucket
->virt_irq
;
120 static unsigned int virt_to_real_irq(unsigned char virt_irq
)
122 return virt_to_real_irq_table
[virt_irq
];
126 * /proc/interrupts printing:
129 int show_interrupts(struct seq_file
*p
, void *v
)
131 int i
= *(loff_t
*) v
, j
;
132 struct irqaction
* action
;
137 for_each_online_cpu(j
)
138 seq_printf(p
, "CPU%d ",j
);
143 spin_lock_irqsave(&irq_desc
[i
].lock
, flags
);
144 action
= irq_desc
[i
].action
;
147 seq_printf(p
, "%3d: ",i
);
149 seq_printf(p
, "%10u ", kstat_irqs(i
));
151 for_each_online_cpu(j
)
152 seq_printf(p
, "%10u ", kstat_cpu(j
).irqs
[i
]);
154 seq_printf(p
, " %9s", irq_desc
[i
].chip
->typename
);
155 seq_printf(p
, " %s", action
->name
);
157 for (action
=action
->next
; action
; action
= action
->next
)
158 seq_printf(p
, ", %s", action
->name
);
162 spin_unlock_irqrestore(&irq_desc
[i
].lock
, flags
);
167 extern unsigned long real_hard_smp_processor_id(void);
169 static unsigned int sun4u_compute_tid(unsigned long imap
, unsigned long cpuid
)
173 if (this_is_starfire
) {
174 tid
= starfire_translate(imap
, cpuid
);
175 tid
<<= IMAP_TID_SHIFT
;
178 if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
181 __asm__ ("rdpr %%ver, %0" : "=r" (ver
));
182 if ((ver
>> 32UL) == __JALAPENO_ID
||
183 (ver
>> 32UL) == __SERRANO_ID
) {
184 tid
= cpuid
<< IMAP_TID_SHIFT
;
185 tid
&= IMAP_TID_JBUS
;
187 unsigned int a
= cpuid
& 0x1f;
188 unsigned int n
= (cpuid
>> 5) & 0x1f;
190 tid
= ((a
<< IMAP_AID_SHIFT
) |
191 (n
<< IMAP_NID_SHIFT
));
192 tid
&= (IMAP_AID_SAFARI
|
196 tid
= cpuid
<< IMAP_TID_SHIFT
;
204 struct irq_handler_data
{
208 void (*pre_handler
)(unsigned int, void *, void *);
209 void *pre_handler_arg1
;
210 void *pre_handler_arg2
;
213 static inline struct ino_bucket
*virt_irq_to_bucket(unsigned int virt_irq
)
215 unsigned int real_irq
= virt_to_real_irq(virt_irq
);
216 struct ino_bucket
*bucket
= NULL
;
218 if (likely(real_irq
))
219 bucket
= __bucket(real_irq
);
225 static int irq_choose_cpu(unsigned int virt_irq
)
227 cpumask_t mask
= irq_desc
[virt_irq
].affinity
;
230 if (cpus_equal(mask
, CPU_MASK_ALL
)) {
231 static int irq_rover
;
232 static DEFINE_SPINLOCK(irq_rover_lock
);
235 /* Round-robin distribution... */
237 spin_lock_irqsave(&irq_rover_lock
, flags
);
239 while (!cpu_online(irq_rover
)) {
240 if (++irq_rover
>= NR_CPUS
)
245 if (++irq_rover
>= NR_CPUS
)
247 } while (!cpu_online(irq_rover
));
249 spin_unlock_irqrestore(&irq_rover_lock
, flags
);
253 cpus_and(tmp
, cpu_online_map
, mask
);
258 cpuid
= first_cpu(tmp
);
264 static int irq_choose_cpu(unsigned int virt_irq
)
266 return real_hard_smp_processor_id();
270 static void sun4u_irq_enable(unsigned int virt_irq
)
272 irq_desc_t
*desc
= irq_desc
+ virt_irq
;
273 struct irq_handler_data
*data
= desc
->handler_data
;
276 unsigned long cpuid
, imap
;
279 cpuid
= irq_choose_cpu(virt_irq
);
282 tid
= sun4u_compute_tid(imap
, cpuid
);
284 upa_writel(tid
| IMAP_VALID
, imap
);
288 static void sun4u_irq_disable(unsigned int virt_irq
)
290 irq_desc_t
*desc
= irq_desc
+ virt_irq
;
291 struct irq_handler_data
*data
= desc
->handler_data
;
294 unsigned long imap
= data
->imap
;
295 u32 tmp
= upa_readl(imap
);
298 upa_writel(tmp
, imap
);
302 static void sun4u_irq_end(unsigned int virt_irq
)
304 irq_desc_t
*desc
= irq_desc
+ virt_irq
;
305 struct irq_handler_data
*data
= desc
->handler_data
;
308 upa_writel(ICLR_IDLE
, data
->iclr
);
311 static void sun4v_irq_enable(unsigned int virt_irq
)
313 struct ino_bucket
*bucket
= virt_irq_to_bucket(virt_irq
);
314 unsigned int ino
= bucket
- &ivector_table
[0];
316 if (likely(bucket
)) {
320 cpuid
= irq_choose_cpu(virt_irq
);
322 err
= sun4v_intr_settarget(ino
, cpuid
);
324 printk("sun4v_intr_settarget(%x,%lu): err(%d)\n",
326 err
= sun4v_intr_setenabled(ino
, HV_INTR_ENABLED
);
328 printk("sun4v_intr_setenabled(%x): err(%d)\n",
333 static void sun4v_irq_disable(unsigned int virt_irq
)
335 struct ino_bucket
*bucket
= virt_irq_to_bucket(virt_irq
);
336 unsigned int ino
= bucket
- &ivector_table
[0];
338 if (likely(bucket
)) {
341 err
= sun4v_intr_setenabled(ino
, HV_INTR_DISABLED
);
343 printk("sun4v_intr_setenabled(%x): "
344 "err(%d)\n", ino
, err
);
348 static void sun4v_irq_end(unsigned int virt_irq
)
350 struct ino_bucket
*bucket
= virt_irq_to_bucket(virt_irq
);
351 unsigned int ino
= bucket
- &ivector_table
[0];
353 if (likely(bucket
)) {
356 err
= sun4v_intr_setstate(ino
, HV_INTR_STATE_IDLE
);
358 printk("sun4v_intr_setstate(%x): "
359 "err(%d)\n", ino
, err
);
363 static void run_pre_handler(unsigned int virt_irq
)
365 struct ino_bucket
*bucket
= virt_irq_to_bucket(virt_irq
);
366 irq_desc_t
*desc
= irq_desc
+ virt_irq
;
367 struct irq_handler_data
*data
= desc
->handler_data
;
369 if (likely(data
->pre_handler
)) {
370 data
->pre_handler(__irq_ino(__irq(bucket
)),
371 data
->pre_handler_arg1
,
372 data
->pre_handler_arg2
);
376 static struct hw_interrupt_type sun4u_irq
= {
378 .enable
= sun4u_irq_enable
,
379 .disable
= sun4u_irq_disable
,
380 .end
= sun4u_irq_end
,
383 static struct hw_interrupt_type sun4u_irq_ack
= {
384 .typename
= "sun4u+ack",
385 .enable
= sun4u_irq_enable
,
386 .disable
= sun4u_irq_disable
,
387 .ack
= run_pre_handler
,
388 .end
= sun4u_irq_end
,
391 static struct hw_interrupt_type sun4v_irq
= {
393 .enable
= sun4v_irq_enable
,
394 .disable
= sun4v_irq_disable
,
395 .end
= sun4v_irq_end
,
398 static struct hw_interrupt_type sun4v_irq_ack
= {
399 .typename
= "sun4v+ack",
400 .enable
= sun4v_irq_enable
,
401 .disable
= sun4v_irq_disable
,
402 .ack
= run_pre_handler
,
403 .end
= sun4v_irq_end
,
406 void irq_install_pre_handler(int virt_irq
,
407 void (*func
)(unsigned int, void *, void *),
408 void *arg1
, void *arg2
)
410 irq_desc_t
*desc
= irq_desc
+ virt_irq
;
411 struct irq_handler_data
*data
= desc
->handler_data
;
413 data
->pre_handler
= func
;
414 data
->pre_handler_arg1
= arg1
;
415 data
->pre_handler_arg2
= arg2
;
417 desc
->chip
= (desc
->chip
== &sun4u_irq
?
418 &sun4u_irq_ack
: &sun4v_irq_ack
);
421 unsigned int build_irq(int inofixup
, unsigned long iclr
, unsigned long imap
)
423 struct ino_bucket
*bucket
;
424 struct irq_handler_data
*data
;
428 BUG_ON(tlb_type
== hypervisor
);
430 ino
= (upa_readl(imap
) & (IMAP_IGN
| IMAP_INO
)) + inofixup
;
431 bucket
= &ivector_table
[ino
];
432 if (!bucket
->virt_irq
) {
433 bucket
->virt_irq
= virt_irq_alloc(__irq(bucket
));
434 irq_desc
[bucket
->virt_irq
].chip
= &sun4u_irq
;
437 desc
= irq_desc
+ bucket
->virt_irq
;
438 if (unlikely(desc
->handler_data
))
441 data
= kzalloc(sizeof(struct irq_handler_data
), GFP_ATOMIC
);
442 if (unlikely(!data
)) {
443 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
446 desc
->handler_data
= data
;
452 return bucket
->virt_irq
;
455 unsigned int sun4v_build_irq(u32 devhandle
, unsigned int devino
)
457 struct ino_bucket
*bucket
;
458 struct irq_handler_data
*data
;
459 unsigned long sysino
;
462 BUG_ON(tlb_type
!= hypervisor
);
464 sysino
= sun4v_devino_to_sysino(devhandle
, devino
);
465 bucket
= &ivector_table
[sysino
];
466 if (!bucket
->virt_irq
) {
467 bucket
->virt_irq
= virt_irq_alloc(__irq(bucket
));
468 irq_desc
[bucket
->virt_irq
].chip
= &sun4v_irq
;
471 desc
= irq_desc
+ bucket
->virt_irq
;
472 if (unlikely(desc
->handler_data
))
475 data
= kzalloc(sizeof(struct irq_handler_data
), GFP_ATOMIC
);
476 if (unlikely(!data
)) {
477 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
480 desc
->handler_data
= data
;
482 /* Catch accidental accesses to these things. IMAP/ICLR handling
483 * is done by hypervisor calls on sun4v platforms, not by direct
490 return bucket
->virt_irq
;
493 void hw_resend_irq(struct hw_interrupt_type
*handler
, unsigned int virt_irq
)
495 struct ino_bucket
*bucket
= virt_irq_to_bucket(virt_irq
);
496 unsigned long pstate
;
499 __asm__
__volatile__("rdpr %%pstate, %0" : "=r" (pstate
));
500 __asm__
__volatile__("wrpr %0, %1, %%pstate"
501 : : "r" (pstate
), "i" (PSTATE_IE
));
502 ent
= irq_work(smp_processor_id());
503 bucket
->irq_chain
= *ent
;
504 *ent
= __irq(bucket
);
505 set_softint(1 << PIL_DEVICE_IRQ
);
506 __asm__
__volatile__("wrpr %0, 0x0, %%pstate" : : "r" (pstate
));
509 void ack_bad_irq(unsigned int virt_irq
)
511 struct ino_bucket
*bucket
= virt_irq_to_bucket(virt_irq
);
512 unsigned int ino
= 0xdeadbeef;
515 ino
= bucket
- &ivector_table
[0];
517 printk(KERN_CRIT
"Unexpected IRQ from ino[%x] virt_irq[%u]\n",
522 extern irqreturn_t
timer_interrupt(int, void *, struct pt_regs
*);
524 void timer_irq(int irq
, struct pt_regs
*regs
)
526 unsigned long clr_mask
= 1 << irq
;
527 unsigned long tick_mask
= tick_ops
->softint_mask
;
529 if (get_softint() & tick_mask
) {
531 clr_mask
= tick_mask
;
533 clear_softint(clr_mask
);
537 kstat_this_cpu
.irqs
[0]++;
538 timer_interrupt(irq
, NULL
, regs
);
544 void handler_irq(int irq
, struct pt_regs
*regs
)
546 struct ino_bucket
*bucket
;
548 clear_softint(1 << irq
);
553 bucket
= __bucket(xchg32(irq_work(smp_processor_id()), 0));
555 struct ino_bucket
*next
= __bucket(bucket
->irq_chain
);
557 bucket
->irq_chain
= 0;
558 __do_IRQ(bucket
->virt_irq
, regs
);
573 static struct sun5_timer
*prom_timers
;
574 static u64 prom_limit0
, prom_limit1
;
576 static void map_prom_timers(void)
578 struct device_node
*dp
;
581 /* PROM timer node hangs out in the top level of device siblings... */
582 dp
= of_find_node_by_path("/");
585 if (!strcmp(dp
->name
, "counter-timer"))
590 /* Assume if node is not present, PROM uses different tick mechanism
591 * which we should not care about.
594 prom_timers
= (struct sun5_timer
*) 0;
598 /* If PROM is really using this, it must be mapped by him. */
599 addr
= of_get_property(dp
, "address", NULL
);
601 prom_printf("PROM does not have timer mapped, trying to continue.\n");
602 prom_timers
= (struct sun5_timer
*) 0;
605 prom_timers
= (struct sun5_timer
*) ((unsigned long)addr
[0]);
608 static void kill_prom_timer(void)
613 /* Save them away for later. */
614 prom_limit0
= prom_timers
->limit0
;
615 prom_limit1
= prom_timers
->limit1
;
617 /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14.
618 * We turn both off here just to be paranoid.
620 prom_timers
->limit0
= 0;
621 prom_timers
->limit1
= 0;
623 /* Wheee, eat the interrupt packet too... */
624 __asm__
__volatile__(
626 " ldxa [%%g0] %0, %%g1\n"
627 " ldxa [%%g2] %1, %%g1\n"
628 " stxa %%g0, [%%g0] %0\n"
631 : "i" (ASI_INTR_RECEIVE
), "i" (ASI_INTR_R
)
635 void init_irqwork_curcpu(void)
637 int cpu
= hard_smp_processor_id();
639 trap_block
[cpu
].irq_worklist
= 0;
642 static void __cpuinit
register_one_mondo(unsigned long paddr
, unsigned long type
)
644 unsigned long num_entries
= 128;
645 unsigned long status
;
647 status
= sun4v_cpu_qconf(type
, paddr
, num_entries
);
648 if (status
!= HV_EOK
) {
649 prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, "
650 "err %lu\n", type
, paddr
, num_entries
, status
);
655 static void __cpuinit
sun4v_register_mondo_queues(int this_cpu
)
657 struct trap_per_cpu
*tb
= &trap_block
[this_cpu
];
659 register_one_mondo(tb
->cpu_mondo_pa
, HV_CPU_QUEUE_CPU_MONDO
);
660 register_one_mondo(tb
->dev_mondo_pa
, HV_CPU_QUEUE_DEVICE_MONDO
);
661 register_one_mondo(tb
->resum_mondo_pa
, HV_CPU_QUEUE_RES_ERROR
);
662 register_one_mondo(tb
->nonresum_mondo_pa
, HV_CPU_QUEUE_NONRES_ERROR
);
665 static void __cpuinit
alloc_one_mondo(unsigned long *pa_ptr
, int use_bootmem
)
670 page
= alloc_bootmem_low_pages(PAGE_SIZE
);
672 page
= (void *) get_zeroed_page(GFP_ATOMIC
);
675 prom_printf("SUN4V: Error, cannot allocate mondo queue.\n");
679 *pa_ptr
= __pa(page
);
682 static void __cpuinit
alloc_one_kbuf(unsigned long *pa_ptr
, int use_bootmem
)
687 page
= alloc_bootmem_low_pages(PAGE_SIZE
);
689 page
= (void *) get_zeroed_page(GFP_ATOMIC
);
692 prom_printf("SUN4V: Error, cannot allocate kbuf page.\n");
696 *pa_ptr
= __pa(page
);
699 static void __cpuinit
init_cpu_send_mondo_info(struct trap_per_cpu
*tb
, int use_bootmem
)
704 BUILD_BUG_ON((NR_CPUS
* sizeof(u16
)) > (PAGE_SIZE
- 64));
707 page
= alloc_bootmem_low_pages(PAGE_SIZE
);
709 page
= (void *) get_zeroed_page(GFP_ATOMIC
);
712 prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n");
716 tb
->cpu_mondo_block_pa
= __pa(page
);
717 tb
->cpu_list_pa
= __pa(page
+ 64);
721 /* Allocate and register the mondo and error queues for this cpu. */
722 void __cpuinit
sun4v_init_mondo_queues(int use_bootmem
, int cpu
, int alloc
, int load
)
724 struct trap_per_cpu
*tb
= &trap_block
[cpu
];
727 alloc_one_mondo(&tb
->cpu_mondo_pa
, use_bootmem
);
728 alloc_one_mondo(&tb
->dev_mondo_pa
, use_bootmem
);
729 alloc_one_mondo(&tb
->resum_mondo_pa
, use_bootmem
);
730 alloc_one_kbuf(&tb
->resum_kernel_buf_pa
, use_bootmem
);
731 alloc_one_mondo(&tb
->nonresum_mondo_pa
, use_bootmem
);
732 alloc_one_kbuf(&tb
->nonresum_kernel_buf_pa
, use_bootmem
);
734 init_cpu_send_mondo_info(tb
, use_bootmem
);
738 if (cpu
!= hard_smp_processor_id()) {
739 prom_printf("SUN4V: init mondo on cpu %d not %d\n",
740 cpu
, hard_smp_processor_id());
743 sun4v_register_mondo_queues(cpu
);
747 static struct irqaction timer_irq_action
= {
751 /* Only invoked on boot processor. */
752 void __init
init_IRQ(void)
756 memset(&ivector_table
[0], 0, sizeof(ivector_table
));
758 if (tlb_type
== hypervisor
)
759 sun4v_init_mondo_queues(1, hard_smp_processor_id(), 1, 1);
761 /* We need to clear any IRQ's pending in the soft interrupt
762 * registers, a spurious one could be left around from the
763 * PROM timer which we just disabled.
765 clear_softint(get_softint());
767 /* Now that ivector table is initialized, it is safe
768 * to receive IRQ vector traps. We will normally take
769 * one or two right now, in case some device PROM used
770 * to boot us wants to speak to us. We just ignore them.
772 __asm__
__volatile__("rdpr %%pstate, %%g1\n\t"
773 "or %%g1, %0, %%g1\n\t"
774 "wrpr %%g1, 0x0, %%pstate"
779 irq_desc
[0].action
= &timer_irq_action
;