1 /* $Id: irq.c,v 1.114 2002/01/11 08:45:38 davem Exp $
2 * irq.c: UltraSparc IRQ handling/init/registry.
4 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
6 * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
9 #include <linux/config.h>
10 #include <linux/module.h>
11 #include <linux/sched.h>
12 #include <linux/ptrace.h>
13 #include <linux/errno.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/signal.h>
17 #include <linux/interrupt.h>
18 #include <linux/slab.h>
19 #include <linux/random.h>
20 #include <linux/init.h>
21 #include <linux/delay.h>
22 #include <linux/proc_fs.h>
23 #include <linux/seq_file.h>
24 #include <linux/bootmem.h>
26 #include <asm/ptrace.h>
27 #include <asm/processor.h>
28 #include <asm/atomic.h>
29 #include <asm/system.h>
33 #include <asm/iommu.h>
35 #include <asm/oplib.h>
36 #include <asm/timer.h>
38 #include <asm/starfire.h>
39 #include <asm/uaccess.h>
40 #include <asm/cache.h>
41 #include <asm/cpudata.h>
42 #include <asm/auxio.h>
46 static void distribute_irqs(void);
49 /* UPA nodes send interrupt packet to UltraSparc with first data reg
50 * value low 5 (7 on Starfire) bits holding the IRQ identifier being
51 * delivered. We must translate this into a non-vector IRQ so we can
52 * set the softint on this cpu.
54 * To make processing these packets efficient and race free we use
55 * an array of irq buckets below. The interrupt vector handler in
56 * entry.S feeds incoming packets into per-cpu pil-indexed lists.
57 * The IVEC handler does not need to act atomically, the PIL dispatch
58 * code uses CAS to get an atomic snapshot of the list and clear it
62 struct ino_bucket ivector_table
[NUM_IVECS
] __attribute__ ((aligned (SMP_CACHE_BYTES
)));
64 /* This has to be in the main kernel image, it cannot be
65 * turned into per-cpu data. The reason is that the main
66 * kernel image is locked into the TLB and this structure
67 * is accessed from the vectored interrupt trap handler. If
68 * access to this structure takes a TLB miss it could cause
69 * the 5-level sparc v9 trap stack to overflow.
71 struct irq_work_struct
{
72 unsigned int irq_worklists
[16];
74 struct irq_work_struct __irq_work
[NR_CPUS
];
75 #define irq_work(__cpu, __pil) &(__irq_work[(__cpu)].irq_worklists[(__pil)])
77 static struct irqaction
*irq_action
[NR_IRQS
+1];
79 /* This only synchronizes entities which modify IRQ handler
80 * state and some selected user-level spots that want to
81 * read things in the table. IRQ handler processing orders
82 * its' accesses such that no locking is needed.
84 static DEFINE_SPINLOCK(irq_action_lock
);
86 static void register_irq_proc (unsigned int irq
);
89 * Upper 2b of irqaction->flags holds the ino.
90 * irqaction->mask holds the smp affinity information.
92 #define put_ino_in_irqaction(action, irq) \
93 action->flags &= 0xffffffffffffUL; \
94 if (__bucket(irq) == &pil0_dummy_bucket) \
95 action->flags |= 0xdeadUL << 48; \
97 action->flags |= __irq_ino(irq) << 48;
98 #define get_ino_in_irqaction(action) (action->flags >> 48)
100 #define put_smpaff_in_irqaction(action, smpaff) (action)->mask = (smpaff)
101 #define get_smpaff_in_irqaction(action) ((action)->mask)
103 int show_interrupts(struct seq_file
*p
, void *v
)
106 int i
= *(loff_t
*) v
;
107 struct irqaction
*action
;
112 spin_lock_irqsave(&irq_action_lock
, flags
);
114 if (!(action
= *(i
+ irq_action
)))
116 seq_printf(p
, "%3d: ", i
);
118 seq_printf(p
, "%10u ", kstat_irqs(i
));
120 for_each_online_cpu(j
) {
121 seq_printf(p
, "%10u ",
122 kstat_cpu(j
).irqs
[i
]);
125 seq_printf(p
, " %s:%lx", action
->name
,
126 get_ino_in_irqaction(action
));
127 for (action
= action
->next
; action
; action
= action
->next
) {
128 seq_printf(p
, ", %s:%lx", action
->name
,
129 get_ino_in_irqaction(action
));
134 spin_unlock_irqrestore(&irq_action_lock
, flags
);
139 extern unsigned long real_hard_smp_processor_id(void);
141 static unsigned int sun4u_compute_tid(unsigned long imap
, unsigned long cpuid
)
145 if (this_is_starfire
) {
146 tid
= starfire_translate(imap
, cpuid
);
147 tid
<<= IMAP_TID_SHIFT
;
150 if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
153 __asm__ ("rdpr %%ver, %0" : "=r" (ver
));
154 if ((ver
>> 32UL) == __JALAPENO_ID
||
155 (ver
>> 32UL) == __SERRANO_ID
) {
156 tid
= cpuid
<< IMAP_TID_SHIFT
;
157 tid
&= IMAP_TID_JBUS
;
159 unsigned int a
= cpuid
& 0x1f;
160 unsigned int n
= (cpuid
>> 5) & 0x1f;
162 tid
= ((a
<< IMAP_AID_SHIFT
) |
163 (n
<< IMAP_NID_SHIFT
));
164 tid
&= (IMAP_AID_SAFARI
|
168 tid
= cpuid
<< IMAP_TID_SHIFT
;
176 /* Now these are always passed a true fully specified sun4u INO. */
177 void enable_irq(unsigned int irq
)
179 struct ino_bucket
*bucket
= __bucket(irq
);
180 unsigned long imap
, cpuid
;
188 /* This gets the physical processor ID, even on uniprocessor,
189 * so we can always program the interrupt target correctly.
191 cpuid
= real_hard_smp_processor_id();
193 if (tlb_type
== hypervisor
) {
194 unsigned int ino
= __irq_ino(irq
);
197 err
= sun4v_intr_settarget(ino
, cpuid
);
199 printk("sun4v_intr_settarget(%x,%lu): err(%d)\n",
201 err
= sun4v_intr_setenabled(ino
, HV_INTR_ENABLED
);
203 printk("sun4v_intr_setenabled(%x): err(%d)\n",
206 unsigned int tid
= sun4u_compute_tid(imap
, cpuid
);
208 /* NOTE NOTE NOTE, IGN and INO are read-only, IGN is a product
209 * of this SYSIO's preconfigured IGN in the SYSIO Control
210 * Register, the hardware just mirrors that value here.
211 * However for Graphics and UPA Slave devices the full
212 * IMAP_INR field can be set by the programmer here.
214 * Things like FFB can now be handled via the new IRQ
217 upa_writel(tid
| IMAP_VALID
, imap
);
223 /* This now gets passed true ino's as well. */
224 void disable_irq(unsigned int irq
)
226 struct ino_bucket
*bucket
= __bucket(irq
);
231 if (tlb_type
== hypervisor
) {
232 unsigned int ino
= __irq_ino(irq
);
235 err
= sun4v_intr_setenabled(ino
, HV_INTR_DISABLED
);
237 printk("sun4v_intr_setenabled(%x): "
238 "err(%d)\n", ino
, err
);
242 /* NOTE: We do not want to futz with the IRQ clear registers
243 * and move the state to IDLE, the SCSI code does call
244 * disable_irq() to assure atomicity in the queue cmd
245 * SCSI adapter driver code. Thus we'd lose interrupts.
247 tmp
= upa_readl(imap
);
249 upa_writel(tmp
, imap
);
254 /* The timer is the one "weird" interrupt which is generated by
255 * the CPU %tick register and not by some normal vectored interrupt
256 * source. To handle this special case, we use this dummy INO bucket.
258 static struct irq_desc pil0_dummy_desc
;
259 static struct ino_bucket pil0_dummy_bucket
= {
260 .irq_info
= &pil0_dummy_desc
,
263 static void build_irq_error(const char *msg
, unsigned int ino
, int pil
, int inofixup
,
264 unsigned long iclr
, unsigned long imap
,
265 struct ino_bucket
*bucket
)
267 prom_printf("IRQ: INO %04x (%d:%016lx:%016lx) --> "
268 "(%d:%d:%016lx:%016lx), halting...\n",
269 ino
, bucket
->pil
, bucket
->iclr
, bucket
->imap
,
270 pil
, inofixup
, iclr
, imap
);
274 unsigned int build_irq(int pil
, int inofixup
, unsigned long iclr
, unsigned long imap
)
276 struct ino_bucket
*bucket
;
280 if (iclr
!= 0UL || imap
!= 0UL) {
281 prom_printf("Invalid dummy bucket for PIL0 (%lx:%lx)\n",
285 return __irq(&pil0_dummy_bucket
);
288 BUG_ON(tlb_type
== hypervisor
);
290 /* RULE: Both must be specified in all other cases. */
291 if (iclr
== 0UL || imap
== 0UL) {
292 prom_printf("Invalid build_irq %d %d %016lx %016lx\n",
293 pil
, inofixup
, iclr
, imap
);
297 ino
= (upa_readl(imap
) & (IMAP_IGN
| IMAP_INO
)) + inofixup
;
298 if (ino
> NUM_IVECS
) {
299 prom_printf("Invalid INO %04x (%d:%d:%016lx:%016lx)\n",
300 ino
, pil
, inofixup
, iclr
, imap
);
304 bucket
= &ivector_table
[ino
];
305 if (bucket
->flags
& IBF_ACTIVE
)
306 build_irq_error("IRQ: Trying to build active INO bucket.\n",
307 ino
, pil
, inofixup
, iclr
, imap
, bucket
);
309 if (bucket
->irq_info
) {
310 if (bucket
->imap
!= imap
|| bucket
->iclr
!= iclr
)
311 build_irq_error("IRQ: Trying to reinit INO bucket.\n",
312 ino
, pil
, inofixup
, iclr
, imap
, bucket
);
317 bucket
->irq_info
= kzalloc(sizeof(struct irq_desc
), GFP_ATOMIC
);
318 if (!bucket
->irq_info
) {
319 prom_printf("IRQ: Error, kmalloc(irq_desc) failed.\n");
323 /* Ok, looks good, set it up. Don't touch the irq_chain or
332 return __irq(bucket
);
335 unsigned int sun4v_build_irq(u32 devhandle
, unsigned int devino
, int pil
, unsigned char flags
)
337 struct ino_bucket
*bucket
;
338 unsigned long sysino
;
340 sysino
= sun4v_devino_to_sysino(devhandle
, devino
);
342 bucket
= &ivector_table
[sysino
];
344 /* Catch accidental accesses to these things. IMAP/ICLR handling
345 * is done by hypervisor calls on sun4v platforms, not by direct
348 * But we need to make them look unique for the disable_irq() logic
351 bucket
->imap
= ~0UL - sysino
;
352 bucket
->iclr
= ~0UL - sysino
;
355 bucket
->flags
= flags
;
357 bucket
->irq_info
= kzalloc(sizeof(struct irq_desc
), GFP_ATOMIC
);
358 if (!bucket
->irq_info
) {
359 prom_printf("IRQ: Error, kmalloc(irq_desc) failed.\n");
363 return __irq(bucket
);
366 static void atomic_bucket_insert(struct ino_bucket
*bucket
)
368 unsigned long pstate
;
371 __asm__
__volatile__("rdpr %%pstate, %0" : "=r" (pstate
));
372 __asm__
__volatile__("wrpr %0, %1, %%pstate"
373 : : "r" (pstate
), "i" (PSTATE_IE
));
374 ent
= irq_work(smp_processor_id(), bucket
->pil
);
375 bucket
->irq_chain
= *ent
;
376 *ent
= __irq(bucket
);
377 __asm__
__volatile__("wrpr %0, 0x0, %%pstate" : : "r" (pstate
));
380 static int check_irq_sharing(int pil
, unsigned long irqflags
)
382 struct irqaction
*action
, *tmp
;
384 action
= *(irq_action
+ pil
);
386 if ((action
->flags
& SA_SHIRQ
) && (irqflags
& SA_SHIRQ
)) {
387 for (tmp
= action
; tmp
->next
; tmp
= tmp
->next
)
396 static void append_irq_action(int pil
, struct irqaction
*action
)
398 struct irqaction
**pp
= irq_action
+ pil
;
405 static struct irqaction
*get_action_slot(struct ino_bucket
*bucket
)
407 struct irq_desc
*desc
= bucket
->irq_info
;
411 if (bucket
->flags
& IBF_PCI
)
412 max_irq
= MAX_IRQ_DESC_ACTION
;
413 for (i
= 0; i
< max_irq
; i
++) {
414 struct irqaction
*p
= &desc
->action
[i
];
417 if (desc
->action_active_mask
& mask
)
420 desc
->action_active_mask
|= mask
;
426 int request_irq(unsigned int irq
, irqreturn_t (*handler
)(int, void *, struct pt_regs
*),
427 unsigned long irqflags
, const char *name
, void *dev_id
)
429 struct irqaction
*action
;
430 struct ino_bucket
*bucket
= __bucket(irq
);
434 if (unlikely(!handler
))
437 if (unlikely(!bucket
->irq_info
))
440 if ((bucket
!= &pil0_dummy_bucket
) && (irqflags
& SA_SAMPLE_RANDOM
)) {
442 * This function might sleep, we want to call it first,
443 * outside of the atomic block. In SA_STATIC_ALLOC case,
444 * random driver's kmalloc will fail, but it is safe.
445 * If already initialized, random driver will not reinit.
446 * Yes, this might clear the entropy pool if the wrong
447 * driver is attempted to be loaded, without actually
448 * installing a new handler, but is this really a problem,
449 * only the sysadmin is able to do this.
451 rand_initialize_irq(irq
);
454 spin_lock_irqsave(&irq_action_lock
, flags
);
456 if (check_irq_sharing(bucket
->pil
, irqflags
)) {
457 spin_unlock_irqrestore(&irq_action_lock
, flags
);
461 action
= get_action_slot(bucket
);
463 spin_unlock_irqrestore(&irq_action_lock
, flags
);
467 bucket
->flags
|= IBF_ACTIVE
;
469 if (bucket
!= &pil0_dummy_bucket
) {
470 pending
= bucket
->pending
;
475 action
->handler
= handler
;
476 action
->flags
= irqflags
;
479 action
->dev_id
= dev_id
;
480 put_ino_in_irqaction(action
, irq
);
481 put_smpaff_in_irqaction(action
, CPU_MASK_NONE
);
483 append_irq_action(bucket
->pil
, action
);
487 /* We ate the IVEC already, this makes sure it does not get lost. */
489 atomic_bucket_insert(bucket
);
490 set_softint(1 << bucket
->pil
);
493 spin_unlock_irqrestore(&irq_action_lock
, flags
);
495 if (bucket
!= &pil0_dummy_bucket
)
496 register_irq_proc(__irq_ino(irq
));
504 EXPORT_SYMBOL(request_irq
);
506 static struct irqaction
*unlink_irq_action(unsigned int irq
, void *dev_id
)
508 struct ino_bucket
*bucket
= __bucket(irq
);
509 struct irqaction
*action
, **pp
;
511 pp
= irq_action
+ bucket
->pil
;
513 if (unlikely(!action
))
516 if (unlikely(!action
->handler
)) {
517 printk("Freeing free IRQ %d\n", bucket
->pil
);
521 while (action
&& action
->dev_id
!= dev_id
) {
532 void free_irq(unsigned int irq
, void *dev_id
)
534 struct irqaction
*action
;
535 struct ino_bucket
*bucket
;
538 spin_lock_irqsave(&irq_action_lock
, flags
);
540 action
= unlink_irq_action(irq
, dev_id
);
542 spin_unlock_irqrestore(&irq_action_lock
, flags
);
544 if (unlikely(!action
))
547 synchronize_irq(irq
);
549 spin_lock_irqsave(&irq_action_lock
, flags
);
551 bucket
= __bucket(irq
);
552 if (bucket
!= &pil0_dummy_bucket
) {
553 struct irq_desc
*desc
= bucket
->irq_info
;
556 for (i
= 0; i
< MAX_IRQ_DESC_ACTION
; i
++) {
557 struct irqaction
*p
= &desc
->action
[i
];
560 desc
->action_active_mask
&= ~(1 << i
);
565 if (!desc
->action_active_mask
) {
566 unsigned long imap
= bucket
->imap
;
568 /* This unique interrupt source is now inactive. */
569 bucket
->flags
&= ~IBF_ACTIVE
;
571 /* See if any other buckets share this bucket's IMAP
572 * and are still active.
574 for (ent
= 0; ent
< NUM_IVECS
; ent
++) {
575 struct ino_bucket
*bp
= &ivector_table
[ent
];
578 (bp
->flags
& IBF_ACTIVE
) != 0)
582 /* Only disable when no other sub-irq levels of
583 * the same IMAP are active.
585 if (ent
== NUM_IVECS
)
590 spin_unlock_irqrestore(&irq_action_lock
, flags
);
593 EXPORT_SYMBOL(free_irq
);
596 void synchronize_irq(unsigned int irq
)
598 struct ino_bucket
*bucket
= __bucket(irq
);
601 /* The following is how I wish I could implement this.
602 * Unfortunately the ICLR registers are read-only, you can
603 * only write ICLR_foo values to them. To get the current
604 * IRQ status you would need to get at the IRQ diag registers
605 * in the PCI/SBUS controller and the layout of those vary
606 * from one controller to the next, sigh... -DaveM
608 unsigned long iclr
= bucket
->iclr
;
611 u32 tmp
= upa_readl(iclr
);
613 if (tmp
== ICLR_TRANSMIT
||
614 tmp
== ICLR_PENDING
) {
621 /* So we have to do this with a INPROGRESS bit just like x86. */
622 while (bucket
->flags
& IBF_INPROGRESS
)
626 #endif /* CONFIG_SMP */
628 static void process_bucket(int irq
, struct ino_bucket
*bp
, struct pt_regs
*regs
)
630 struct irq_desc
*desc
= bp
->irq_info
;
631 unsigned char flags
= bp
->flags
;
635 bp
->flags
|= IBF_INPROGRESS
;
637 if (unlikely(!(flags
& IBF_ACTIVE
))) {
642 if (desc
->pre_handler
)
643 desc
->pre_handler(bp
,
644 desc
->pre_handler_arg1
,
645 desc
->pre_handler_arg2
);
647 action_mask
= desc
->action_active_mask
;
649 for (i
= 0; i
< MAX_IRQ_DESC_ACTION
; i
++) {
650 struct irqaction
*p
= &desc
->action
[i
];
653 if (!(action_mask
& mask
))
656 action_mask
&= ~mask
;
658 if (p
->handler(__irq(bp
), p
->dev_id
, regs
) == IRQ_HANDLED
)
665 if (tlb_type
== hypervisor
) {
666 unsigned int ino
= __irq_ino(bp
);
669 err
= sun4v_intr_setstate(ino
, HV_INTR_STATE_IDLE
);
671 printk("sun4v_intr_setstate(%x): "
672 "err(%d)\n", ino
, err
);
674 upa_writel(ICLR_IDLE
, bp
->iclr
);
677 /* Test and add entropy */
678 if (random
& SA_SAMPLE_RANDOM
)
679 add_interrupt_randomness(irq
);
682 bp
->flags
&= ~IBF_INPROGRESS
;
685 void handler_irq(int irq
, struct pt_regs
*regs
)
687 struct ino_bucket
*bp
;
688 int cpu
= smp_processor_id();
692 * Check for TICK_INT on level 14 softint.
695 unsigned long clr_mask
= 1 << irq
;
696 unsigned long tick_mask
= tick_ops
->softint_mask
;
698 if ((irq
== 14) && (get_softint() & tick_mask
)) {
700 clr_mask
= tick_mask
;
702 clear_softint(clr_mask
);
705 clear_softint(1 << irq
);
709 kstat_this_cpu
.irqs
[irq
]++;
714 __bucket(xchg32(irq_work(cpu
, irq
), 0)) :
717 bp
= __bucket(xchg32(irq_work(cpu
, irq
), 0));
720 struct ino_bucket
*nbp
= __bucket(bp
->irq_chain
);
723 process_bucket(irq
, bp
, regs
);
729 #ifdef CONFIG_BLK_DEV_FD
730 extern irqreturn_t
floppy_interrupt(int, void *, struct pt_regs
*);
732 /* XXX No easy way to include asm/floppy.h XXX */
733 extern unsigned char *pdma_vaddr
;
734 extern unsigned long pdma_size
;
735 extern volatile int doing_pdma
;
736 extern unsigned long fdc_status
;
738 irqreturn_t
sparc_floppy_irq(int irq
, void *dev_cookie
, struct pt_regs
*regs
)
740 if (likely(doing_pdma
)) {
741 void __iomem
*stat
= (void __iomem
*) fdc_status
;
742 unsigned char *vaddr
= pdma_vaddr
;
743 unsigned long size
= pdma_size
;
748 if (unlikely(!(val
& 0x80))) {
753 if (unlikely(!(val
& 0x20))) {
761 *vaddr
++ = readb(stat
+ 1);
763 unsigned char data
= *vaddr
++;
766 writeb(data
, stat
+ 1);
774 /* Send Terminal Count pulse to floppy controller. */
775 val
= readb(auxio_register
);
776 val
|= AUXIO_AUX1_FTCNT
;
777 writeb(val
, auxio_register
);
778 val
&= ~AUXIO_AUX1_FTCNT
;
779 writeb(val
, auxio_register
);
785 return floppy_interrupt(irq
, dev_cookie
, regs
);
787 EXPORT_SYMBOL(sparc_floppy_irq
);
790 /* We really don't need these at all on the Sparc. We only have
791 * stubs here because they are exported to modules.
793 unsigned long probe_irq_on(void)
798 EXPORT_SYMBOL(probe_irq_on
);
800 int probe_irq_off(unsigned long mask
)
805 EXPORT_SYMBOL(probe_irq_off
);
808 static int retarget_one_irq(struct irqaction
*p
, int goal_cpu
)
810 struct ino_bucket
*bucket
= get_ino_in_irqaction(p
) + ivector_table
;
812 while (!cpu_online(goal_cpu
)) {
813 if (++goal_cpu
>= NR_CPUS
)
817 if (tlb_type
== hypervisor
) {
818 unsigned int ino
= __irq_ino(bucket
);
820 sun4v_intr_settarget(ino
, goal_cpu
);
821 sun4v_intr_setenabled(ino
, HV_INTR_ENABLED
);
823 unsigned long imap
= bucket
->imap
;
824 unsigned int tid
= sun4u_compute_tid(imap
, goal_cpu
);
826 upa_writel(tid
| IMAP_VALID
, imap
);
830 if (++goal_cpu
>= NR_CPUS
)
832 } while (!cpu_online(goal_cpu
));
837 /* Called from request_irq. */
838 static void distribute_irqs(void)
843 spin_lock_irqsave(&irq_action_lock
, flags
);
847 * Skip the timer at [0], and very rare error/power intrs at [15].
848 * Also level [12], it causes problems on Ex000 systems.
850 for (level
= 1; level
< NR_IRQS
; level
++) {
851 struct irqaction
*p
= irq_action
[level
];
857 cpu
= retarget_one_irq(p
, cpu
);
861 spin_unlock_irqrestore(&irq_action_lock
, flags
);
872 static struct sun5_timer
*prom_timers
;
873 static u64 prom_limit0
, prom_limit1
;
875 static void map_prom_timers(void)
877 unsigned int addr
[3];
880 /* PROM timer node hangs out in the top level of device siblings... */
881 tnode
= prom_finddevice("/counter-timer");
883 /* Assume if node is not present, PROM uses different tick mechanism
884 * which we should not care about.
886 if (tnode
== 0 || tnode
== -1) {
887 prom_timers
= (struct sun5_timer
*) 0;
891 /* If PROM is really using this, it must be mapped by him. */
892 err
= prom_getproperty(tnode
, "address", (char *)addr
, sizeof(addr
));
894 prom_printf("PROM does not have timer mapped, trying to continue.\n");
895 prom_timers
= (struct sun5_timer
*) 0;
898 prom_timers
= (struct sun5_timer
*) ((unsigned long)addr
[0]);
901 static void kill_prom_timer(void)
906 /* Save them away for later. */
907 prom_limit0
= prom_timers
->limit0
;
908 prom_limit1
= prom_timers
->limit1
;
910 /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14.
911 * We turn both off here just to be paranoid.
913 prom_timers
->limit0
= 0;
914 prom_timers
->limit1
= 0;
916 /* Wheee, eat the interrupt packet too... */
917 __asm__
__volatile__(
919 " ldxa [%%g0] %0, %%g1\n"
920 " ldxa [%%g2] %1, %%g1\n"
921 " stxa %%g0, [%%g0] %0\n"
924 : "i" (ASI_INTR_RECEIVE
), "i" (ASI_INTR_R
)
928 void init_irqwork_curcpu(void)
930 int cpu
= hard_smp_processor_id();
932 memset(__irq_work
+ cpu
, 0, sizeof(struct irq_work_struct
));
935 static void __cpuinit
register_one_mondo(unsigned long paddr
, unsigned long type
)
937 unsigned long num_entries
= 128;
938 unsigned long status
;
940 status
= sun4v_cpu_qconf(type
, paddr
, num_entries
);
941 if (status
!= HV_EOK
) {
942 prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, "
943 "err %lu\n", type
, paddr
, num_entries
, status
);
948 static void __cpuinit
sun4v_register_mondo_queues(int this_cpu
)
950 struct trap_per_cpu
*tb
= &trap_block
[this_cpu
];
952 register_one_mondo(tb
->cpu_mondo_pa
, HV_CPU_QUEUE_CPU_MONDO
);
953 register_one_mondo(tb
->dev_mondo_pa
, HV_CPU_QUEUE_DEVICE_MONDO
);
954 register_one_mondo(tb
->resum_mondo_pa
, HV_CPU_QUEUE_RES_ERROR
);
955 register_one_mondo(tb
->nonresum_mondo_pa
, HV_CPU_QUEUE_NONRES_ERROR
);
958 static void __cpuinit
alloc_one_mondo(unsigned long *pa_ptr
, int use_bootmem
)
963 page
= alloc_bootmem_low_pages(PAGE_SIZE
);
965 page
= (void *) get_zeroed_page(GFP_ATOMIC
);
968 prom_printf("SUN4V: Error, cannot allocate mondo queue.\n");
972 *pa_ptr
= __pa(page
);
975 static void __cpuinit
alloc_one_kbuf(unsigned long *pa_ptr
, int use_bootmem
)
980 page
= alloc_bootmem_low_pages(PAGE_SIZE
);
982 page
= (void *) get_zeroed_page(GFP_ATOMIC
);
985 prom_printf("SUN4V: Error, cannot allocate kbuf page.\n");
989 *pa_ptr
= __pa(page
);
992 static void __cpuinit
init_cpu_send_mondo_info(struct trap_per_cpu
*tb
, int use_bootmem
)
997 BUILD_BUG_ON((NR_CPUS
* sizeof(u16
)) > (PAGE_SIZE
- 64));
1000 page
= alloc_bootmem_low_pages(PAGE_SIZE
);
1002 page
= (void *) get_zeroed_page(GFP_ATOMIC
);
1005 prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n");
1009 tb
->cpu_mondo_block_pa
= __pa(page
);
1010 tb
->cpu_list_pa
= __pa(page
+ 64);
1014 /* Allocate and register the mondo and error queues for this cpu. */
1015 void __cpuinit
sun4v_init_mondo_queues(int use_bootmem
, int cpu
, int alloc
, int load
)
1017 struct trap_per_cpu
*tb
= &trap_block
[cpu
];
1020 alloc_one_mondo(&tb
->cpu_mondo_pa
, use_bootmem
);
1021 alloc_one_mondo(&tb
->dev_mondo_pa
, use_bootmem
);
1022 alloc_one_mondo(&tb
->resum_mondo_pa
, use_bootmem
);
1023 alloc_one_kbuf(&tb
->resum_kernel_buf_pa
, use_bootmem
);
1024 alloc_one_mondo(&tb
->nonresum_mondo_pa
, use_bootmem
);
1025 alloc_one_kbuf(&tb
->nonresum_kernel_buf_pa
, use_bootmem
);
1027 init_cpu_send_mondo_info(tb
, use_bootmem
);
1031 if (cpu
!= hard_smp_processor_id()) {
1032 prom_printf("SUN4V: init mondo on cpu %d not %d\n",
1033 cpu
, hard_smp_processor_id());
1036 sun4v_register_mondo_queues(cpu
);
1040 /* Only invoked on boot processor. */
1041 void __init
init_IRQ(void)
1045 memset(&ivector_table
[0], 0, sizeof(ivector_table
));
1047 if (tlb_type
== hypervisor
)
1048 sun4v_init_mondo_queues(1, hard_smp_processor_id(), 1, 1);
1050 /* We need to clear any IRQ's pending in the soft interrupt
1051 * registers, a spurious one could be left around from the
1052 * PROM timer which we just disabled.
1054 clear_softint(get_softint());
1056 /* Now that ivector table is initialized, it is safe
1057 * to receive IRQ vector traps. We will normally take
1058 * one or two right now, in case some device PROM used
1059 * to boot us wants to speak to us. We just ignore them.
1061 __asm__
__volatile__("rdpr %%pstate, %%g1\n\t"
1062 "or %%g1, %0, %%g1\n\t"
1063 "wrpr %%g1, 0x0, %%pstate"
1069 static struct proc_dir_entry
* root_irq_dir
;
1070 static struct proc_dir_entry
* irq_dir
[NUM_IVECS
];
1074 static int irq_affinity_read_proc (char *page
, char **start
, off_t off
,
1075 int count
, int *eof
, void *data
)
1077 struct ino_bucket
*bp
= ivector_table
+ (long)data
;
1078 struct irq_desc
*desc
= bp
->irq_info
;
1079 struct irqaction
*ap
= desc
->action
;
1083 mask
= get_smpaff_in_irqaction(ap
);
1084 if (cpus_empty(mask
))
1085 mask
= cpu_online_map
;
1087 len
= cpumask_scnprintf(page
, count
, mask
);
1088 if (count
- len
< 2)
1090 len
+= sprintf(page
+ len
, "\n");
1094 static inline void set_intr_affinity(int irq
, cpumask_t hw_aff
)
1096 struct ino_bucket
*bp
= ivector_table
+ irq
;
1097 struct irq_desc
*desc
= bp
->irq_info
;
1098 struct irqaction
*ap
= desc
->action
;
1100 /* Users specify affinity in terms of hw cpu ids.
1101 * As soon as we do this, handler_irq() might see and take action.
1103 put_smpaff_in_irqaction(ap
, hw_aff
);
1105 /* Migration is simply done by the next cpu to service this
1110 static int irq_affinity_write_proc (struct file
*file
, const char __user
*buffer
,
1111 unsigned long count
, void *data
)
1113 int irq
= (long) data
, full_count
= count
, err
;
1114 cpumask_t new_value
;
1116 err
= cpumask_parse(buffer
, count
, new_value
);
1119 * Do not allow disabling IRQs completely - it's a too easy
1120 * way to make the system unusable accidentally :-) At least
1121 * one online CPU still has to be targeted.
1123 cpus_and(new_value
, new_value
, cpu_online_map
);
1124 if (cpus_empty(new_value
))
1127 set_intr_affinity(irq
, new_value
);
1134 #define MAX_NAMELEN 10
1136 static void register_irq_proc (unsigned int irq
)
1138 char name
[MAX_NAMELEN
];
1140 if (!root_irq_dir
|| irq_dir
[irq
])
1143 memset(name
, 0, MAX_NAMELEN
);
1144 sprintf(name
, "%x", irq
);
1146 /* create /proc/irq/1234 */
1147 irq_dir
[irq
] = proc_mkdir(name
, root_irq_dir
);
1150 /* XXX SMP affinity not supported on starfire yet. */
1151 if (this_is_starfire
== 0) {
1152 struct proc_dir_entry
*entry
;
1154 /* create /proc/irq/1234/smp_affinity */
1155 entry
= create_proc_entry("smp_affinity", 0600, irq_dir
[irq
]);
1159 entry
->data
= (void *)(long)irq
;
1160 entry
->read_proc
= irq_affinity_read_proc
;
1161 entry
->write_proc
= irq_affinity_write_proc
;
1167 void init_irq_proc (void)
1169 /* create /proc/irq */
1170 root_irq_dir
= proc_mkdir("irq", NULL
);