1 /* $Id: irq.c,v 1.114 2002/01/11 08:45:38 davem Exp $
2 * irq.c: UltraSparc IRQ handling/init/registry.
4 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
6 * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
9 #include <linux/config.h>
10 #include <linux/module.h>
11 #include <linux/sched.h>
12 #include <linux/ptrace.h>
13 #include <linux/errno.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/signal.h>
17 #include <linux/interrupt.h>
18 #include <linux/slab.h>
19 #include <linux/random.h>
20 #include <linux/init.h>
21 #include <linux/delay.h>
22 #include <linux/proc_fs.h>
23 #include <linux/seq_file.h>
24 #include <linux/bootmem.h>
25 #include <linux/irq.h>
27 #include <asm/ptrace.h>
28 #include <asm/processor.h>
29 #include <asm/atomic.h>
30 #include <asm/system.h>
34 #include <asm/iommu.h>
36 #include <asm/oplib.h>
37 #include <asm/timer.h>
39 #include <asm/starfire.h>
40 #include <asm/uaccess.h>
41 #include <asm/cache.h>
42 #include <asm/cpudata.h>
43 #include <asm/auxio.h>
46 /* UPA nodes send interrupt packet to UltraSparc with first data reg
47 * value low 5 (7 on Starfire) bits holding the IRQ identifier being
48 * delivered. We must translate this into a non-vector IRQ so we can
49 * set the softint on this cpu.
51 * To make processing these packets efficient and race free we use
52 * an array of irq buckets below. The interrupt vector handler in
53 * entry.S feeds incoming packets into per-cpu pil-indexed lists.
54 * The IVEC handler does not need to act atomically, the PIL dispatch
55 * code uses CAS to get an atomic snapshot of the list and clear it
58 * If you make changes to ino_bucket, please update hand coded assembler
59 * of the vectored interrupt trap handler(s) in entry.S and sun4v_ivec.S
62 /* Next handler in per-CPU IRQ worklist. We know that
63 * bucket pointers have the high 32-bits clear, so to
64 * save space we only store the bits we need.
66 /*0x00*/unsigned int irq_chain
;
68 /* Virtual interrupt number assigned to this INO. */
69 /*0x04*/unsigned int virt_irq
;
72 #define NUM_IVECS (IMAP_INR + 1)
73 struct ino_bucket ivector_table
[NUM_IVECS
] __attribute__ ((aligned (SMP_CACHE_BYTES
)));
75 #define __irq_ino(irq) \
76 (((struct ino_bucket *)(unsigned long)(irq)) - &ivector_table[0])
77 #define __bucket(irq) ((struct ino_bucket *)(unsigned long)(irq))
78 #define __irq(bucket) ((unsigned int)(unsigned long)(bucket))
80 /* This has to be in the main kernel image, it cannot be
81 * turned into per-cpu data. The reason is that the main
82 * kernel image is locked into the TLB and this structure
83 * is accessed from the vectored interrupt trap handler. If
84 * access to this structure takes a TLB miss it could cause
85 * the 5-level sparc v9 trap stack to overflow.
87 #define irq_work(__cpu) &(trap_block[(__cpu)].irq_worklist)
89 static unsigned int virt_to_real_irq_table
[NR_IRQS
];
90 static unsigned char virt_irq_cur
= 1;
92 static unsigned char virt_irq_alloc(unsigned int real_irq
)
96 BUILD_BUG_ON(NR_IRQS
>= 256);
100 printk(KERN_ERR
"IRQ: Out of virtual IRQs.\n");
104 virt_irq_cur
= ent
+ 1;
105 virt_to_real_irq_table
[ent
] = real_irq
;
110 #if 0 /* Currently unused. */
111 static unsigned char real_to_virt_irq(unsigned int real_irq
)
113 struct ino_bucket
*bucket
= __bucket(real_irq
);
115 return bucket
->virt_irq
;
119 static unsigned int virt_to_real_irq(unsigned char virt_irq
)
121 return virt_to_real_irq_table
[virt_irq
];
125 * /proc/interrupts printing:
128 int show_interrupts(struct seq_file
*p
, void *v
)
130 int i
= *(loff_t
*) v
, j
;
131 struct irqaction
* action
;
136 for_each_online_cpu(j
)
137 seq_printf(p
, "CPU%d ",j
);
142 spin_lock_irqsave(&irq_desc
[i
].lock
, flags
);
143 action
= irq_desc
[i
].action
;
146 seq_printf(p
, "%3d: ",i
);
148 seq_printf(p
, "%10u ", kstat_irqs(i
));
150 for_each_online_cpu(j
)
151 seq_printf(p
, "%10u ", kstat_cpu(j
).irqs
[i
]);
153 seq_printf(p
, " %9s", irq_desc
[i
].handler
->typename
);
154 seq_printf(p
, " %s", action
->name
);
156 for (action
=action
->next
; action
; action
= action
->next
)
157 seq_printf(p
, ", %s", action
->name
);
161 spin_unlock_irqrestore(&irq_desc
[i
].lock
, flags
);
166 extern unsigned long real_hard_smp_processor_id(void);
168 static unsigned int sun4u_compute_tid(unsigned long imap
, unsigned long cpuid
)
172 if (this_is_starfire
) {
173 tid
= starfire_translate(imap
, cpuid
);
174 tid
<<= IMAP_TID_SHIFT
;
177 if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
180 __asm__ ("rdpr %%ver, %0" : "=r" (ver
));
181 if ((ver
>> 32UL) == __JALAPENO_ID
||
182 (ver
>> 32UL) == __SERRANO_ID
) {
183 tid
= cpuid
<< IMAP_TID_SHIFT
;
184 tid
&= IMAP_TID_JBUS
;
186 unsigned int a
= cpuid
& 0x1f;
187 unsigned int n
= (cpuid
>> 5) & 0x1f;
189 tid
= ((a
<< IMAP_AID_SHIFT
) |
190 (n
<< IMAP_NID_SHIFT
));
191 tid
&= (IMAP_AID_SAFARI
|
195 tid
= cpuid
<< IMAP_TID_SHIFT
;
203 struct irq_handler_data
{
207 void (*pre_handler
)(unsigned int, void *, void *);
208 void *pre_handler_arg1
;
209 void *pre_handler_arg2
;
212 static inline struct ino_bucket
*virt_irq_to_bucket(unsigned int virt_irq
)
214 unsigned int real_irq
= virt_to_real_irq(virt_irq
);
215 struct ino_bucket
*bucket
= NULL
;
217 if (likely(real_irq
))
218 bucket
= __bucket(real_irq
);
224 static int irq_choose_cpu(unsigned int virt_irq
)
226 cpumask_t mask
= irq_affinity
[virt_irq
];
229 if (cpus_equal(mask
, CPU_MASK_ALL
)) {
230 static int irq_rover
;
231 static DEFINE_SPINLOCK(irq_rover_lock
);
234 /* Round-robin distribution... */
236 spin_lock_irqsave(&irq_rover_lock
, flags
);
238 while (!cpu_online(irq_rover
)) {
239 if (++irq_rover
>= NR_CPUS
)
244 if (++irq_rover
>= NR_CPUS
)
246 } while (!cpu_online(irq_rover
));
248 spin_unlock_irqrestore(&irq_rover_lock
, flags
);
252 cpus_and(tmp
, cpu_online_map
, mask
);
257 cpuid
= first_cpu(tmp
);
263 static int irq_choose_cpu(unsigned int virt_irq
)
265 return real_hard_smp_processor_id();
269 static void sun4u_irq_enable(unsigned int virt_irq
)
271 irq_desc_t
*desc
= irq_desc
+ virt_irq
;
272 struct irq_handler_data
*data
= desc
->handler_data
;
275 unsigned long cpuid
, imap
;
278 cpuid
= irq_choose_cpu(virt_irq
);
281 tid
= sun4u_compute_tid(imap
, cpuid
);
283 upa_writel(tid
| IMAP_VALID
, imap
);
287 static void sun4u_irq_disable(unsigned int virt_irq
)
289 irq_desc_t
*desc
= irq_desc
+ virt_irq
;
290 struct irq_handler_data
*data
= desc
->handler_data
;
293 unsigned long imap
= data
->imap
;
294 u32 tmp
= upa_readl(imap
);
297 upa_writel(tmp
, imap
);
301 static void sun4u_irq_end(unsigned int virt_irq
)
303 irq_desc_t
*desc
= irq_desc
+ virt_irq
;
304 struct irq_handler_data
*data
= desc
->handler_data
;
307 upa_writel(ICLR_IDLE
, data
->iclr
);
310 static void sun4v_irq_enable(unsigned int virt_irq
)
312 struct ino_bucket
*bucket
= virt_irq_to_bucket(virt_irq
);
313 unsigned int ino
= bucket
- &ivector_table
[0];
315 if (likely(bucket
)) {
319 cpuid
= irq_choose_cpu(virt_irq
);
321 err
= sun4v_intr_settarget(ino
, cpuid
);
323 printk("sun4v_intr_settarget(%x,%lu): err(%d)\n",
325 err
= sun4v_intr_setenabled(ino
, HV_INTR_ENABLED
);
327 printk("sun4v_intr_setenabled(%x): err(%d)\n",
332 static void sun4v_irq_disable(unsigned int virt_irq
)
334 struct ino_bucket
*bucket
= virt_irq_to_bucket(virt_irq
);
335 unsigned int ino
= bucket
- &ivector_table
[0];
337 if (likely(bucket
)) {
340 err
= sun4v_intr_setenabled(ino
, HV_INTR_DISABLED
);
342 printk("sun4v_intr_setenabled(%x): "
343 "err(%d)\n", ino
, err
);
347 static void sun4v_irq_end(unsigned int virt_irq
)
349 struct ino_bucket
*bucket
= virt_irq_to_bucket(virt_irq
);
350 unsigned int ino
= bucket
- &ivector_table
[0];
352 if (likely(bucket
)) {
355 err
= sun4v_intr_setstate(ino
, HV_INTR_STATE_IDLE
);
357 printk("sun4v_intr_setstate(%x): "
358 "err(%d)\n", ino
, err
);
362 static void run_pre_handler(unsigned int virt_irq
)
364 struct ino_bucket
*bucket
= virt_irq_to_bucket(virt_irq
);
365 irq_desc_t
*desc
= irq_desc
+ virt_irq
;
366 struct irq_handler_data
*data
= desc
->handler_data
;
368 if (likely(data
->pre_handler
)) {
369 data
->pre_handler(__irq_ino(__irq(bucket
)),
370 data
->pre_handler_arg1
,
371 data
->pre_handler_arg2
);
375 static struct hw_interrupt_type sun4u_irq
= {
377 .enable
= sun4u_irq_enable
,
378 .disable
= sun4u_irq_disable
,
379 .end
= sun4u_irq_end
,
382 static struct hw_interrupt_type sun4u_irq_ack
= {
383 .typename
= "sun4u+ack",
384 .enable
= sun4u_irq_enable
,
385 .disable
= sun4u_irq_disable
,
386 .ack
= run_pre_handler
,
387 .end
= sun4u_irq_end
,
390 static struct hw_interrupt_type sun4v_irq
= {
392 .enable
= sun4v_irq_enable
,
393 .disable
= sun4v_irq_disable
,
394 .end
= sun4v_irq_end
,
397 static struct hw_interrupt_type sun4v_irq_ack
= {
398 .typename
= "sun4v+ack",
399 .enable
= sun4v_irq_enable
,
400 .disable
= sun4v_irq_disable
,
401 .ack
= run_pre_handler
,
402 .end
= sun4v_irq_end
,
405 void irq_install_pre_handler(int virt_irq
,
406 void (*func
)(unsigned int, void *, void *),
407 void *arg1
, void *arg2
)
409 irq_desc_t
*desc
= irq_desc
+ virt_irq
;
410 struct irq_handler_data
*data
= desc
->handler_data
;
412 data
->pre_handler
= func
;
413 data
->pre_handler_arg1
= arg1
;
414 data
->pre_handler_arg2
= arg2
;
416 desc
->handler
= (desc
->handler
== &sun4u_irq
?
417 &sun4u_irq_ack
: &sun4v_irq_ack
);
420 unsigned int build_irq(int inofixup
, unsigned long iclr
, unsigned long imap
)
422 struct ino_bucket
*bucket
;
423 struct irq_handler_data
*data
;
427 BUG_ON(tlb_type
== hypervisor
);
429 ino
= (upa_readl(imap
) & (IMAP_IGN
| IMAP_INO
)) + inofixup
;
430 bucket
= &ivector_table
[ino
];
431 if (!bucket
->virt_irq
) {
432 bucket
->virt_irq
= virt_irq_alloc(__irq(bucket
));
433 irq_desc
[bucket
->virt_irq
].handler
= &sun4u_irq
;
436 desc
= irq_desc
+ bucket
->virt_irq
;
437 if (unlikely(desc
->handler_data
))
440 data
= kzalloc(sizeof(struct irq_handler_data
), GFP_ATOMIC
);
441 if (unlikely(!data
)) {
442 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
445 desc
->handler_data
= data
;
451 return bucket
->virt_irq
;
454 unsigned int sun4v_build_irq(u32 devhandle
, unsigned int devino
)
456 struct ino_bucket
*bucket
;
457 struct irq_handler_data
*data
;
458 unsigned long sysino
;
461 BUG_ON(tlb_type
!= hypervisor
);
463 sysino
= sun4v_devino_to_sysino(devhandle
, devino
);
464 bucket
= &ivector_table
[sysino
];
465 if (!bucket
->virt_irq
) {
466 bucket
->virt_irq
= virt_irq_alloc(__irq(bucket
));
467 irq_desc
[bucket
->virt_irq
].handler
= &sun4v_irq
;
470 desc
= irq_desc
+ bucket
->virt_irq
;
471 if (unlikely(desc
->handler_data
))
474 data
= kzalloc(sizeof(struct irq_handler_data
), GFP_ATOMIC
);
475 if (unlikely(!data
)) {
476 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
479 desc
->handler_data
= data
;
481 /* Catch accidental accesses to these things. IMAP/ICLR handling
482 * is done by hypervisor calls on sun4v platforms, not by direct
489 return bucket
->virt_irq
;
492 void hw_resend_irq(struct hw_interrupt_type
*handler
, unsigned int virt_irq
)
494 struct ino_bucket
*bucket
= virt_irq_to_bucket(virt_irq
);
495 unsigned long pstate
;
498 __asm__
__volatile__("rdpr %%pstate, %0" : "=r" (pstate
));
499 __asm__
__volatile__("wrpr %0, %1, %%pstate"
500 : : "r" (pstate
), "i" (PSTATE_IE
));
501 ent
= irq_work(smp_processor_id());
502 bucket
->irq_chain
= *ent
;
503 *ent
= __irq(bucket
);
504 set_softint(1 << PIL_DEVICE_IRQ
);
505 __asm__
__volatile__("wrpr %0, 0x0, %%pstate" : : "r" (pstate
));
508 void ack_bad_irq(unsigned int virt_irq
)
510 struct ino_bucket
*bucket
= virt_irq_to_bucket(virt_irq
);
511 unsigned int ino
= 0xdeadbeef;
514 ino
= bucket
- &ivector_table
[0];
516 printk(KERN_CRIT
"Unexpected IRQ from ino[%x] virt_irq[%u]\n",
521 extern irqreturn_t
timer_interrupt(int, void *, struct pt_regs
*);
523 void timer_irq(int irq
, struct pt_regs
*regs
)
525 unsigned long clr_mask
= 1 << irq
;
526 unsigned long tick_mask
= tick_ops
->softint_mask
;
528 if (get_softint() & tick_mask
) {
530 clr_mask
= tick_mask
;
532 clear_softint(clr_mask
);
536 kstat_this_cpu
.irqs
[0]++;
537 timer_interrupt(irq
, NULL
, regs
);
543 void handler_irq(int irq
, struct pt_regs
*regs
)
545 struct ino_bucket
*bucket
;
547 clear_softint(1 << irq
);
552 bucket
= __bucket(xchg32(irq_work(smp_processor_id()), 0));
554 struct ino_bucket
*next
= __bucket(bucket
->irq_chain
);
556 bucket
->irq_chain
= 0;
557 __do_IRQ(bucket
->virt_irq
, regs
);
565 #ifdef CONFIG_BLK_DEV_FD
566 extern irqreturn_t
floppy_interrupt(int, void *, struct pt_regs
*);
568 /* XXX No easy way to include asm/floppy.h XXX */
569 extern unsigned char *pdma_vaddr
;
570 extern unsigned long pdma_size
;
571 extern volatile int doing_pdma
;
572 extern unsigned long fdc_status
;
574 irqreturn_t
sparc_floppy_irq(int irq
, void *dev_cookie
, struct pt_regs
*regs
)
576 if (likely(doing_pdma
)) {
577 void __iomem
*stat
= (void __iomem
*) fdc_status
;
578 unsigned char *vaddr
= pdma_vaddr
;
579 unsigned long size
= pdma_size
;
584 if (unlikely(!(val
& 0x80))) {
589 if (unlikely(!(val
& 0x20))) {
597 *vaddr
++ = readb(stat
+ 1);
599 unsigned char data
= *vaddr
++;
602 writeb(data
, stat
+ 1);
610 /* Send Terminal Count pulse to floppy controller. */
611 val
= readb(auxio_register
);
612 val
|= AUXIO_AUX1_FTCNT
;
613 writeb(val
, auxio_register
);
614 val
&= ~AUXIO_AUX1_FTCNT
;
615 writeb(val
, auxio_register
);
621 return floppy_interrupt(irq
, dev_cookie
, regs
);
623 EXPORT_SYMBOL(sparc_floppy_irq
);
633 static struct sun5_timer
*prom_timers
;
634 static u64 prom_limit0
, prom_limit1
;
636 static void map_prom_timers(void)
638 unsigned int addr
[3];
641 /* PROM timer node hangs out in the top level of device siblings... */
642 tnode
= prom_finddevice("/counter-timer");
644 /* Assume if node is not present, PROM uses different tick mechanism
645 * which we should not care about.
647 if (tnode
== 0 || tnode
== -1) {
648 prom_timers
= (struct sun5_timer
*) 0;
652 /* If PROM is really using this, it must be mapped by him. */
653 err
= prom_getproperty(tnode
, "address", (char *)addr
, sizeof(addr
));
655 prom_printf("PROM does not have timer mapped, trying to continue.\n");
656 prom_timers
= (struct sun5_timer
*) 0;
659 prom_timers
= (struct sun5_timer
*) ((unsigned long)addr
[0]);
662 static void kill_prom_timer(void)
667 /* Save them away for later. */
668 prom_limit0
= prom_timers
->limit0
;
669 prom_limit1
= prom_timers
->limit1
;
671 /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14.
672 * We turn both off here just to be paranoid.
674 prom_timers
->limit0
= 0;
675 prom_timers
->limit1
= 0;
677 /* Wheee, eat the interrupt packet too... */
678 __asm__
__volatile__(
680 " ldxa [%%g0] %0, %%g1\n"
681 " ldxa [%%g2] %1, %%g1\n"
682 " stxa %%g0, [%%g0] %0\n"
685 : "i" (ASI_INTR_RECEIVE
), "i" (ASI_INTR_R
)
689 void init_irqwork_curcpu(void)
691 int cpu
= hard_smp_processor_id();
693 trap_block
[cpu
].irq_worklist
= 0;
696 static void __cpuinit
register_one_mondo(unsigned long paddr
, unsigned long type
)
698 unsigned long num_entries
= 128;
699 unsigned long status
;
701 status
= sun4v_cpu_qconf(type
, paddr
, num_entries
);
702 if (status
!= HV_EOK
) {
703 prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, "
704 "err %lu\n", type
, paddr
, num_entries
, status
);
709 static void __cpuinit
sun4v_register_mondo_queues(int this_cpu
)
711 struct trap_per_cpu
*tb
= &trap_block
[this_cpu
];
713 register_one_mondo(tb
->cpu_mondo_pa
, HV_CPU_QUEUE_CPU_MONDO
);
714 register_one_mondo(tb
->dev_mondo_pa
, HV_CPU_QUEUE_DEVICE_MONDO
);
715 register_one_mondo(tb
->resum_mondo_pa
, HV_CPU_QUEUE_RES_ERROR
);
716 register_one_mondo(tb
->nonresum_mondo_pa
, HV_CPU_QUEUE_NONRES_ERROR
);
719 static void __cpuinit
alloc_one_mondo(unsigned long *pa_ptr
, int use_bootmem
)
724 page
= alloc_bootmem_low_pages(PAGE_SIZE
);
726 page
= (void *) get_zeroed_page(GFP_ATOMIC
);
729 prom_printf("SUN4V: Error, cannot allocate mondo queue.\n");
733 *pa_ptr
= __pa(page
);
736 static void __cpuinit
alloc_one_kbuf(unsigned long *pa_ptr
, int use_bootmem
)
741 page
= alloc_bootmem_low_pages(PAGE_SIZE
);
743 page
= (void *) get_zeroed_page(GFP_ATOMIC
);
746 prom_printf("SUN4V: Error, cannot allocate kbuf page.\n");
750 *pa_ptr
= __pa(page
);
753 static void __cpuinit
init_cpu_send_mondo_info(struct trap_per_cpu
*tb
, int use_bootmem
)
758 BUILD_BUG_ON((NR_CPUS
* sizeof(u16
)) > (PAGE_SIZE
- 64));
761 page
= alloc_bootmem_low_pages(PAGE_SIZE
);
763 page
= (void *) get_zeroed_page(GFP_ATOMIC
);
766 prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n");
770 tb
->cpu_mondo_block_pa
= __pa(page
);
771 tb
->cpu_list_pa
= __pa(page
+ 64);
775 /* Allocate and register the mondo and error queues for this cpu. */
776 void __cpuinit
sun4v_init_mondo_queues(int use_bootmem
, int cpu
, int alloc
, int load
)
778 struct trap_per_cpu
*tb
= &trap_block
[cpu
];
781 alloc_one_mondo(&tb
->cpu_mondo_pa
, use_bootmem
);
782 alloc_one_mondo(&tb
->dev_mondo_pa
, use_bootmem
);
783 alloc_one_mondo(&tb
->resum_mondo_pa
, use_bootmem
);
784 alloc_one_kbuf(&tb
->resum_kernel_buf_pa
, use_bootmem
);
785 alloc_one_mondo(&tb
->nonresum_mondo_pa
, use_bootmem
);
786 alloc_one_kbuf(&tb
->nonresum_kernel_buf_pa
, use_bootmem
);
788 init_cpu_send_mondo_info(tb
, use_bootmem
);
792 if (cpu
!= hard_smp_processor_id()) {
793 prom_printf("SUN4V: init mondo on cpu %d not %d\n",
794 cpu
, hard_smp_processor_id());
797 sun4v_register_mondo_queues(cpu
);
801 static struct irqaction timer_irq_action
= {
805 /* Only invoked on boot processor. */
806 void __init
init_IRQ(void)
810 memset(&ivector_table
[0], 0, sizeof(ivector_table
));
812 if (tlb_type
== hypervisor
)
813 sun4v_init_mondo_queues(1, hard_smp_processor_id(), 1, 1);
815 /* We need to clear any IRQ's pending in the soft interrupt
816 * registers, a spurious one could be left around from the
817 * PROM timer which we just disabled.
819 clear_softint(get_softint());
821 /* Now that ivector table is initialized, it is safe
822 * to receive IRQ vector traps. We will normally take
823 * one or two right now, in case some device PROM used
824 * to boot us wants to speak to us. We just ignore them.
826 __asm__
__volatile__("rdpr %%pstate, %%g1\n\t"
827 "or %%g1, %0, %%g1\n\t"
828 "wrpr %%g1, 0x0, %%pstate"
833 irq_desc
[0].action
= &timer_irq_action
;