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[mirror_ubuntu-bionic-kernel.git] / arch / sparc64 / kernel / pci_sabre.c
1 /* pci_sabre.c: Sabre specific PCI controller support.
2 *
3 * Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net)
4 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com)
6 */
7
8 #include <linux/kernel.h>
9 #include <linux/types.h>
10 #include <linux/pci.h>
11 #include <linux/init.h>
12 #include <linux/slab.h>
13 #include <linux/interrupt.h>
14 #include <linux/of_device.h>
15
16 #include <asm/apb.h>
17 #include <asm/iommu.h>
18 #include <asm/irq.h>
19 #include <asm/prom.h>
20
21 #include "pci_impl.h"
22 #include "iommu_common.h"
23
24 #define DRIVER_NAME "sabre"
25 #define PFX DRIVER_NAME ": "
26
27 /* All SABRE registers are 64-bits. The following accessor
28 * routines are how they are accessed. The REG parameter
29 * is a physical address.
30 */
31 #define sabre_read(__reg) \
32 ({ u64 __ret; \
33 __asm__ __volatile__("ldxa [%1] %2, %0" \
34 : "=r" (__ret) \
35 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
36 : "memory"); \
37 __ret; \
38 })
39 #define sabre_write(__reg, __val) \
40 __asm__ __volatile__("stxa %0, [%1] %2" \
41 : /* no outputs */ \
42 : "r" (__val), "r" (__reg), \
43 "i" (ASI_PHYS_BYPASS_EC_E) \
44 : "memory")
45
46 /* SABRE PCI controller register offsets and definitions. */
47 #define SABRE_UE_AFSR 0x0030UL
48 #define SABRE_UEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */
49 #define SABRE_UEAFSR_PDWR 0x2000000000000000UL /* Primary PCI DMA Write */
50 #define SABRE_UEAFSR_SDRD 0x0800000000000000UL /* Secondary PCI DMA Read */
51 #define SABRE_UEAFSR_SDWR 0x0400000000000000UL /* Secondary PCI DMA Write */
52 #define SABRE_UEAFSR_SDTE 0x0200000000000000UL /* Secondary DMA Translation Error */
53 #define SABRE_UEAFSR_PDTE 0x0100000000000000UL /* Primary DMA Translation Error */
54 #define SABRE_UEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask */
55 #define SABRE_UEAFSR_OFF 0x00000000e0000000UL /* Offset (AFAR bits [5:3] */
56 #define SABRE_UEAFSR_BLK 0x0000000000800000UL /* Was block operation */
57 #define SABRE_UECE_AFAR 0x0038UL
58 #define SABRE_CE_AFSR 0x0040UL
59 #define SABRE_CEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */
60 #define SABRE_CEAFSR_PDWR 0x2000000000000000UL /* Primary PCI DMA Write */
61 #define SABRE_CEAFSR_SDRD 0x0800000000000000UL /* Secondary PCI DMA Read */
62 #define SABRE_CEAFSR_SDWR 0x0400000000000000UL /* Secondary PCI DMA Write */
63 #define SABRE_CEAFSR_ESYND 0x00ff000000000000UL /* ECC Syndrome */
64 #define SABRE_CEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask */
65 #define SABRE_CEAFSR_OFF 0x00000000e0000000UL /* Offset */
66 #define SABRE_CEAFSR_BLK 0x0000000000800000UL /* Was block operation */
67 #define SABRE_UECE_AFAR_ALIAS 0x0048UL /* Aliases to 0x0038 */
68 #define SABRE_IOMMU_CONTROL 0x0200UL
69 #define SABRE_IOMMUCTRL_ERRSTS 0x0000000006000000UL /* Error status bits */
70 #define SABRE_IOMMUCTRL_ERR 0x0000000001000000UL /* Error present in IOTLB */
71 #define SABRE_IOMMUCTRL_LCKEN 0x0000000000800000UL /* IOTLB lock enable */
72 #define SABRE_IOMMUCTRL_LCKPTR 0x0000000000780000UL /* IOTLB lock pointer */
73 #define SABRE_IOMMUCTRL_TSBSZ 0x0000000000070000UL /* TSB Size */
74 #define SABRE_IOMMU_TSBSZ_1K 0x0000000000000000
75 #define SABRE_IOMMU_TSBSZ_2K 0x0000000000010000
76 #define SABRE_IOMMU_TSBSZ_4K 0x0000000000020000
77 #define SABRE_IOMMU_TSBSZ_8K 0x0000000000030000
78 #define SABRE_IOMMU_TSBSZ_16K 0x0000000000040000
79 #define SABRE_IOMMU_TSBSZ_32K 0x0000000000050000
80 #define SABRE_IOMMU_TSBSZ_64K 0x0000000000060000
81 #define SABRE_IOMMU_TSBSZ_128K 0x0000000000070000
82 #define SABRE_IOMMUCTRL_TBWSZ 0x0000000000000004UL /* TSB assumed page size */
83 #define SABRE_IOMMUCTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */
84 #define SABRE_IOMMUCTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */
85 #define SABRE_IOMMU_TSBBASE 0x0208UL
86 #define SABRE_IOMMU_FLUSH 0x0210UL
87 #define SABRE_IMAP_A_SLOT0 0x0c00UL
88 #define SABRE_IMAP_B_SLOT0 0x0c20UL
89 #define SABRE_IMAP_SCSI 0x1000UL
90 #define SABRE_IMAP_ETH 0x1008UL
91 #define SABRE_IMAP_BPP 0x1010UL
92 #define SABRE_IMAP_AU_REC 0x1018UL
93 #define SABRE_IMAP_AU_PLAY 0x1020UL
94 #define SABRE_IMAP_PFAIL 0x1028UL
95 #define SABRE_IMAP_KMS 0x1030UL
96 #define SABRE_IMAP_FLPY 0x1038UL
97 #define SABRE_IMAP_SHW 0x1040UL
98 #define SABRE_IMAP_KBD 0x1048UL
99 #define SABRE_IMAP_MS 0x1050UL
100 #define SABRE_IMAP_SER 0x1058UL
101 #define SABRE_IMAP_UE 0x1070UL
102 #define SABRE_IMAP_CE 0x1078UL
103 #define SABRE_IMAP_PCIERR 0x1080UL
104 #define SABRE_IMAP_GFX 0x1098UL
105 #define SABRE_IMAP_EUPA 0x10a0UL
106 #define SABRE_ICLR_A_SLOT0 0x1400UL
107 #define SABRE_ICLR_B_SLOT0 0x1480UL
108 #define SABRE_ICLR_SCSI 0x1800UL
109 #define SABRE_ICLR_ETH 0x1808UL
110 #define SABRE_ICLR_BPP 0x1810UL
111 #define SABRE_ICLR_AU_REC 0x1818UL
112 #define SABRE_ICLR_AU_PLAY 0x1820UL
113 #define SABRE_ICLR_PFAIL 0x1828UL
114 #define SABRE_ICLR_KMS 0x1830UL
115 #define SABRE_ICLR_FLPY 0x1838UL
116 #define SABRE_ICLR_SHW 0x1840UL
117 #define SABRE_ICLR_KBD 0x1848UL
118 #define SABRE_ICLR_MS 0x1850UL
119 #define SABRE_ICLR_SER 0x1858UL
120 #define SABRE_ICLR_UE 0x1870UL
121 #define SABRE_ICLR_CE 0x1878UL
122 #define SABRE_ICLR_PCIERR 0x1880UL
123 #define SABRE_WRSYNC 0x1c20UL
124 #define SABRE_PCICTRL 0x2000UL
125 #define SABRE_PCICTRL_MRLEN 0x0000001000000000UL /* Use MemoryReadLine for block loads/stores */
126 #define SABRE_PCICTRL_SERR 0x0000000400000000UL /* Set when SERR asserted on PCI bus */
127 #define SABRE_PCICTRL_ARBPARK 0x0000000000200000UL /* Bus Parking 0=Ultra-IIi 1=prev-bus-owner */
128 #define SABRE_PCICTRL_CPUPRIO 0x0000000000100000UL /* Ultra-IIi granted every other bus cycle */
129 #define SABRE_PCICTRL_ARBPRIO 0x00000000000f0000UL /* Slot which is granted every other bus cycle */
130 #define SABRE_PCICTRL_ERREN 0x0000000000000100UL /* PCI Error Interrupt Enable */
131 #define SABRE_PCICTRL_RTRYWE 0x0000000000000080UL /* DMA Flow Control 0=wait-if-possible 1=retry */
132 #define SABRE_PCICTRL_AEN 0x000000000000000fUL /* Slot PCI arbitration enables */
133 #define SABRE_PIOAFSR 0x2010UL
134 #define SABRE_PIOAFSR_PMA 0x8000000000000000UL /* Primary Master Abort */
135 #define SABRE_PIOAFSR_PTA 0x4000000000000000UL /* Primary Target Abort */
136 #define SABRE_PIOAFSR_PRTRY 0x2000000000000000UL /* Primary Excessive Retries */
137 #define SABRE_PIOAFSR_PPERR 0x1000000000000000UL /* Primary Parity Error */
138 #define SABRE_PIOAFSR_SMA 0x0800000000000000UL /* Secondary Master Abort */
139 #define SABRE_PIOAFSR_STA 0x0400000000000000UL /* Secondary Target Abort */
140 #define SABRE_PIOAFSR_SRTRY 0x0200000000000000UL /* Secondary Excessive Retries */
141 #define SABRE_PIOAFSR_SPERR 0x0100000000000000UL /* Secondary Parity Error */
142 #define SABRE_PIOAFSR_BMSK 0x0000ffff00000000UL /* Byte Mask */
143 #define SABRE_PIOAFSR_BLK 0x0000000080000000UL /* Was Block Operation */
144 #define SABRE_PIOAFAR 0x2018UL
145 #define SABRE_PCIDIAG 0x2020UL
146 #define SABRE_PCIDIAG_DRTRY 0x0000000000000040UL /* Disable PIO Retry Limit */
147 #define SABRE_PCIDIAG_IPAPAR 0x0000000000000008UL /* Invert PIO Address Parity */
148 #define SABRE_PCIDIAG_IPDPAR 0x0000000000000004UL /* Invert PIO Data Parity */
149 #define SABRE_PCIDIAG_IDDPAR 0x0000000000000002UL /* Invert DMA Data Parity */
150 #define SABRE_PCIDIAG_ELPBK 0x0000000000000001UL /* Loopback Enable - not supported */
151 #define SABRE_PCITASR 0x2028UL
152 #define SABRE_PCITASR_EF 0x0000000000000080UL /* Respond to 0xe0000000-0xffffffff */
153 #define SABRE_PCITASR_CD 0x0000000000000040UL /* Respond to 0xc0000000-0xdfffffff */
154 #define SABRE_PCITASR_AB 0x0000000000000020UL /* Respond to 0xa0000000-0xbfffffff */
155 #define SABRE_PCITASR_89 0x0000000000000010UL /* Respond to 0x80000000-0x9fffffff */
156 #define SABRE_PCITASR_67 0x0000000000000008UL /* Respond to 0x60000000-0x7fffffff */
157 #define SABRE_PCITASR_45 0x0000000000000004UL /* Respond to 0x40000000-0x5fffffff */
158 #define SABRE_PCITASR_23 0x0000000000000002UL /* Respond to 0x20000000-0x3fffffff */
159 #define SABRE_PCITASR_01 0x0000000000000001UL /* Respond to 0x00000000-0x1fffffff */
160 #define SABRE_PIOBUF_DIAG 0x5000UL
161 #define SABRE_DMABUF_DIAGLO 0x5100UL
162 #define SABRE_DMABUF_DIAGHI 0x51c0UL
163 #define SABRE_IMAP_GFX_ALIAS 0x6000UL /* Aliases to 0x1098 */
164 #define SABRE_IMAP_EUPA_ALIAS 0x8000UL /* Aliases to 0x10a0 */
165 #define SABRE_IOMMU_VADIAG 0xa400UL
166 #define SABRE_IOMMU_TCDIAG 0xa408UL
167 #define SABRE_IOMMU_TAG 0xa580UL
168 #define SABRE_IOMMUTAG_ERRSTS 0x0000000001800000UL /* Error status bits */
169 #define SABRE_IOMMUTAG_ERR 0x0000000000400000UL /* Error present */
170 #define SABRE_IOMMUTAG_WRITE 0x0000000000200000UL /* Page is writable */
171 #define SABRE_IOMMUTAG_STREAM 0x0000000000100000UL /* Streamable bit - unused */
172 #define SABRE_IOMMUTAG_SIZE 0x0000000000080000UL /* 0=8k 1=16k */
173 #define SABRE_IOMMUTAG_VPN 0x000000000007ffffUL /* Virtual Page Number [31:13] */
174 #define SABRE_IOMMU_DATA 0xa600UL
175 #define SABRE_IOMMUDATA_VALID 0x0000000040000000UL /* Valid */
176 #define SABRE_IOMMUDATA_USED 0x0000000020000000UL /* Used (for LRU algorithm) */
177 #define SABRE_IOMMUDATA_CACHE 0x0000000010000000UL /* Cacheable */
178 #define SABRE_IOMMUDATA_PPN 0x00000000001fffffUL /* Physical Page Number [33:13] */
179 #define SABRE_PCI_IRQSTATE 0xa800UL
180 #define SABRE_OBIO_IRQSTATE 0xa808UL
181 #define SABRE_FFBCFG 0xf000UL
182 #define SABRE_FFBCFG_SPRQS 0x000000000f000000 /* Slave P_RQST queue size */
183 #define SABRE_FFBCFG_ONEREAD 0x0000000000004000 /* Slave supports one outstanding read */
184 #define SABRE_MCCTRL0 0xf010UL
185 #define SABRE_MCCTRL0_RENAB 0x0000000080000000 /* Refresh Enable */
186 #define SABRE_MCCTRL0_EENAB 0x0000000010000000 /* Enable all ECC functions */
187 #define SABRE_MCCTRL0_11BIT 0x0000000000001000 /* Enable 11-bit column addressing */
188 #define SABRE_MCCTRL0_DPP 0x0000000000000f00 /* DIMM Pair Present Bits */
189 #define SABRE_MCCTRL0_RINTVL 0x00000000000000ff /* Refresh Interval */
190 #define SABRE_MCCTRL1 0xf018UL
191 #define SABRE_MCCTRL1_AMDC 0x0000000038000000 /* Advance Memdata Clock */
192 #define SABRE_MCCTRL1_ARDC 0x0000000007000000 /* Advance DRAM Read Data Clock */
193 #define SABRE_MCCTRL1_CSR 0x0000000000e00000 /* CAS to RAS delay for CBR refresh */
194 #define SABRE_MCCTRL1_CASRW 0x00000000001c0000 /* CAS length for read/write */
195 #define SABRE_MCCTRL1_RCD 0x0000000000038000 /* RAS to CAS delay */
196 #define SABRE_MCCTRL1_CP 0x0000000000007000 /* CAS Precharge */
197 #define SABRE_MCCTRL1_RP 0x0000000000000e00 /* RAS Precharge */
198 #define SABRE_MCCTRL1_RAS 0x00000000000001c0 /* Length of RAS for refresh */
199 #define SABRE_MCCTRL1_CASRW2 0x0000000000000038 /* Must be same as CASRW */
200 #define SABRE_MCCTRL1_RSC 0x0000000000000007 /* RAS after CAS hold time */
201 #define SABRE_RESETCTRL 0xf020UL
202
203 #define SABRE_CONFIGSPACE 0x001000000UL
204 #define SABRE_IOSPACE 0x002000000UL
205 #define SABRE_IOSPACE_SIZE 0x000ffffffUL
206 #define SABRE_MEMSPACE 0x100000000UL
207 #define SABRE_MEMSPACE_SIZE 0x07fffffffUL
208
209 static int hummingbird_p;
210 static struct pci_bus *sabre_root_bus;
211
212 /* SABRE error handling support. */
213 static void sabre_check_iommu_error(struct pci_pbm_info *pbm,
214 unsigned long afsr,
215 unsigned long afar)
216 {
217 struct iommu *iommu = pbm->iommu;
218 unsigned long iommu_tag[16];
219 unsigned long iommu_data[16];
220 unsigned long flags;
221 u64 control;
222 int i;
223
224 spin_lock_irqsave(&iommu->lock, flags);
225 control = sabre_read(iommu->iommu_control);
226 if (control & SABRE_IOMMUCTRL_ERR) {
227 char *type_string;
228
229 /* Clear the error encountered bit.
230 * NOTE: On Sabre this is write 1 to clear,
231 * which is different from Psycho.
232 */
233 sabre_write(iommu->iommu_control, control);
234 switch((control & SABRE_IOMMUCTRL_ERRSTS) >> 25UL) {
235 case 1:
236 type_string = "Invalid Error";
237 break;
238 case 3:
239 type_string = "ECC Error";
240 break;
241 default:
242 type_string = "Unknown";
243 break;
244 };
245 printk("%s: IOMMU Error, type[%s]\n",
246 pbm->name, type_string);
247
248 /* Enter diagnostic mode and probe for error'd
249 * entries in the IOTLB.
250 */
251 control &= ~(SABRE_IOMMUCTRL_ERRSTS | SABRE_IOMMUCTRL_ERR);
252 sabre_write(iommu->iommu_control,
253 (control | SABRE_IOMMUCTRL_DENAB));
254 for (i = 0; i < 16; i++) {
255 unsigned long base = pbm->controller_regs;
256
257 iommu_tag[i] =
258 sabre_read(base + SABRE_IOMMU_TAG + (i * 8UL));
259 iommu_data[i] =
260 sabre_read(base + SABRE_IOMMU_DATA + (i * 8UL));
261 sabre_write(base + SABRE_IOMMU_TAG + (i * 8UL), 0);
262 sabre_write(base + SABRE_IOMMU_DATA + (i * 8UL), 0);
263 }
264 sabre_write(iommu->iommu_control, control);
265
266 for (i = 0; i < 16; i++) {
267 unsigned long tag, data;
268
269 tag = iommu_tag[i];
270 if (!(tag & SABRE_IOMMUTAG_ERR))
271 continue;
272
273 data = iommu_data[i];
274 switch((tag & SABRE_IOMMUTAG_ERRSTS) >> 23UL) {
275 case 1:
276 type_string = "Invalid Error";
277 break;
278 case 3:
279 type_string = "ECC Error";
280 break;
281 default:
282 type_string = "Unknown";
283 break;
284 };
285 printk("%s: IOMMU TAG(%d)[RAW(%016lx)error(%s)wr(%d)sz(%dK)vpg(%08lx)]\n",
286 pbm->name, i, tag, type_string,
287 ((tag & SABRE_IOMMUTAG_WRITE) ? 1 : 0),
288 ((tag & SABRE_IOMMUTAG_SIZE) ? 64 : 8),
289 ((tag & SABRE_IOMMUTAG_VPN) << IOMMU_PAGE_SHIFT));
290 printk("%s: IOMMU DATA(%d)[RAW(%016lx)valid(%d)used(%d)cache(%d)ppg(%016lx)\n",
291 pbm->name, i, data,
292 ((data & SABRE_IOMMUDATA_VALID) ? 1 : 0),
293 ((data & SABRE_IOMMUDATA_USED) ? 1 : 0),
294 ((data & SABRE_IOMMUDATA_CACHE) ? 1 : 0),
295 ((data & SABRE_IOMMUDATA_PPN) << IOMMU_PAGE_SHIFT));
296 }
297 }
298 spin_unlock_irqrestore(&iommu->lock, flags);
299 }
300
301 static irqreturn_t sabre_ue_intr(int irq, void *dev_id)
302 {
303 struct pci_pbm_info *pbm = dev_id;
304 unsigned long afsr_reg = pbm->controller_regs + SABRE_UE_AFSR;
305 unsigned long afar_reg = pbm->controller_regs + SABRE_UECE_AFAR;
306 unsigned long afsr, afar, error_bits;
307 int reported;
308
309 /* Latch uncorrectable error status. */
310 afar = sabre_read(afar_reg);
311 afsr = sabre_read(afsr_reg);
312
313 /* Clear the primary/secondary error status bits. */
314 error_bits = afsr &
315 (SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR |
316 SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR |
317 SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE);
318 if (!error_bits)
319 return IRQ_NONE;
320 sabre_write(afsr_reg, error_bits);
321
322 /* Log the error. */
323 printk("%s: Uncorrectable Error, primary error type[%s%s]\n",
324 pbm->name,
325 ((error_bits & SABRE_UEAFSR_PDRD) ?
326 "DMA Read" :
327 ((error_bits & SABRE_UEAFSR_PDWR) ?
328 "DMA Write" : "???")),
329 ((error_bits & SABRE_UEAFSR_PDTE) ?
330 ":Translation Error" : ""));
331 printk("%s: bytemask[%04lx] dword_offset[%lx] was_block(%d)\n",
332 pbm->name,
333 (afsr & SABRE_UEAFSR_BMSK) >> 32UL,
334 (afsr & SABRE_UEAFSR_OFF) >> 29UL,
335 ((afsr & SABRE_UEAFSR_BLK) ? 1 : 0));
336 printk("%s: UE AFAR [%016lx]\n", pbm->name, afar);
337 printk("%s: UE Secondary errors [", pbm->name);
338 reported = 0;
339 if (afsr & SABRE_UEAFSR_SDRD) {
340 reported++;
341 printk("(DMA Read)");
342 }
343 if (afsr & SABRE_UEAFSR_SDWR) {
344 reported++;
345 printk("(DMA Write)");
346 }
347 if (afsr & SABRE_UEAFSR_SDTE) {
348 reported++;
349 printk("(Translation Error)");
350 }
351 if (!reported)
352 printk("(none)");
353 printk("]\n");
354
355 /* Interrogate IOMMU for error status. */
356 sabre_check_iommu_error(pbm, afsr, afar);
357
358 return IRQ_HANDLED;
359 }
360
361 static irqreturn_t sabre_ce_intr(int irq, void *dev_id)
362 {
363 struct pci_pbm_info *pbm = dev_id;
364 unsigned long afsr_reg = pbm->controller_regs + SABRE_CE_AFSR;
365 unsigned long afar_reg = pbm->controller_regs + SABRE_UECE_AFAR;
366 unsigned long afsr, afar, error_bits;
367 int reported;
368
369 /* Latch error status. */
370 afar = sabre_read(afar_reg);
371 afsr = sabre_read(afsr_reg);
372
373 /* Clear primary/secondary error status bits. */
374 error_bits = afsr &
375 (SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR |
376 SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR);
377 if (!error_bits)
378 return IRQ_NONE;
379 sabre_write(afsr_reg, error_bits);
380
381 /* Log the error. */
382 printk("%s: Correctable Error, primary error type[%s]\n",
383 pbm->name,
384 ((error_bits & SABRE_CEAFSR_PDRD) ?
385 "DMA Read" :
386 ((error_bits & SABRE_CEAFSR_PDWR) ?
387 "DMA Write" : "???")));
388
389 /* XXX Use syndrome and afar to print out module string just like
390 * XXX UDB CE trap handler does... -DaveM
391 */
392 printk("%s: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] "
393 "was_block(%d)\n",
394 pbm->name,
395 (afsr & SABRE_CEAFSR_ESYND) >> 48UL,
396 (afsr & SABRE_CEAFSR_BMSK) >> 32UL,
397 (afsr & SABRE_CEAFSR_OFF) >> 29UL,
398 ((afsr & SABRE_CEAFSR_BLK) ? 1 : 0));
399 printk("%s: CE AFAR [%016lx]\n", pbm->name, afar);
400 printk("%s: CE Secondary errors [", pbm->name);
401 reported = 0;
402 if (afsr & SABRE_CEAFSR_SDRD) {
403 reported++;
404 printk("(DMA Read)");
405 }
406 if (afsr & SABRE_CEAFSR_SDWR) {
407 reported++;
408 printk("(DMA Write)");
409 }
410 if (!reported)
411 printk("(none)");
412 printk("]\n");
413
414 return IRQ_HANDLED;
415 }
416
417 static irqreturn_t sabre_pcierr_intr_other(struct pci_pbm_info *pbm)
418 {
419 unsigned long csr_reg, csr, csr_error_bits;
420 irqreturn_t ret = IRQ_NONE;
421 u16 stat;
422
423 csr_reg = pbm->controller_regs + SABRE_PCICTRL;
424 csr = sabre_read(csr_reg);
425 csr_error_bits =
426 csr & SABRE_PCICTRL_SERR;
427 if (csr_error_bits) {
428 /* Clear the errors. */
429 sabre_write(csr_reg, csr);
430
431 /* Log 'em. */
432 if (csr_error_bits & SABRE_PCICTRL_SERR)
433 printk("%s: PCI SERR signal asserted.\n",
434 pbm->name);
435 ret = IRQ_HANDLED;
436 }
437 pci_bus_read_config_word(sabre_root_bus, 0,
438 PCI_STATUS, &stat);
439 if (stat & (PCI_STATUS_PARITY |
440 PCI_STATUS_SIG_TARGET_ABORT |
441 PCI_STATUS_REC_TARGET_ABORT |
442 PCI_STATUS_REC_MASTER_ABORT |
443 PCI_STATUS_SIG_SYSTEM_ERROR)) {
444 printk("%s: PCI bus error, PCI_STATUS[%04x]\n",
445 pbm->name, stat);
446 pci_bus_write_config_word(sabre_root_bus, 0,
447 PCI_STATUS, 0xffff);
448 ret = IRQ_HANDLED;
449 }
450 return ret;
451 }
452
453 static irqreturn_t sabre_pcierr_intr(int irq, void *dev_id)
454 {
455 struct pci_pbm_info *pbm = dev_id;
456 unsigned long afsr_reg, afar_reg;
457 unsigned long afsr, afar, error_bits;
458 int reported;
459
460 afsr_reg = pbm->controller_regs + SABRE_PIOAFSR;
461 afar_reg = pbm->controller_regs + SABRE_PIOAFAR;
462
463 /* Latch error status. */
464 afar = sabre_read(afar_reg);
465 afsr = sabre_read(afsr_reg);
466
467 /* Clear primary/secondary error status bits. */
468 error_bits = afsr &
469 (SABRE_PIOAFSR_PMA | SABRE_PIOAFSR_PTA |
470 SABRE_PIOAFSR_PRTRY | SABRE_PIOAFSR_PPERR |
471 SABRE_PIOAFSR_SMA | SABRE_PIOAFSR_STA |
472 SABRE_PIOAFSR_SRTRY | SABRE_PIOAFSR_SPERR);
473 if (!error_bits)
474 return sabre_pcierr_intr_other(pbm);
475 sabre_write(afsr_reg, error_bits);
476
477 /* Log the error. */
478 printk("%s: PCI Error, primary error type[%s]\n",
479 pbm->name,
480 (((error_bits & SABRE_PIOAFSR_PMA) ?
481 "Master Abort" :
482 ((error_bits & SABRE_PIOAFSR_PTA) ?
483 "Target Abort" :
484 ((error_bits & SABRE_PIOAFSR_PRTRY) ?
485 "Excessive Retries" :
486 ((error_bits & SABRE_PIOAFSR_PPERR) ?
487 "Parity Error" : "???"))))));
488 printk("%s: bytemask[%04lx] was_block(%d)\n",
489 pbm->name,
490 (afsr & SABRE_PIOAFSR_BMSK) >> 32UL,
491 (afsr & SABRE_PIOAFSR_BLK) ? 1 : 0);
492 printk("%s: PCI AFAR [%016lx]\n", pbm->name, afar);
493 printk("%s: PCI Secondary errors [", pbm->name);
494 reported = 0;
495 if (afsr & SABRE_PIOAFSR_SMA) {
496 reported++;
497 printk("(Master Abort)");
498 }
499 if (afsr & SABRE_PIOAFSR_STA) {
500 reported++;
501 printk("(Target Abort)");
502 }
503 if (afsr & SABRE_PIOAFSR_SRTRY) {
504 reported++;
505 printk("(Excessive Retries)");
506 }
507 if (afsr & SABRE_PIOAFSR_SPERR) {
508 reported++;
509 printk("(Parity Error)");
510 }
511 if (!reported)
512 printk("(none)");
513 printk("]\n");
514
515 /* For the error types shown, scan both PCI buses for devices
516 * which have logged that error type.
517 */
518
519 /* If we see a Target Abort, this could be the result of an
520 * IOMMU translation error of some sort. It is extremely
521 * useful to log this information as usually it indicates
522 * a bug in the IOMMU support code or a PCI device driver.
523 */
524 if (error_bits & (SABRE_PIOAFSR_PTA | SABRE_PIOAFSR_STA)) {
525 sabre_check_iommu_error(pbm, afsr, afar);
526 pci_scan_for_target_abort(pbm, pbm->pci_bus);
527 }
528 if (error_bits & (SABRE_PIOAFSR_PMA | SABRE_PIOAFSR_SMA))
529 pci_scan_for_master_abort(pbm, pbm->pci_bus);
530
531 /* For excessive retries, SABRE/PBM will abort the device
532 * and there is no way to specifically check for excessive
533 * retries in the config space status registers. So what
534 * we hope is that we'll catch it via the master/target
535 * abort events.
536 */
537
538 if (error_bits & (SABRE_PIOAFSR_PPERR | SABRE_PIOAFSR_SPERR))
539 pci_scan_for_parity_error(pbm, pbm->pci_bus);
540
541 return IRQ_HANDLED;
542 }
543
544 static void sabre_register_error_handlers(struct pci_pbm_info *pbm)
545 {
546 struct device_node *dp = pbm->prom_node;
547 struct of_device *op;
548 unsigned long base = pbm->controller_regs;
549 u64 tmp;
550 int err;
551
552 if (pbm->chip_type == PBM_CHIP_TYPE_SABRE)
553 dp = dp->parent;
554
555 op = of_find_device_by_node(dp);
556 if (!op)
557 return;
558
559 /* Sabre/Hummingbird IRQ property layout is:
560 * 0: PCI ERR
561 * 1: UE ERR
562 * 2: CE ERR
563 * 3: POWER FAIL
564 */
565 if (op->num_irqs < 4)
566 return;
567
568 /* We clear the error bits in the appropriate AFSR before
569 * registering the handler so that we don't get spurious
570 * interrupts.
571 */
572 sabre_write(base + SABRE_UE_AFSR,
573 (SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR |
574 SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR |
575 SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE));
576
577 err = request_irq(op->irqs[1], sabre_ue_intr, 0, "SABRE_UE", pbm);
578 if (err)
579 printk(KERN_WARNING "%s: Couldn't register UE, err=%d.\n",
580 pbm->name, err);
581
582 sabre_write(base + SABRE_CE_AFSR,
583 (SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR |
584 SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR));
585
586 err = request_irq(op->irqs[2], sabre_ce_intr, 0, "SABRE_CE", pbm);
587 if (err)
588 printk(KERN_WARNING "%s: Couldn't register CE, err=%d.\n",
589 pbm->name, err);
590 err = request_irq(op->irqs[0], sabre_pcierr_intr, 0,
591 "SABRE_PCIERR", pbm);
592 if (err)
593 printk(KERN_WARNING "%s: Couldn't register PCIERR, err=%d.\n",
594 pbm->name, err);
595
596 tmp = sabre_read(base + SABRE_PCICTRL);
597 tmp |= SABRE_PCICTRL_ERREN;
598 sabre_write(base + SABRE_PCICTRL, tmp);
599 }
600
601 static void apb_init(struct pci_bus *sabre_bus)
602 {
603 struct pci_dev *pdev;
604
605 list_for_each_entry(pdev, &sabre_bus->devices, bus_list) {
606 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
607 pdev->device == PCI_DEVICE_ID_SUN_SIMBA) {
608 u16 word16;
609
610 pci_read_config_word(pdev, PCI_COMMAND, &word16);
611 word16 |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY |
612 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY |
613 PCI_COMMAND_IO;
614 pci_write_config_word(pdev, PCI_COMMAND, word16);
615
616 /* Status register bits are "write 1 to clear". */
617 pci_write_config_word(pdev, PCI_STATUS, 0xffff);
618 pci_write_config_word(pdev, PCI_SEC_STATUS, 0xffff);
619
620 /* Use a primary/seconday latency timer value
621 * of 64.
622 */
623 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
624 pci_write_config_byte(pdev, PCI_SEC_LATENCY_TIMER, 64);
625
626 /* Enable reporting/forwarding of master aborts,
627 * parity, and SERR.
628 */
629 pci_write_config_byte(pdev, PCI_BRIDGE_CONTROL,
630 (PCI_BRIDGE_CTL_PARITY |
631 PCI_BRIDGE_CTL_SERR |
632 PCI_BRIDGE_CTL_MASTER_ABORT));
633 }
634 }
635 }
636
637 static void __init sabre_scan_bus(struct pci_pbm_info *pbm)
638 {
639 static int once;
640
641 /* The APB bridge speaks to the Sabre host PCI bridge
642 * at 66Mhz, but the front side of APB runs at 33Mhz
643 * for both segments.
644 *
645 * Hummingbird systems do not use APB, so they run
646 * at 66MHZ.
647 */
648 if (hummingbird_p)
649 pbm->is_66mhz_capable = 1;
650 else
651 pbm->is_66mhz_capable = 0;
652
653 /* This driver has not been verified to handle
654 * multiple SABREs yet, so trap this.
655 *
656 * Also note that the SABRE host bridge is hardwired
657 * to live at bus 0.
658 */
659 if (once != 0) {
660 printk(KERN_ERR PFX "Multiple controllers unsupported.\n");
661 return;
662 }
663 once++;
664
665 pbm->pci_bus = pci_scan_one_pbm(pbm);
666 if (!pbm->pci_bus)
667 return;
668
669 sabre_root_bus = pbm->pci_bus;
670
671 apb_init(pbm->pci_bus);
672
673 sabre_register_error_handlers(pbm);
674 }
675
676 static int sabre_iommu_init(struct pci_pbm_info *pbm,
677 int tsbsize, unsigned long dvma_offset,
678 u32 dma_mask)
679 {
680 struct iommu *iommu = pbm->iommu;
681 unsigned long i;
682 u64 control;
683 int err;
684
685 /* Register addresses. */
686 iommu->iommu_control = pbm->controller_regs + SABRE_IOMMU_CONTROL;
687 iommu->iommu_tsbbase = pbm->controller_regs + SABRE_IOMMU_TSBBASE;
688 iommu->iommu_flush = pbm->controller_regs + SABRE_IOMMU_FLUSH;
689 iommu->iommu_tags = iommu->iommu_flush + (0xa580UL - 0x0210UL);
690 iommu->write_complete_reg = pbm->controller_regs + SABRE_WRSYNC;
691 /* Sabre's IOMMU lacks ctx flushing. */
692 iommu->iommu_ctxflush = 0;
693
694 /* Invalidate TLB Entries. */
695 control = sabre_read(pbm->controller_regs + SABRE_IOMMU_CONTROL);
696 control |= SABRE_IOMMUCTRL_DENAB;
697 sabre_write(pbm->controller_regs + SABRE_IOMMU_CONTROL, control);
698
699 for(i = 0; i < 16; i++) {
700 sabre_write(pbm->controller_regs + SABRE_IOMMU_TAG + (i * 8UL), 0);
701 sabre_write(pbm->controller_regs + SABRE_IOMMU_DATA + (i * 8UL), 0);
702 }
703
704 /* Leave diag mode enabled for full-flushing done
705 * in pci_iommu.c
706 */
707 err = iommu_table_init(iommu, tsbsize * 1024 * 8,
708 dvma_offset, dma_mask, pbm->numa_node);
709 if (err) {
710 printk(KERN_ERR PFX "iommu_table_init() failed\n");
711 return err;
712 }
713
714 sabre_write(pbm->controller_regs + SABRE_IOMMU_TSBBASE,
715 __pa(iommu->page_table));
716
717 control = sabre_read(pbm->controller_regs + SABRE_IOMMU_CONTROL);
718 control &= ~(SABRE_IOMMUCTRL_TSBSZ | SABRE_IOMMUCTRL_TBWSZ);
719 control |= SABRE_IOMMUCTRL_ENAB;
720 switch(tsbsize) {
721 case 64:
722 control |= SABRE_IOMMU_TSBSZ_64K;
723 break;
724 case 128:
725 control |= SABRE_IOMMU_TSBSZ_128K;
726 break;
727 default:
728 printk(KERN_ERR PFX "Illegal TSB size %d\n", tsbsize);
729 return -EINVAL;
730 }
731 sabre_write(pbm->controller_regs + SABRE_IOMMU_CONTROL, control);
732
733 return 0;
734 }
735
736 static void __init sabre_pbm_init(struct pci_controller_info *p,
737 struct pci_pbm_info *pbm, struct device_node *dp)
738 {
739 pbm->name = dp->full_name;
740 printk("%s: SABRE PCI Bus Module\n", pbm->name);
741
742 pbm->numa_node = -1;
743
744 pbm->pci_ops = &sun4u_pci_ops;
745 pbm->config_space_reg_bits = 8;
746
747 pbm->index = pci_num_pbms++;
748
749 pbm->chip_type = PBM_CHIP_TYPE_SABRE;
750 pbm->parent = p;
751 pbm->prom_node = dp;
752 pci_get_pbm_props(pbm);
753
754 pci_determine_mem_io_space(pbm);
755
756 sabre_scan_bus(pbm);
757 }
758
759 static int __devinit sabre_probe(struct of_device *op,
760 const struct of_device_id *match)
761 {
762 const struct linux_prom64_registers *pr_regs;
763 struct device_node *dp = op->node;
764 struct pci_controller_info *p;
765 struct pci_pbm_info *pbm;
766 u32 upa_portid, dma_mask;
767 struct iommu *iommu;
768 int tsbsize, err;
769 const u32 *vdma;
770 u64 clear_irq;
771
772 hummingbird_p = (match->data != NULL);
773 if (!hummingbird_p) {
774 struct device_node *cpu_dp;
775
776 /* Of course, Sun has to encode things a thousand
777 * different ways, inconsistently.
778 */
779 for_each_node_by_type(cpu_dp, "cpu") {
780 if (!strcmp(cpu_dp->name, "SUNW,UltraSPARC-IIe"))
781 hummingbird_p = 1;
782 }
783 }
784
785 err = -ENOMEM;
786 p = kzalloc(sizeof(*p), GFP_ATOMIC);
787 if (!p) {
788 printk(KERN_ERR PFX "Cannot allocate controller info.\n");
789 goto out_free;
790 }
791
792 iommu = kzalloc(sizeof(*iommu), GFP_ATOMIC);
793 if (!iommu) {
794 printk(KERN_ERR PFX "Cannot allocate PBM iommu.\n");
795 goto out_free;
796 }
797
798 pbm = &p->pbm_A;
799 pbm->iommu = iommu;
800
801 upa_portid = of_getintprop_default(dp, "upa-portid", 0xff);
802
803 pbm->next = pci_pbm_root;
804 pci_pbm_root = pbm;
805
806 pbm->portid = upa_portid;
807
808 /*
809 * Map in SABRE register set and report the presence of this SABRE.
810 */
811
812 pr_regs = of_get_property(dp, "reg", NULL);
813 err = -ENODEV;
814 if (!pr_regs) {
815 printk(KERN_ERR PFX "No reg property\n");
816 goto out_free;
817 }
818
819 /*
820 * First REG in property is base of entire SABRE register space.
821 */
822 pbm->controller_regs = pr_regs[0].phys_addr;
823
824 /* Clear interrupts */
825
826 /* PCI first */
827 for (clear_irq = SABRE_ICLR_A_SLOT0; clear_irq < SABRE_ICLR_B_SLOT0 + 0x80; clear_irq += 8)
828 sabre_write(pbm->controller_regs + clear_irq, 0x0UL);
829
830 /* Then OBIO */
831 for (clear_irq = SABRE_ICLR_SCSI; clear_irq < SABRE_ICLR_SCSI + 0x80; clear_irq += 8)
832 sabre_write(pbm->controller_regs + clear_irq, 0x0UL);
833
834 /* Error interrupts are enabled later after the bus scan. */
835 sabre_write(pbm->controller_regs + SABRE_PCICTRL,
836 (SABRE_PCICTRL_MRLEN | SABRE_PCICTRL_SERR |
837 SABRE_PCICTRL_ARBPARK | SABRE_PCICTRL_AEN));
838
839 /* Now map in PCI config space for entire SABRE. */
840 pbm->config_space =
841 (pbm->controller_regs + SABRE_CONFIGSPACE);
842
843 vdma = of_get_property(dp, "virtual-dma", NULL);
844 if (!vdma) {
845 printk(KERN_ERR PFX "No virtual-dma property\n");
846 goto out_free;
847 }
848
849 dma_mask = vdma[0];
850 switch(vdma[1]) {
851 case 0x20000000:
852 dma_mask |= 0x1fffffff;
853 tsbsize = 64;
854 break;
855 case 0x40000000:
856 dma_mask |= 0x3fffffff;
857 tsbsize = 128;
858 break;
859
860 case 0x80000000:
861 dma_mask |= 0x7fffffff;
862 tsbsize = 128;
863 break;
864 default:
865 printk(KERN_ERR PFX "Strange virtual-dma size.\n");
866 goto out_free;
867 }
868
869 err = sabre_iommu_init(pbm, tsbsize, vdma[0], dma_mask);
870 if (err)
871 goto out_free;
872
873 /*
874 * Look for APB underneath.
875 */
876 sabre_pbm_init(p, pbm, dp);
877 return 0;
878
879 out_free:
880 if (p) {
881 if (p->pbm_A.iommu)
882 kfree(p->pbm_A.iommu);
883 kfree(p);
884 }
885 return err;
886 }
887
888 static struct of_device_id __initdata sabre_match[] = {
889 {
890 .name = "pci",
891 .compatible = "pci108e,a001",
892 .data = (void *) 1,
893 },
894 {
895 .name = "pci",
896 .compatible = "pci108e,a000",
897 },
898 {},
899 };
900
901 static struct of_platform_driver sabre_driver = {
902 .name = DRIVER_NAME,
903 .match_table = sabre_match,
904 .probe = sabre_probe,
905 };
906
907 static int __init sabre_init(void)
908 {
909 return of_register_driver(&sabre_driver, &of_bus_type);
910 }
911
912 subsys_initcall(sabre_init);
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