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Consolidate of_find_node_by routines
[mirror_ubuntu-artful-kernel.git] / arch / sparc64 / kernel / prom.c
1 /*
2 * Procedures for creating, accessing and interpreting the device tree.
3 *
4 * Paul Mackerras August 1996.
5 * Copyright (C) 1996-2005 Paul Mackerras.
6 *
7 * Adapted for 64bit PowerPC by Dave Engebretsen and Peter Bergner.
8 * {engebret|bergner}@us.ibm.com
9 *
10 * Adapted for sparc64 by David S. Miller davem@davemloft.net
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version
15 * 2 of the License, or (at your option) any later version.
16 */
17
18 #include <linux/kernel.h>
19 #include <linux/types.h>
20 #include <linux/string.h>
21 #include <linux/mm.h>
22 #include <linux/bootmem.h>
23 #include <linux/module.h>
24
25 #include <asm/prom.h>
26 #include <asm/of_device.h>
27 #include <asm/oplib.h>
28 #include <asm/irq.h>
29 #include <asm/asi.h>
30 #include <asm/upa.h>
31 #include <asm/smp.h>
32
33 extern struct device_node *allnodes; /* temporary while merging */
34
35 extern rwlock_t devtree_lock; /* temporary while merging */
36
37 struct device_node *of_find_node_by_phandle(phandle handle)
38 {
39 struct device_node *np;
40
41 for (np = allnodes; np != 0; np = np->allnext)
42 if (np->node == handle)
43 break;
44
45 return np;
46 }
47 EXPORT_SYMBOL(of_find_node_by_phandle);
48
49 int of_getintprop_default(struct device_node *np, const char *name, int def)
50 {
51 struct property *prop;
52 int len;
53
54 prop = of_find_property(np, name, &len);
55 if (!prop || len != 4)
56 return def;
57
58 return *(int *) prop->value;
59 }
60 EXPORT_SYMBOL(of_getintprop_default);
61
62 int of_set_property(struct device_node *dp, const char *name, void *val, int len)
63 {
64 struct property **prevp;
65 void *new_val;
66 int err;
67
68 new_val = kmalloc(len, GFP_KERNEL);
69 if (!new_val)
70 return -ENOMEM;
71
72 memcpy(new_val, val, len);
73
74 err = -ENODEV;
75
76 write_lock(&devtree_lock);
77 prevp = &dp->properties;
78 while (*prevp) {
79 struct property *prop = *prevp;
80
81 if (!strcasecmp(prop->name, name)) {
82 void *old_val = prop->value;
83 int ret;
84
85 ret = prom_setprop(dp->node, name, val, len);
86 err = -EINVAL;
87 if (ret >= 0) {
88 prop->value = new_val;
89 prop->length = len;
90
91 if (OF_IS_DYNAMIC(prop))
92 kfree(old_val);
93
94 OF_MARK_DYNAMIC(prop);
95
96 err = 0;
97 }
98 break;
99 }
100 prevp = &(*prevp)->next;
101 }
102 write_unlock(&devtree_lock);
103
104 /* XXX Upate procfs if necessary... */
105
106 return err;
107 }
108 EXPORT_SYMBOL(of_set_property);
109
110 static unsigned int prom_early_allocated;
111
112 static void * __init prom_early_alloc(unsigned long size)
113 {
114 void *ret;
115
116 ret = __alloc_bootmem(size, SMP_CACHE_BYTES, 0UL);
117 if (ret != NULL)
118 memset(ret, 0, size);
119
120 prom_early_allocated += size;
121
122 return ret;
123 }
124
125 #ifdef CONFIG_PCI
126 /* PSYCHO interrupt mapping support. */
127 #define PSYCHO_IMAP_A_SLOT0 0x0c00UL
128 #define PSYCHO_IMAP_B_SLOT0 0x0c20UL
129 static unsigned long psycho_pcislot_imap_offset(unsigned long ino)
130 {
131 unsigned int bus = (ino & 0x10) >> 4;
132 unsigned int slot = (ino & 0x0c) >> 2;
133
134 if (bus == 0)
135 return PSYCHO_IMAP_A_SLOT0 + (slot * 8);
136 else
137 return PSYCHO_IMAP_B_SLOT0 + (slot * 8);
138 }
139
140 #define PSYCHO_IMAP_SCSI 0x1000UL
141 #define PSYCHO_IMAP_ETH 0x1008UL
142 #define PSYCHO_IMAP_BPP 0x1010UL
143 #define PSYCHO_IMAP_AU_REC 0x1018UL
144 #define PSYCHO_IMAP_AU_PLAY 0x1020UL
145 #define PSYCHO_IMAP_PFAIL 0x1028UL
146 #define PSYCHO_IMAP_KMS 0x1030UL
147 #define PSYCHO_IMAP_FLPY 0x1038UL
148 #define PSYCHO_IMAP_SHW 0x1040UL
149 #define PSYCHO_IMAP_KBD 0x1048UL
150 #define PSYCHO_IMAP_MS 0x1050UL
151 #define PSYCHO_IMAP_SER 0x1058UL
152 #define PSYCHO_IMAP_TIM0 0x1060UL
153 #define PSYCHO_IMAP_TIM1 0x1068UL
154 #define PSYCHO_IMAP_UE 0x1070UL
155 #define PSYCHO_IMAP_CE 0x1078UL
156 #define PSYCHO_IMAP_A_ERR 0x1080UL
157 #define PSYCHO_IMAP_B_ERR 0x1088UL
158 #define PSYCHO_IMAP_PMGMT 0x1090UL
159 #define PSYCHO_IMAP_GFX 0x1098UL
160 #define PSYCHO_IMAP_EUPA 0x10a0UL
161
162 static unsigned long __psycho_onboard_imap_off[] = {
163 /*0x20*/ PSYCHO_IMAP_SCSI,
164 /*0x21*/ PSYCHO_IMAP_ETH,
165 /*0x22*/ PSYCHO_IMAP_BPP,
166 /*0x23*/ PSYCHO_IMAP_AU_REC,
167 /*0x24*/ PSYCHO_IMAP_AU_PLAY,
168 /*0x25*/ PSYCHO_IMAP_PFAIL,
169 /*0x26*/ PSYCHO_IMAP_KMS,
170 /*0x27*/ PSYCHO_IMAP_FLPY,
171 /*0x28*/ PSYCHO_IMAP_SHW,
172 /*0x29*/ PSYCHO_IMAP_KBD,
173 /*0x2a*/ PSYCHO_IMAP_MS,
174 /*0x2b*/ PSYCHO_IMAP_SER,
175 /*0x2c*/ PSYCHO_IMAP_TIM0,
176 /*0x2d*/ PSYCHO_IMAP_TIM1,
177 /*0x2e*/ PSYCHO_IMAP_UE,
178 /*0x2f*/ PSYCHO_IMAP_CE,
179 /*0x30*/ PSYCHO_IMAP_A_ERR,
180 /*0x31*/ PSYCHO_IMAP_B_ERR,
181 /*0x32*/ PSYCHO_IMAP_PMGMT,
182 /*0x33*/ PSYCHO_IMAP_GFX,
183 /*0x34*/ PSYCHO_IMAP_EUPA,
184 };
185 #define PSYCHO_ONBOARD_IRQ_BASE 0x20
186 #define PSYCHO_ONBOARD_IRQ_LAST 0x34
187 #define psycho_onboard_imap_offset(__ino) \
188 __psycho_onboard_imap_off[(__ino) - PSYCHO_ONBOARD_IRQ_BASE]
189
190 #define PSYCHO_ICLR_A_SLOT0 0x1400UL
191 #define PSYCHO_ICLR_SCSI 0x1800UL
192
193 #define psycho_iclr_offset(ino) \
194 ((ino & 0x20) ? (PSYCHO_ICLR_SCSI + (((ino) & 0x1f) << 3)) : \
195 (PSYCHO_ICLR_A_SLOT0 + (((ino) & 0x1f)<<3)))
196
197 static unsigned int psycho_irq_build(struct device_node *dp,
198 unsigned int ino,
199 void *_data)
200 {
201 unsigned long controller_regs = (unsigned long) _data;
202 unsigned long imap, iclr;
203 unsigned long imap_off, iclr_off;
204 int inofixup = 0;
205
206 ino &= 0x3f;
207 if (ino < PSYCHO_ONBOARD_IRQ_BASE) {
208 /* PCI slot */
209 imap_off = psycho_pcislot_imap_offset(ino);
210 } else {
211 /* Onboard device */
212 if (ino > PSYCHO_ONBOARD_IRQ_LAST) {
213 prom_printf("psycho_irq_build: Wacky INO [%x]\n", ino);
214 prom_halt();
215 }
216 imap_off = psycho_onboard_imap_offset(ino);
217 }
218
219 /* Now build the IRQ bucket. */
220 imap = controller_regs + imap_off;
221
222 iclr_off = psycho_iclr_offset(ino);
223 iclr = controller_regs + iclr_off;
224
225 if ((ino & 0x20) == 0)
226 inofixup = ino & 0x03;
227
228 return build_irq(inofixup, iclr, imap);
229 }
230
231 static void __init psycho_irq_trans_init(struct device_node *dp)
232 {
233 const struct linux_prom64_registers *regs;
234
235 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
236 dp->irq_trans->irq_build = psycho_irq_build;
237
238 regs = of_get_property(dp, "reg", NULL);
239 dp->irq_trans->data = (void *) regs[2].phys_addr;
240 }
241
242 #define sabre_read(__reg) \
243 ({ u64 __ret; \
244 __asm__ __volatile__("ldxa [%1] %2, %0" \
245 : "=r" (__ret) \
246 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
247 : "memory"); \
248 __ret; \
249 })
250
251 struct sabre_irq_data {
252 unsigned long controller_regs;
253 unsigned int pci_first_busno;
254 };
255 #define SABRE_CONFIGSPACE 0x001000000UL
256 #define SABRE_WRSYNC 0x1c20UL
257
258 #define SABRE_CONFIG_BASE(CONFIG_SPACE) \
259 (CONFIG_SPACE | (1UL << 24))
260 #define SABRE_CONFIG_ENCODE(BUS, DEVFN, REG) \
261 (((unsigned long)(BUS) << 16) | \
262 ((unsigned long)(DEVFN) << 8) | \
263 ((unsigned long)(REG)))
264
265 /* When a device lives behind a bridge deeper in the PCI bus topology
266 * than APB, a special sequence must run to make sure all pending DMA
267 * transfers at the time of IRQ delivery are visible in the coherency
268 * domain by the cpu. This sequence is to perform a read on the far
269 * side of the non-APB bridge, then perform a read of Sabre's DMA
270 * write-sync register.
271 */
272 static void sabre_wsync_handler(unsigned int ino, void *_arg1, void *_arg2)
273 {
274 unsigned int phys_hi = (unsigned int) (unsigned long) _arg1;
275 struct sabre_irq_data *irq_data = _arg2;
276 unsigned long controller_regs = irq_data->controller_regs;
277 unsigned long sync_reg = controller_regs + SABRE_WRSYNC;
278 unsigned long config_space = controller_regs + SABRE_CONFIGSPACE;
279 unsigned int bus, devfn;
280 u16 _unused;
281
282 config_space = SABRE_CONFIG_BASE(config_space);
283
284 bus = (phys_hi >> 16) & 0xff;
285 devfn = (phys_hi >> 8) & 0xff;
286
287 config_space |= SABRE_CONFIG_ENCODE(bus, devfn, 0x00);
288
289 __asm__ __volatile__("membar #Sync\n\t"
290 "lduha [%1] %2, %0\n\t"
291 "membar #Sync"
292 : "=r" (_unused)
293 : "r" ((u16 *) config_space),
294 "i" (ASI_PHYS_BYPASS_EC_E_L)
295 : "memory");
296
297 sabre_read(sync_reg);
298 }
299
300 #define SABRE_IMAP_A_SLOT0 0x0c00UL
301 #define SABRE_IMAP_B_SLOT0 0x0c20UL
302 #define SABRE_IMAP_SCSI 0x1000UL
303 #define SABRE_IMAP_ETH 0x1008UL
304 #define SABRE_IMAP_BPP 0x1010UL
305 #define SABRE_IMAP_AU_REC 0x1018UL
306 #define SABRE_IMAP_AU_PLAY 0x1020UL
307 #define SABRE_IMAP_PFAIL 0x1028UL
308 #define SABRE_IMAP_KMS 0x1030UL
309 #define SABRE_IMAP_FLPY 0x1038UL
310 #define SABRE_IMAP_SHW 0x1040UL
311 #define SABRE_IMAP_KBD 0x1048UL
312 #define SABRE_IMAP_MS 0x1050UL
313 #define SABRE_IMAP_SER 0x1058UL
314 #define SABRE_IMAP_UE 0x1070UL
315 #define SABRE_IMAP_CE 0x1078UL
316 #define SABRE_IMAP_PCIERR 0x1080UL
317 #define SABRE_IMAP_GFX 0x1098UL
318 #define SABRE_IMAP_EUPA 0x10a0UL
319 #define SABRE_ICLR_A_SLOT0 0x1400UL
320 #define SABRE_ICLR_B_SLOT0 0x1480UL
321 #define SABRE_ICLR_SCSI 0x1800UL
322 #define SABRE_ICLR_ETH 0x1808UL
323 #define SABRE_ICLR_BPP 0x1810UL
324 #define SABRE_ICLR_AU_REC 0x1818UL
325 #define SABRE_ICLR_AU_PLAY 0x1820UL
326 #define SABRE_ICLR_PFAIL 0x1828UL
327 #define SABRE_ICLR_KMS 0x1830UL
328 #define SABRE_ICLR_FLPY 0x1838UL
329 #define SABRE_ICLR_SHW 0x1840UL
330 #define SABRE_ICLR_KBD 0x1848UL
331 #define SABRE_ICLR_MS 0x1850UL
332 #define SABRE_ICLR_SER 0x1858UL
333 #define SABRE_ICLR_UE 0x1870UL
334 #define SABRE_ICLR_CE 0x1878UL
335 #define SABRE_ICLR_PCIERR 0x1880UL
336
337 static unsigned long sabre_pcislot_imap_offset(unsigned long ino)
338 {
339 unsigned int bus = (ino & 0x10) >> 4;
340 unsigned int slot = (ino & 0x0c) >> 2;
341
342 if (bus == 0)
343 return SABRE_IMAP_A_SLOT0 + (slot * 8);
344 else
345 return SABRE_IMAP_B_SLOT0 + (slot * 8);
346 }
347
348 static unsigned long __sabre_onboard_imap_off[] = {
349 /*0x20*/ SABRE_IMAP_SCSI,
350 /*0x21*/ SABRE_IMAP_ETH,
351 /*0x22*/ SABRE_IMAP_BPP,
352 /*0x23*/ SABRE_IMAP_AU_REC,
353 /*0x24*/ SABRE_IMAP_AU_PLAY,
354 /*0x25*/ SABRE_IMAP_PFAIL,
355 /*0x26*/ SABRE_IMAP_KMS,
356 /*0x27*/ SABRE_IMAP_FLPY,
357 /*0x28*/ SABRE_IMAP_SHW,
358 /*0x29*/ SABRE_IMAP_KBD,
359 /*0x2a*/ SABRE_IMAP_MS,
360 /*0x2b*/ SABRE_IMAP_SER,
361 /*0x2c*/ 0 /* reserved */,
362 /*0x2d*/ 0 /* reserved */,
363 /*0x2e*/ SABRE_IMAP_UE,
364 /*0x2f*/ SABRE_IMAP_CE,
365 /*0x30*/ SABRE_IMAP_PCIERR,
366 /*0x31*/ 0 /* reserved */,
367 /*0x32*/ 0 /* reserved */,
368 /*0x33*/ SABRE_IMAP_GFX,
369 /*0x34*/ SABRE_IMAP_EUPA,
370 };
371 #define SABRE_ONBOARD_IRQ_BASE 0x20
372 #define SABRE_ONBOARD_IRQ_LAST 0x30
373 #define sabre_onboard_imap_offset(__ino) \
374 __sabre_onboard_imap_off[(__ino) - SABRE_ONBOARD_IRQ_BASE]
375
376 #define sabre_iclr_offset(ino) \
377 ((ino & 0x20) ? (SABRE_ICLR_SCSI + (((ino) & 0x1f) << 3)) : \
378 (SABRE_ICLR_A_SLOT0 + (((ino) & 0x1f)<<3)))
379
380 static int sabre_device_needs_wsync(struct device_node *dp)
381 {
382 struct device_node *parent = dp->parent;
383 const char *parent_model, *parent_compat;
384
385 /* This traversal up towards the root is meant to
386 * handle two cases:
387 *
388 * 1) non-PCI bus sitting under PCI, such as 'ebus'
389 * 2) the PCI controller interrupts themselves, which
390 * will use the sabre_irq_build but do not need
391 * the DMA synchronization handling
392 */
393 while (parent) {
394 if (!strcmp(parent->type, "pci"))
395 break;
396 parent = parent->parent;
397 }
398
399 if (!parent)
400 return 0;
401
402 parent_model = of_get_property(parent,
403 "model", NULL);
404 if (parent_model &&
405 (!strcmp(parent_model, "SUNW,sabre") ||
406 !strcmp(parent_model, "SUNW,simba")))
407 return 0;
408
409 parent_compat = of_get_property(parent,
410 "compatible", NULL);
411 if (parent_compat &&
412 (!strcmp(parent_compat, "pci108e,a000") ||
413 !strcmp(parent_compat, "pci108e,a001")))
414 return 0;
415
416 return 1;
417 }
418
419 static unsigned int sabre_irq_build(struct device_node *dp,
420 unsigned int ino,
421 void *_data)
422 {
423 struct sabre_irq_data *irq_data = _data;
424 unsigned long controller_regs = irq_data->controller_regs;
425 const struct linux_prom_pci_registers *regs;
426 unsigned long imap, iclr;
427 unsigned long imap_off, iclr_off;
428 int inofixup = 0;
429 int virt_irq;
430
431 ino &= 0x3f;
432 if (ino < SABRE_ONBOARD_IRQ_BASE) {
433 /* PCI slot */
434 imap_off = sabre_pcislot_imap_offset(ino);
435 } else {
436 /* onboard device */
437 if (ino > SABRE_ONBOARD_IRQ_LAST) {
438 prom_printf("sabre_irq_build: Wacky INO [%x]\n", ino);
439 prom_halt();
440 }
441 imap_off = sabre_onboard_imap_offset(ino);
442 }
443
444 /* Now build the IRQ bucket. */
445 imap = controller_regs + imap_off;
446
447 iclr_off = sabre_iclr_offset(ino);
448 iclr = controller_regs + iclr_off;
449
450 if ((ino & 0x20) == 0)
451 inofixup = ino & 0x03;
452
453 virt_irq = build_irq(inofixup, iclr, imap);
454
455 /* If the parent device is a PCI<->PCI bridge other than
456 * APB, we have to install a pre-handler to ensure that
457 * all pending DMA is drained before the interrupt handler
458 * is run.
459 */
460 regs = of_get_property(dp, "reg", NULL);
461 if (regs && sabre_device_needs_wsync(dp)) {
462 irq_install_pre_handler(virt_irq,
463 sabre_wsync_handler,
464 (void *) (long) regs->phys_hi,
465 (void *) irq_data);
466 }
467
468 return virt_irq;
469 }
470
471 static void __init sabre_irq_trans_init(struct device_node *dp)
472 {
473 const struct linux_prom64_registers *regs;
474 struct sabre_irq_data *irq_data;
475 const u32 *busrange;
476
477 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
478 dp->irq_trans->irq_build = sabre_irq_build;
479
480 irq_data = prom_early_alloc(sizeof(struct sabre_irq_data));
481
482 regs = of_get_property(dp, "reg", NULL);
483 irq_data->controller_regs = regs[0].phys_addr;
484
485 busrange = of_get_property(dp, "bus-range", NULL);
486 irq_data->pci_first_busno = busrange[0];
487
488 dp->irq_trans->data = irq_data;
489 }
490
491 /* SCHIZO interrupt mapping support. Unlike Psycho, for this controller the
492 * imap/iclr registers are per-PBM.
493 */
494 #define SCHIZO_IMAP_BASE 0x1000UL
495 #define SCHIZO_ICLR_BASE 0x1400UL
496
497 static unsigned long schizo_imap_offset(unsigned long ino)
498 {
499 return SCHIZO_IMAP_BASE + (ino * 8UL);
500 }
501
502 static unsigned long schizo_iclr_offset(unsigned long ino)
503 {
504 return SCHIZO_ICLR_BASE + (ino * 8UL);
505 }
506
507 static unsigned long schizo_ino_to_iclr(unsigned long pbm_regs,
508 unsigned int ino)
509 {
510
511 return pbm_regs + schizo_iclr_offset(ino);
512 }
513
514 static unsigned long schizo_ino_to_imap(unsigned long pbm_regs,
515 unsigned int ino)
516 {
517 return pbm_regs + schizo_imap_offset(ino);
518 }
519
520 #define schizo_read(__reg) \
521 ({ u64 __ret; \
522 __asm__ __volatile__("ldxa [%1] %2, %0" \
523 : "=r" (__ret) \
524 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
525 : "memory"); \
526 __ret; \
527 })
528 #define schizo_write(__reg, __val) \
529 __asm__ __volatile__("stxa %0, [%1] %2" \
530 : /* no outputs */ \
531 : "r" (__val), "r" (__reg), \
532 "i" (ASI_PHYS_BYPASS_EC_E) \
533 : "memory")
534
535 static void tomatillo_wsync_handler(unsigned int ino, void *_arg1, void *_arg2)
536 {
537 unsigned long sync_reg = (unsigned long) _arg2;
538 u64 mask = 1UL << (ino & IMAP_INO);
539 u64 val;
540 int limit;
541
542 schizo_write(sync_reg, mask);
543
544 limit = 100000;
545 val = 0;
546 while (--limit) {
547 val = schizo_read(sync_reg);
548 if (!(val & mask))
549 break;
550 }
551 if (limit <= 0) {
552 printk("tomatillo_wsync_handler: DMA won't sync [%lx:%lx]\n",
553 val, mask);
554 }
555
556 if (_arg1) {
557 static unsigned char cacheline[64]
558 __attribute__ ((aligned (64)));
559
560 __asm__ __volatile__("rd %%fprs, %0\n\t"
561 "or %0, %4, %1\n\t"
562 "wr %1, 0x0, %%fprs\n\t"
563 "stda %%f0, [%5] %6\n\t"
564 "wr %0, 0x0, %%fprs\n\t"
565 "membar #Sync"
566 : "=&r" (mask), "=&r" (val)
567 : "0" (mask), "1" (val),
568 "i" (FPRS_FEF), "r" (&cacheline[0]),
569 "i" (ASI_BLK_COMMIT_P));
570 }
571 }
572
573 struct schizo_irq_data {
574 unsigned long pbm_regs;
575 unsigned long sync_reg;
576 u32 portid;
577 int chip_version;
578 };
579
580 static unsigned int schizo_irq_build(struct device_node *dp,
581 unsigned int ino,
582 void *_data)
583 {
584 struct schizo_irq_data *irq_data = _data;
585 unsigned long pbm_regs = irq_data->pbm_regs;
586 unsigned long imap, iclr;
587 int ign_fixup;
588 int virt_irq;
589 int is_tomatillo;
590
591 ino &= 0x3f;
592
593 /* Now build the IRQ bucket. */
594 imap = schizo_ino_to_imap(pbm_regs, ino);
595 iclr = schizo_ino_to_iclr(pbm_regs, ino);
596
597 /* On Schizo, no inofixup occurs. This is because each
598 * INO has it's own IMAP register. On Psycho and Sabre
599 * there is only one IMAP register for each PCI slot even
600 * though four different INOs can be generated by each
601 * PCI slot.
602 *
603 * But, for JBUS variants (essentially, Tomatillo), we have
604 * to fixup the lowest bit of the interrupt group number.
605 */
606 ign_fixup = 0;
607
608 is_tomatillo = (irq_data->sync_reg != 0UL);
609
610 if (is_tomatillo) {
611 if (irq_data->portid & 1)
612 ign_fixup = (1 << 6);
613 }
614
615 virt_irq = build_irq(ign_fixup, iclr, imap);
616
617 if (is_tomatillo) {
618 irq_install_pre_handler(virt_irq,
619 tomatillo_wsync_handler,
620 ((irq_data->chip_version <= 4) ?
621 (void *) 1 : (void *) 0),
622 (void *) irq_data->sync_reg);
623 }
624
625 return virt_irq;
626 }
627
628 static void __init __schizo_irq_trans_init(struct device_node *dp,
629 int is_tomatillo)
630 {
631 const struct linux_prom64_registers *regs;
632 struct schizo_irq_data *irq_data;
633
634 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
635 dp->irq_trans->irq_build = schizo_irq_build;
636
637 irq_data = prom_early_alloc(sizeof(struct schizo_irq_data));
638
639 regs = of_get_property(dp, "reg", NULL);
640 dp->irq_trans->data = irq_data;
641
642 irq_data->pbm_regs = regs[0].phys_addr;
643 if (is_tomatillo)
644 irq_data->sync_reg = regs[3].phys_addr + 0x1a18UL;
645 else
646 irq_data->sync_reg = 0UL;
647 irq_data->portid = of_getintprop_default(dp, "portid", 0);
648 irq_data->chip_version = of_getintprop_default(dp, "version#", 0);
649 }
650
651 static void __init schizo_irq_trans_init(struct device_node *dp)
652 {
653 __schizo_irq_trans_init(dp, 0);
654 }
655
656 static void __init tomatillo_irq_trans_init(struct device_node *dp)
657 {
658 __schizo_irq_trans_init(dp, 1);
659 }
660
661 static unsigned int pci_sun4v_irq_build(struct device_node *dp,
662 unsigned int devino,
663 void *_data)
664 {
665 u32 devhandle = (u32) (unsigned long) _data;
666
667 return sun4v_build_irq(devhandle, devino);
668 }
669
670 static void __init pci_sun4v_irq_trans_init(struct device_node *dp)
671 {
672 const struct linux_prom64_registers *regs;
673
674 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
675 dp->irq_trans->irq_build = pci_sun4v_irq_build;
676
677 regs = of_get_property(dp, "reg", NULL);
678 dp->irq_trans->data = (void *) (unsigned long)
679 ((regs->phys_addr >> 32UL) & 0x0fffffff);
680 }
681
682 struct fire_irq_data {
683 unsigned long pbm_regs;
684 u32 portid;
685 };
686
687 #define FIRE_IMAP_BASE 0x001000
688 #define FIRE_ICLR_BASE 0x001400
689
690 static unsigned long fire_imap_offset(unsigned long ino)
691 {
692 return FIRE_IMAP_BASE + (ino * 8UL);
693 }
694
695 static unsigned long fire_iclr_offset(unsigned long ino)
696 {
697 return FIRE_ICLR_BASE + (ino * 8UL);
698 }
699
700 static unsigned long fire_ino_to_iclr(unsigned long pbm_regs,
701 unsigned int ino)
702 {
703 return pbm_regs + fire_iclr_offset(ino);
704 }
705
706 static unsigned long fire_ino_to_imap(unsigned long pbm_regs,
707 unsigned int ino)
708 {
709 return pbm_regs + fire_imap_offset(ino);
710 }
711
712 static unsigned int fire_irq_build(struct device_node *dp,
713 unsigned int ino,
714 void *_data)
715 {
716 struct fire_irq_data *irq_data = _data;
717 unsigned long pbm_regs = irq_data->pbm_regs;
718 unsigned long imap, iclr;
719 unsigned long int_ctrlr;
720
721 ino &= 0x3f;
722
723 /* Now build the IRQ bucket. */
724 imap = fire_ino_to_imap(pbm_regs, ino);
725 iclr = fire_ino_to_iclr(pbm_regs, ino);
726
727 /* Set the interrupt controller number. */
728 int_ctrlr = 1 << 6;
729 upa_writeq(int_ctrlr, imap);
730
731 /* The interrupt map registers do not have an INO field
732 * like other chips do. They return zero in the INO
733 * field, and the interrupt controller number is controlled
734 * in bits 6 to 9. So in order for build_irq() to get
735 * the INO right we pass it in as part of the fixup
736 * which will get added to the map register zero value
737 * read by build_irq().
738 */
739 ino |= (irq_data->portid << 6);
740 ino -= int_ctrlr;
741 return build_irq(ino, iclr, imap);
742 }
743
744 static void __init fire_irq_trans_init(struct device_node *dp)
745 {
746 const struct linux_prom64_registers *regs;
747 struct fire_irq_data *irq_data;
748
749 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
750 dp->irq_trans->irq_build = fire_irq_build;
751
752 irq_data = prom_early_alloc(sizeof(struct fire_irq_data));
753
754 regs = of_get_property(dp, "reg", NULL);
755 dp->irq_trans->data = irq_data;
756
757 irq_data->pbm_regs = regs[0].phys_addr;
758 irq_data->portid = of_getintprop_default(dp, "portid", 0);
759 }
760 #endif /* CONFIG_PCI */
761
762 #ifdef CONFIG_SBUS
763 /* INO number to IMAP register offset for SYSIO external IRQ's.
764 * This should conform to both Sunfire/Wildfire server and Fusion
765 * desktop designs.
766 */
767 #define SYSIO_IMAP_SLOT0 0x2c00UL
768 #define SYSIO_IMAP_SLOT1 0x2c08UL
769 #define SYSIO_IMAP_SLOT2 0x2c10UL
770 #define SYSIO_IMAP_SLOT3 0x2c18UL
771 #define SYSIO_IMAP_SCSI 0x3000UL
772 #define SYSIO_IMAP_ETH 0x3008UL
773 #define SYSIO_IMAP_BPP 0x3010UL
774 #define SYSIO_IMAP_AUDIO 0x3018UL
775 #define SYSIO_IMAP_PFAIL 0x3020UL
776 #define SYSIO_IMAP_KMS 0x3028UL
777 #define SYSIO_IMAP_FLPY 0x3030UL
778 #define SYSIO_IMAP_SHW 0x3038UL
779 #define SYSIO_IMAP_KBD 0x3040UL
780 #define SYSIO_IMAP_MS 0x3048UL
781 #define SYSIO_IMAP_SER 0x3050UL
782 #define SYSIO_IMAP_TIM0 0x3060UL
783 #define SYSIO_IMAP_TIM1 0x3068UL
784 #define SYSIO_IMAP_UE 0x3070UL
785 #define SYSIO_IMAP_CE 0x3078UL
786 #define SYSIO_IMAP_SBERR 0x3080UL
787 #define SYSIO_IMAP_PMGMT 0x3088UL
788 #define SYSIO_IMAP_GFX 0x3090UL
789 #define SYSIO_IMAP_EUPA 0x3098UL
790
791 #define bogon ((unsigned long) -1)
792 static unsigned long sysio_irq_offsets[] = {
793 /* SBUS Slot 0 --> 3, level 1 --> 7 */
794 SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
795 SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
796 SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
797 SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
798 SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
799 SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
800 SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
801 SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
802
803 /* Onboard devices (not relevant/used on SunFire). */
804 SYSIO_IMAP_SCSI,
805 SYSIO_IMAP_ETH,
806 SYSIO_IMAP_BPP,
807 bogon,
808 SYSIO_IMAP_AUDIO,
809 SYSIO_IMAP_PFAIL,
810 bogon,
811 bogon,
812 SYSIO_IMAP_KMS,
813 SYSIO_IMAP_FLPY,
814 SYSIO_IMAP_SHW,
815 SYSIO_IMAP_KBD,
816 SYSIO_IMAP_MS,
817 SYSIO_IMAP_SER,
818 bogon,
819 bogon,
820 SYSIO_IMAP_TIM0,
821 SYSIO_IMAP_TIM1,
822 bogon,
823 bogon,
824 SYSIO_IMAP_UE,
825 SYSIO_IMAP_CE,
826 SYSIO_IMAP_SBERR,
827 SYSIO_IMAP_PMGMT,
828 SYSIO_IMAP_GFX,
829 SYSIO_IMAP_EUPA,
830 };
831
832 #undef bogon
833
834 #define NUM_SYSIO_OFFSETS ARRAY_SIZE(sysio_irq_offsets)
835
836 /* Convert Interrupt Mapping register pointer to associated
837 * Interrupt Clear register pointer, SYSIO specific version.
838 */
839 #define SYSIO_ICLR_UNUSED0 0x3400UL
840 #define SYSIO_ICLR_SLOT0 0x3408UL
841 #define SYSIO_ICLR_SLOT1 0x3448UL
842 #define SYSIO_ICLR_SLOT2 0x3488UL
843 #define SYSIO_ICLR_SLOT3 0x34c8UL
844 static unsigned long sysio_imap_to_iclr(unsigned long imap)
845 {
846 unsigned long diff = SYSIO_ICLR_UNUSED0 - SYSIO_IMAP_SLOT0;
847 return imap + diff;
848 }
849
850 static unsigned int sbus_of_build_irq(struct device_node *dp,
851 unsigned int ino,
852 void *_data)
853 {
854 unsigned long reg_base = (unsigned long) _data;
855 const struct linux_prom_registers *regs;
856 unsigned long imap, iclr;
857 int sbus_slot = 0;
858 int sbus_level = 0;
859
860 ino &= 0x3f;
861
862 regs = of_get_property(dp, "reg", NULL);
863 if (regs)
864 sbus_slot = regs->which_io;
865
866 if (ino < 0x20)
867 ino += (sbus_slot * 8);
868
869 imap = sysio_irq_offsets[ino];
870 if (imap == ((unsigned long)-1)) {
871 prom_printf("get_irq_translations: Bad SYSIO INO[%x]\n",
872 ino);
873 prom_halt();
874 }
875 imap += reg_base;
876
877 /* SYSIO inconsistency. For external SLOTS, we have to select
878 * the right ICLR register based upon the lower SBUS irq level
879 * bits.
880 */
881 if (ino >= 0x20) {
882 iclr = sysio_imap_to_iclr(imap);
883 } else {
884 sbus_level = ino & 0x7;
885
886 switch(sbus_slot) {
887 case 0:
888 iclr = reg_base + SYSIO_ICLR_SLOT0;
889 break;
890 case 1:
891 iclr = reg_base + SYSIO_ICLR_SLOT1;
892 break;
893 case 2:
894 iclr = reg_base + SYSIO_ICLR_SLOT2;
895 break;
896 default:
897 case 3:
898 iclr = reg_base + SYSIO_ICLR_SLOT3;
899 break;
900 };
901
902 iclr += ((unsigned long)sbus_level - 1UL) * 8UL;
903 }
904 return build_irq(sbus_level, iclr, imap);
905 }
906
907 static void __init sbus_irq_trans_init(struct device_node *dp)
908 {
909 const struct linux_prom64_registers *regs;
910
911 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
912 dp->irq_trans->irq_build = sbus_of_build_irq;
913
914 regs = of_get_property(dp, "reg", NULL);
915 dp->irq_trans->data = (void *) (unsigned long) regs->phys_addr;
916 }
917 #endif /* CONFIG_SBUS */
918
919
920 static unsigned int central_build_irq(struct device_node *dp,
921 unsigned int ino,
922 void *_data)
923 {
924 struct device_node *central_dp = _data;
925 struct of_device *central_op = of_find_device_by_node(central_dp);
926 struct resource *res;
927 unsigned long imap, iclr;
928 u32 tmp;
929
930 if (!strcmp(dp->name, "eeprom")) {
931 res = &central_op->resource[5];
932 } else if (!strcmp(dp->name, "zs")) {
933 res = &central_op->resource[4];
934 } else if (!strcmp(dp->name, "clock-board")) {
935 res = &central_op->resource[3];
936 } else {
937 return ino;
938 }
939
940 imap = res->start + 0x00UL;
941 iclr = res->start + 0x10UL;
942
943 /* Set the INO state to idle, and disable. */
944 upa_writel(0, iclr);
945 upa_readl(iclr);
946
947 tmp = upa_readl(imap);
948 tmp &= ~0x80000000;
949 upa_writel(tmp, imap);
950
951 return build_irq(0, iclr, imap);
952 }
953
954 static void __init central_irq_trans_init(struct device_node *dp)
955 {
956 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
957 dp->irq_trans->irq_build = central_build_irq;
958
959 dp->irq_trans->data = dp;
960 }
961
962 struct irq_trans {
963 const char *name;
964 void (*init)(struct device_node *);
965 };
966
967 #ifdef CONFIG_PCI
968 static struct irq_trans __initdata pci_irq_trans_table[] = {
969 { "SUNW,sabre", sabre_irq_trans_init },
970 { "pci108e,a000", sabre_irq_trans_init },
971 { "pci108e,a001", sabre_irq_trans_init },
972 { "SUNW,psycho", psycho_irq_trans_init },
973 { "pci108e,8000", psycho_irq_trans_init },
974 { "SUNW,schizo", schizo_irq_trans_init },
975 { "pci108e,8001", schizo_irq_trans_init },
976 { "SUNW,schizo+", schizo_irq_trans_init },
977 { "pci108e,8002", schizo_irq_trans_init },
978 { "SUNW,tomatillo", tomatillo_irq_trans_init },
979 { "pci108e,a801", tomatillo_irq_trans_init },
980 { "SUNW,sun4v-pci", pci_sun4v_irq_trans_init },
981 { "pciex108e,80f0", fire_irq_trans_init },
982 };
983 #endif
984
985 static unsigned int sun4v_vdev_irq_build(struct device_node *dp,
986 unsigned int devino,
987 void *_data)
988 {
989 u32 devhandle = (u32) (unsigned long) _data;
990
991 return sun4v_build_irq(devhandle, devino);
992 }
993
994 static void __init sun4v_vdev_irq_trans_init(struct device_node *dp)
995 {
996 const struct linux_prom64_registers *regs;
997
998 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
999 dp->irq_trans->irq_build = sun4v_vdev_irq_build;
1000
1001 regs = of_get_property(dp, "reg", NULL);
1002 dp->irq_trans->data = (void *) (unsigned long)
1003 ((regs->phys_addr >> 32UL) & 0x0fffffff);
1004 }
1005
1006 static void __init irq_trans_init(struct device_node *dp)
1007 {
1008 #ifdef CONFIG_PCI
1009 const char *model;
1010 int i;
1011 #endif
1012
1013 #ifdef CONFIG_PCI
1014 model = of_get_property(dp, "model", NULL);
1015 if (!model)
1016 model = of_get_property(dp, "compatible", NULL);
1017 if (model) {
1018 for (i = 0; i < ARRAY_SIZE(pci_irq_trans_table); i++) {
1019 struct irq_trans *t = &pci_irq_trans_table[i];
1020
1021 if (!strcmp(model, t->name))
1022 return t->init(dp);
1023 }
1024 }
1025 #endif
1026 #ifdef CONFIG_SBUS
1027 if (!strcmp(dp->name, "sbus") ||
1028 !strcmp(dp->name, "sbi"))
1029 return sbus_irq_trans_init(dp);
1030 #endif
1031 if (!strcmp(dp->name, "fhc") &&
1032 !strcmp(dp->parent->name, "central"))
1033 return central_irq_trans_init(dp);
1034 if (!strcmp(dp->name, "virtual-devices"))
1035 return sun4v_vdev_irq_trans_init(dp);
1036 }
1037
1038 static int is_root_node(const struct device_node *dp)
1039 {
1040 if (!dp)
1041 return 0;
1042
1043 return (dp->parent == NULL);
1044 }
1045
1046 /* The following routines deal with the black magic of fully naming a
1047 * node.
1048 *
1049 * Certain well known named nodes are just the simple name string.
1050 *
1051 * Actual devices have an address specifier appended to the base name
1052 * string, like this "foo@addr". The "addr" can be in any number of
1053 * formats, and the platform plus the type of the node determine the
1054 * format and how it is constructed.
1055 *
1056 * For children of the ROOT node, the naming convention is fixed and
1057 * determined by whether this is a sun4u or sun4v system.
1058 *
1059 * For children of other nodes, it is bus type specific. So
1060 * we walk up the tree until we discover a "device_type" property
1061 * we recognize and we go from there.
1062 *
1063 * As an example, the boot device on my workstation has a full path:
1064 *
1065 * /pci@1e,600000/ide@d/disk@0,0:c
1066 */
1067 static void __init sun4v_path_component(struct device_node *dp, char *tmp_buf)
1068 {
1069 struct linux_prom64_registers *regs;
1070 struct property *rprop;
1071 u32 high_bits, low_bits, type;
1072
1073 rprop = of_find_property(dp, "reg", NULL);
1074 if (!rprop)
1075 return;
1076
1077 regs = rprop->value;
1078 if (!is_root_node(dp->parent)) {
1079 sprintf(tmp_buf, "%s@%x,%x",
1080 dp->name,
1081 (unsigned int) (regs->phys_addr >> 32UL),
1082 (unsigned int) (regs->phys_addr & 0xffffffffUL));
1083 return;
1084 }
1085
1086 type = regs->phys_addr >> 60UL;
1087 high_bits = (regs->phys_addr >> 32UL) & 0x0fffffffUL;
1088 low_bits = (regs->phys_addr & 0xffffffffUL);
1089
1090 if (type == 0 || type == 8) {
1091 const char *prefix = (type == 0) ? "m" : "i";
1092
1093 if (low_bits)
1094 sprintf(tmp_buf, "%s@%s%x,%x",
1095 dp->name, prefix,
1096 high_bits, low_bits);
1097 else
1098 sprintf(tmp_buf, "%s@%s%x",
1099 dp->name,
1100 prefix,
1101 high_bits);
1102 } else if (type == 12) {
1103 sprintf(tmp_buf, "%s@%x",
1104 dp->name, high_bits);
1105 }
1106 }
1107
1108 static void __init sun4u_path_component(struct device_node *dp, char *tmp_buf)
1109 {
1110 struct linux_prom64_registers *regs;
1111 struct property *prop;
1112
1113 prop = of_find_property(dp, "reg", NULL);
1114 if (!prop)
1115 return;
1116
1117 regs = prop->value;
1118 if (!is_root_node(dp->parent)) {
1119 sprintf(tmp_buf, "%s@%x,%x",
1120 dp->name,
1121 (unsigned int) (regs->phys_addr >> 32UL),
1122 (unsigned int) (regs->phys_addr & 0xffffffffUL));
1123 return;
1124 }
1125
1126 prop = of_find_property(dp, "upa-portid", NULL);
1127 if (!prop)
1128 prop = of_find_property(dp, "portid", NULL);
1129 if (prop) {
1130 unsigned long mask = 0xffffffffUL;
1131
1132 if (tlb_type >= cheetah)
1133 mask = 0x7fffff;
1134
1135 sprintf(tmp_buf, "%s@%x,%x",
1136 dp->name,
1137 *(u32 *)prop->value,
1138 (unsigned int) (regs->phys_addr & mask));
1139 }
1140 }
1141
1142 /* "name@slot,offset" */
1143 static void __init sbus_path_component(struct device_node *dp, char *tmp_buf)
1144 {
1145 struct linux_prom_registers *regs;
1146 struct property *prop;
1147
1148 prop = of_find_property(dp, "reg", NULL);
1149 if (!prop)
1150 return;
1151
1152 regs = prop->value;
1153 sprintf(tmp_buf, "%s@%x,%x",
1154 dp->name,
1155 regs->which_io,
1156 regs->phys_addr);
1157 }
1158
1159 /* "name@devnum[,func]" */
1160 static void __init pci_path_component(struct device_node *dp, char *tmp_buf)
1161 {
1162 struct linux_prom_pci_registers *regs;
1163 struct property *prop;
1164 unsigned int devfn;
1165
1166 prop = of_find_property(dp, "reg", NULL);
1167 if (!prop)
1168 return;
1169
1170 regs = prop->value;
1171 devfn = (regs->phys_hi >> 8) & 0xff;
1172 if (devfn & 0x07) {
1173 sprintf(tmp_buf, "%s@%x,%x",
1174 dp->name,
1175 devfn >> 3,
1176 devfn & 0x07);
1177 } else {
1178 sprintf(tmp_buf, "%s@%x",
1179 dp->name,
1180 devfn >> 3);
1181 }
1182 }
1183
1184 /* "name@UPA_PORTID,offset" */
1185 static void __init upa_path_component(struct device_node *dp, char *tmp_buf)
1186 {
1187 struct linux_prom64_registers *regs;
1188 struct property *prop;
1189
1190 prop = of_find_property(dp, "reg", NULL);
1191 if (!prop)
1192 return;
1193
1194 regs = prop->value;
1195
1196 prop = of_find_property(dp, "upa-portid", NULL);
1197 if (!prop)
1198 return;
1199
1200 sprintf(tmp_buf, "%s@%x,%x",
1201 dp->name,
1202 *(u32 *) prop->value,
1203 (unsigned int) (regs->phys_addr & 0xffffffffUL));
1204 }
1205
1206 /* "name@reg" */
1207 static void __init vdev_path_component(struct device_node *dp, char *tmp_buf)
1208 {
1209 struct property *prop;
1210 u32 *regs;
1211
1212 prop = of_find_property(dp, "reg", NULL);
1213 if (!prop)
1214 return;
1215
1216 regs = prop->value;
1217
1218 sprintf(tmp_buf, "%s@%x", dp->name, *regs);
1219 }
1220
1221 /* "name@addrhi,addrlo" */
1222 static void __init ebus_path_component(struct device_node *dp, char *tmp_buf)
1223 {
1224 struct linux_prom64_registers *regs;
1225 struct property *prop;
1226
1227 prop = of_find_property(dp, "reg", NULL);
1228 if (!prop)
1229 return;
1230
1231 regs = prop->value;
1232
1233 sprintf(tmp_buf, "%s@%x,%x",
1234 dp->name,
1235 (unsigned int) (regs->phys_addr >> 32UL),
1236 (unsigned int) (regs->phys_addr & 0xffffffffUL));
1237 }
1238
1239 /* "name@bus,addr" */
1240 static void __init i2c_path_component(struct device_node *dp, char *tmp_buf)
1241 {
1242 struct property *prop;
1243 u32 *regs;
1244
1245 prop = of_find_property(dp, "reg", NULL);
1246 if (!prop)
1247 return;
1248
1249 regs = prop->value;
1250
1251 /* This actually isn't right... should look at the #address-cells
1252 * property of the i2c bus node etc. etc.
1253 */
1254 sprintf(tmp_buf, "%s@%x,%x",
1255 dp->name, regs[0], regs[1]);
1256 }
1257
1258 /* "name@reg0[,reg1]" */
1259 static void __init usb_path_component(struct device_node *dp, char *tmp_buf)
1260 {
1261 struct property *prop;
1262 u32 *regs;
1263
1264 prop = of_find_property(dp, "reg", NULL);
1265 if (!prop)
1266 return;
1267
1268 regs = prop->value;
1269
1270 if (prop->length == sizeof(u32) || regs[1] == 1) {
1271 sprintf(tmp_buf, "%s@%x",
1272 dp->name, regs[0]);
1273 } else {
1274 sprintf(tmp_buf, "%s@%x,%x",
1275 dp->name, regs[0], regs[1]);
1276 }
1277 }
1278
1279 /* "name@reg0reg1[,reg2reg3]" */
1280 static void __init ieee1394_path_component(struct device_node *dp, char *tmp_buf)
1281 {
1282 struct property *prop;
1283 u32 *regs;
1284
1285 prop = of_find_property(dp, "reg", NULL);
1286 if (!prop)
1287 return;
1288
1289 regs = prop->value;
1290
1291 if (regs[2] || regs[3]) {
1292 sprintf(tmp_buf, "%s@%08x%08x,%04x%08x",
1293 dp->name, regs[0], regs[1], regs[2], regs[3]);
1294 } else {
1295 sprintf(tmp_buf, "%s@%08x%08x",
1296 dp->name, regs[0], regs[1]);
1297 }
1298 }
1299
1300 static void __init __build_path_component(struct device_node *dp, char *tmp_buf)
1301 {
1302 struct device_node *parent = dp->parent;
1303
1304 if (parent != NULL) {
1305 if (!strcmp(parent->type, "pci") ||
1306 !strcmp(parent->type, "pciex"))
1307 return pci_path_component(dp, tmp_buf);
1308 if (!strcmp(parent->type, "sbus"))
1309 return sbus_path_component(dp, tmp_buf);
1310 if (!strcmp(parent->type, "upa"))
1311 return upa_path_component(dp, tmp_buf);
1312 if (!strcmp(parent->type, "ebus"))
1313 return ebus_path_component(dp, tmp_buf);
1314 if (!strcmp(parent->name, "usb") ||
1315 !strcmp(parent->name, "hub"))
1316 return usb_path_component(dp, tmp_buf);
1317 if (!strcmp(parent->type, "i2c"))
1318 return i2c_path_component(dp, tmp_buf);
1319 if (!strcmp(parent->type, "firewire"))
1320 return ieee1394_path_component(dp, tmp_buf);
1321 if (!strcmp(parent->type, "virtual-devices"))
1322 return vdev_path_component(dp, tmp_buf);
1323
1324 /* "isa" is handled with platform naming */
1325 }
1326
1327 /* Use platform naming convention. */
1328 if (tlb_type == hypervisor)
1329 return sun4v_path_component(dp, tmp_buf);
1330 else
1331 return sun4u_path_component(dp, tmp_buf);
1332 }
1333
1334 static char * __init build_path_component(struct device_node *dp)
1335 {
1336 char tmp_buf[64], *n;
1337
1338 tmp_buf[0] = '\0';
1339 __build_path_component(dp, tmp_buf);
1340 if (tmp_buf[0] == '\0')
1341 strcpy(tmp_buf, dp->name);
1342
1343 n = prom_early_alloc(strlen(tmp_buf) + 1);
1344 strcpy(n, tmp_buf);
1345
1346 return n;
1347 }
1348
1349 static char * __init build_full_name(struct device_node *dp)
1350 {
1351 int len, ourlen, plen;
1352 char *n;
1353
1354 plen = strlen(dp->parent->full_name);
1355 ourlen = strlen(dp->path_component_name);
1356 len = ourlen + plen + 2;
1357
1358 n = prom_early_alloc(len);
1359 strcpy(n, dp->parent->full_name);
1360 if (!is_root_node(dp->parent)) {
1361 strcpy(n + plen, "/");
1362 plen++;
1363 }
1364 strcpy(n + plen, dp->path_component_name);
1365
1366 return n;
1367 }
1368
1369 static unsigned int unique_id;
1370
1371 static struct property * __init build_one_prop(phandle node, char *prev, char *special_name, void *special_val, int special_len)
1372 {
1373 static struct property *tmp = NULL;
1374 struct property *p;
1375
1376 if (tmp) {
1377 p = tmp;
1378 memset(p, 0, sizeof(*p) + 32);
1379 tmp = NULL;
1380 } else {
1381 p = prom_early_alloc(sizeof(struct property) + 32);
1382 p->unique_id = unique_id++;
1383 }
1384
1385 p->name = (char *) (p + 1);
1386 if (special_name) {
1387 strcpy(p->name, special_name);
1388 p->length = special_len;
1389 p->value = prom_early_alloc(special_len);
1390 memcpy(p->value, special_val, special_len);
1391 } else {
1392 if (prev == NULL) {
1393 prom_firstprop(node, p->name);
1394 } else {
1395 prom_nextprop(node, prev, p->name);
1396 }
1397 if (strlen(p->name) == 0) {
1398 tmp = p;
1399 return NULL;
1400 }
1401 p->length = prom_getproplen(node, p->name);
1402 if (p->length <= 0) {
1403 p->length = 0;
1404 } else {
1405 p->value = prom_early_alloc(p->length + 1);
1406 prom_getproperty(node, p->name, p->value, p->length);
1407 ((unsigned char *)p->value)[p->length] = '\0';
1408 }
1409 }
1410 return p;
1411 }
1412
1413 static struct property * __init build_prop_list(phandle node)
1414 {
1415 struct property *head, *tail;
1416
1417 head = tail = build_one_prop(node, NULL,
1418 ".node", &node, sizeof(node));
1419
1420 tail->next = build_one_prop(node, NULL, NULL, NULL, 0);
1421 tail = tail->next;
1422 while(tail) {
1423 tail->next = build_one_prop(node, tail->name,
1424 NULL, NULL, 0);
1425 tail = tail->next;
1426 }
1427
1428 return head;
1429 }
1430
1431 static char * __init get_one_property(phandle node, const char *name)
1432 {
1433 char *buf = "<NULL>";
1434 int len;
1435
1436 len = prom_getproplen(node, name);
1437 if (len > 0) {
1438 buf = prom_early_alloc(len);
1439 prom_getproperty(node, name, buf, len);
1440 }
1441
1442 return buf;
1443 }
1444
1445 static struct device_node * __init create_node(phandle node, struct device_node *parent)
1446 {
1447 struct device_node *dp;
1448
1449 if (!node)
1450 return NULL;
1451
1452 dp = prom_early_alloc(sizeof(*dp));
1453 dp->unique_id = unique_id++;
1454 dp->parent = parent;
1455
1456 kref_init(&dp->kref);
1457
1458 dp->name = get_one_property(node, "name");
1459 dp->type = get_one_property(node, "device_type");
1460 dp->node = node;
1461
1462 dp->properties = build_prop_list(node);
1463
1464 irq_trans_init(dp);
1465
1466 return dp;
1467 }
1468
1469 static struct device_node * __init build_tree(struct device_node *parent, phandle node, struct device_node ***nextp)
1470 {
1471 struct device_node *ret = NULL, *prev_sibling = NULL;
1472 struct device_node *dp;
1473
1474 while (1) {
1475 dp = create_node(node, parent);
1476 if (!dp)
1477 break;
1478
1479 if (prev_sibling)
1480 prev_sibling->sibling = dp;
1481
1482 if (!ret)
1483 ret = dp;
1484 prev_sibling = dp;
1485
1486 *(*nextp) = dp;
1487 *nextp = &dp->allnext;
1488
1489 dp->path_component_name = build_path_component(dp);
1490 dp->full_name = build_full_name(dp);
1491
1492 dp->child = build_tree(dp, prom_getchild(node), nextp);
1493
1494 node = prom_getsibling(node);
1495 }
1496
1497 return ret;
1498 }
1499
1500 static const char *get_mid_prop(void)
1501 {
1502 return (tlb_type == spitfire ? "upa-portid" : "portid");
1503 }
1504
1505 struct device_node *of_find_node_by_cpuid(int cpuid)
1506 {
1507 struct device_node *dp;
1508 const char *mid_prop = get_mid_prop();
1509
1510 for_each_node_by_type(dp, "cpu") {
1511 int id = of_getintprop_default(dp, mid_prop, -1);
1512 const char *this_mid_prop = mid_prop;
1513
1514 if (id < 0) {
1515 this_mid_prop = "cpuid";
1516 id = of_getintprop_default(dp, this_mid_prop, -1);
1517 }
1518
1519 if (id < 0) {
1520 prom_printf("OF: Serious problem, cpu lacks "
1521 "%s property", this_mid_prop);
1522 prom_halt();
1523 }
1524 if (cpuid == id)
1525 return dp;
1526 }
1527 return NULL;
1528 }
1529
1530 static void __init of_fill_in_cpu_data(void)
1531 {
1532 struct device_node *dp;
1533 const char *mid_prop = get_mid_prop();
1534
1535 ncpus_probed = 0;
1536 for_each_node_by_type(dp, "cpu") {
1537 int cpuid = of_getintprop_default(dp, mid_prop, -1);
1538 const char *this_mid_prop = mid_prop;
1539 struct device_node *portid_parent;
1540 int portid = -1;
1541
1542 portid_parent = NULL;
1543 if (cpuid < 0) {
1544 this_mid_prop = "cpuid";
1545 cpuid = of_getintprop_default(dp, this_mid_prop, -1);
1546 if (cpuid >= 0) {
1547 int limit = 2;
1548
1549 portid_parent = dp;
1550 while (limit--) {
1551 portid_parent = portid_parent->parent;
1552 if (!portid_parent)
1553 break;
1554 portid = of_getintprop_default(portid_parent,
1555 "portid", -1);
1556 if (portid >= 0)
1557 break;
1558 }
1559 }
1560 }
1561
1562 if (cpuid < 0) {
1563 prom_printf("OF: Serious problem, cpu lacks "
1564 "%s property", this_mid_prop);
1565 prom_halt();
1566 }
1567
1568 ncpus_probed++;
1569
1570 #ifdef CONFIG_SMP
1571 if (cpuid >= NR_CPUS)
1572 continue;
1573 #else
1574 /* On uniprocessor we only want the values for the
1575 * real physical cpu the kernel booted onto, however
1576 * cpu_data() only has one entry at index 0.
1577 */
1578 if (cpuid != real_hard_smp_processor_id())
1579 continue;
1580 cpuid = 0;
1581 #endif
1582
1583 cpu_data(cpuid).clock_tick =
1584 of_getintprop_default(dp, "clock-frequency", 0);
1585
1586 if (portid_parent) {
1587 cpu_data(cpuid).dcache_size =
1588 of_getintprop_default(dp, "l1-dcache-size",
1589 16 * 1024);
1590 cpu_data(cpuid).dcache_line_size =
1591 of_getintprop_default(dp, "l1-dcache-line-size",
1592 32);
1593 cpu_data(cpuid).icache_size =
1594 of_getintprop_default(dp, "l1-icache-size",
1595 8 * 1024);
1596 cpu_data(cpuid).icache_line_size =
1597 of_getintprop_default(dp, "l1-icache-line-size",
1598 32);
1599 cpu_data(cpuid).ecache_size =
1600 of_getintprop_default(dp, "l2-cache-size", 0);
1601 cpu_data(cpuid).ecache_line_size =
1602 of_getintprop_default(dp, "l2-cache-line-size", 0);
1603 if (!cpu_data(cpuid).ecache_size ||
1604 !cpu_data(cpuid).ecache_line_size) {
1605 cpu_data(cpuid).ecache_size =
1606 of_getintprop_default(portid_parent,
1607 "l2-cache-size",
1608 (4 * 1024 * 1024));
1609 cpu_data(cpuid).ecache_line_size =
1610 of_getintprop_default(portid_parent,
1611 "l2-cache-line-size", 64);
1612 }
1613
1614 cpu_data(cpuid).core_id = portid + 1;
1615 cpu_data(cpuid).proc_id = portid;
1616 #ifdef CONFIG_SMP
1617 sparc64_multi_core = 1;
1618 #endif
1619 } else {
1620 cpu_data(cpuid).dcache_size =
1621 of_getintprop_default(dp, "dcache-size", 16 * 1024);
1622 cpu_data(cpuid).dcache_line_size =
1623 of_getintprop_default(dp, "dcache-line-size", 32);
1624
1625 cpu_data(cpuid).icache_size =
1626 of_getintprop_default(dp, "icache-size", 16 * 1024);
1627 cpu_data(cpuid).icache_line_size =
1628 of_getintprop_default(dp, "icache-line-size", 32);
1629
1630 cpu_data(cpuid).ecache_size =
1631 of_getintprop_default(dp, "ecache-size",
1632 (4 * 1024 * 1024));
1633 cpu_data(cpuid).ecache_line_size =
1634 of_getintprop_default(dp, "ecache-line-size", 64);
1635
1636 cpu_data(cpuid).core_id = 0;
1637 cpu_data(cpuid).proc_id = -1;
1638 }
1639
1640 #ifdef CONFIG_SMP
1641 cpu_set(cpuid, cpu_present_map);
1642 cpu_set(cpuid, cpu_possible_map);
1643 #endif
1644 }
1645
1646 smp_fill_in_sib_core_maps();
1647 }
1648
1649 void __init prom_build_devicetree(void)
1650 {
1651 struct device_node **nextp;
1652
1653 allnodes = create_node(prom_root_node, NULL);
1654 allnodes->path_component_name = "";
1655 allnodes->full_name = "/";
1656
1657 nextp = &allnodes->allnext;
1658 allnodes->child = build_tree(allnodes,
1659 prom_getchild(allnodes->node),
1660 &nextp);
1661 printk("PROM: Built device tree with %u bytes of memory.\n",
1662 prom_early_allocated);
1663
1664 if (tlb_type != hypervisor)
1665 of_fill_in_cpu_data();
1666 }
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