1 /* smp.c: Sparc64 SMP support.
3 * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net)
6 #include <linux/module.h>
7 #include <linux/kernel.h>
8 #include <linux/sched.h>
10 #include <linux/pagemap.h>
11 #include <linux/threads.h>
12 #include <linux/smp.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/delay.h>
16 #include <linux/init.h>
17 #include <linux/spinlock.h>
19 #include <linux/seq_file.h>
20 #include <linux/cache.h>
21 #include <linux/jiffies.h>
22 #include <linux/profile.h>
23 #include <linux/bootmem.h>
26 #include <asm/ptrace.h>
27 #include <asm/atomic.h>
28 #include <asm/tlbflush.h>
29 #include <asm/mmu_context.h>
30 #include <asm/cpudata.h>
31 #include <asm/hvtramp.h>
33 #include <asm/timer.h>
36 #include <asm/irq_regs.h>
38 #include <asm/pgtable.h>
39 #include <asm/oplib.h>
40 #include <asm/uaccess.h>
41 #include <asm/timer.h>
42 #include <asm/starfire.h>
44 #include <asm/sections.h>
46 #include <asm/mdesc.h>
48 #include <asm/hypervisor.h>
50 int sparc64_multi_core __read_mostly
;
52 cpumask_t cpu_possible_map __read_mostly
= CPU_MASK_NONE
;
53 cpumask_t cpu_online_map __read_mostly
= CPU_MASK_NONE
;
54 DEFINE_PER_CPU(cpumask_t
, cpu_sibling_map
) = CPU_MASK_NONE
;
55 cpumask_t cpu_core_map
[NR_CPUS
] __read_mostly
=
56 { [0 ... NR_CPUS
-1] = CPU_MASK_NONE
};
58 EXPORT_SYMBOL(cpu_possible_map
);
59 EXPORT_SYMBOL(cpu_online_map
);
60 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map
);
61 EXPORT_SYMBOL(cpu_core_map
);
63 static cpumask_t smp_commenced_mask
;
65 void smp_info(struct seq_file
*m
)
69 seq_printf(m
, "State:\n");
70 for_each_online_cpu(i
)
71 seq_printf(m
, "CPU%d:\t\tonline\n", i
);
74 void smp_bogo(struct seq_file
*m
)
78 for_each_online_cpu(i
)
80 "Cpu%dClkTck\t: %016lx\n",
81 i
, cpu_data(i
).clock_tick
);
84 static __cacheline_aligned_in_smp
DEFINE_SPINLOCK(call_lock
);
86 extern void setup_sparc64_timer(void);
88 static volatile unsigned long callin_flag
= 0;
90 void __cpuinit
smp_callin(void)
92 int cpuid
= hard_smp_processor_id();
94 __local_per_cpu_offset
= __per_cpu_offset(cpuid
);
96 if (tlb_type
== hypervisor
)
97 sun4v_ktsb_register();
101 setup_sparc64_timer();
103 if (cheetah_pcache_forced_on
)
104 cheetah_enable_pcache();
109 __asm__
__volatile__("membar #Sync\n\t"
110 "flush %%g6" : : : "memory");
112 /* Clear this or we will die instantly when we
113 * schedule back to this idler...
115 current_thread_info()->new_child
= 0;
117 /* Attach to the address space of init_task. */
118 atomic_inc(&init_mm
.mm_count
);
119 current
->active_mm
= &init_mm
;
121 while (!cpu_isset(cpuid
, smp_commenced_mask
))
124 spin_lock(&call_lock
);
125 cpu_set(cpuid
, cpu_online_map
);
126 spin_unlock(&call_lock
);
128 /* idle thread is expected to have preempt disabled */
134 printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
135 panic("SMP bolixed\n");
138 /* This tick register synchronization scheme is taken entirely from
139 * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit.
141 * The only change I've made is to rework it so that the master
142 * initiates the synchonization instead of the slave. -DaveM
146 #define SLAVE (SMP_CACHE_BYTES/sizeof(unsigned long))
148 #define NUM_ROUNDS 64 /* magic value */
149 #define NUM_ITERS 5 /* likewise */
151 static DEFINE_SPINLOCK(itc_sync_lock
);
152 static unsigned long go
[SLAVE
+ 1];
154 #define DEBUG_TICK_SYNC 0
156 static inline long get_delta (long *rt
, long *master
)
158 unsigned long best_t0
= 0, best_t1
= ~0UL, best_tm
= 0;
159 unsigned long tcenter
, t0
, t1
, tm
;
162 for (i
= 0; i
< NUM_ITERS
; i
++) {
163 t0
= tick_ops
->get_tick();
166 while (!(tm
= go
[SLAVE
]))
170 t1
= tick_ops
->get_tick();
172 if (t1
- t0
< best_t1
- best_t0
)
173 best_t0
= t0
, best_t1
= t1
, best_tm
= tm
;
176 *rt
= best_t1
- best_t0
;
177 *master
= best_tm
- best_t0
;
179 /* average best_t0 and best_t1 without overflow: */
180 tcenter
= (best_t0
/2 + best_t1
/2);
181 if (best_t0
% 2 + best_t1
% 2 == 2)
183 return tcenter
- best_tm
;
186 void smp_synchronize_tick_client(void)
188 long i
, delta
, adj
, adjust_latency
= 0, done
= 0;
189 unsigned long flags
, rt
, master_time_stamp
, bound
;
192 long rt
; /* roundtrip time */
193 long master
; /* master's timestamp */
194 long diff
; /* difference between midpoint and master's timestamp */
195 long lat
; /* estimate of itc adjustment latency */
204 local_irq_save(flags
);
206 for (i
= 0; i
< NUM_ROUNDS
; i
++) {
207 delta
= get_delta(&rt
, &master_time_stamp
);
209 done
= 1; /* let's lock on to this... */
215 adjust_latency
+= -delta
;
216 adj
= -delta
+ adjust_latency
/4;
220 tick_ops
->add_tick(adj
);
224 t
[i
].master
= master_time_stamp
;
226 t
[i
].lat
= adjust_latency
/4;
230 local_irq_restore(flags
);
233 for (i
= 0; i
< NUM_ROUNDS
; i
++)
234 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
235 t
[i
].rt
, t
[i
].master
, t
[i
].diff
, t
[i
].lat
);
238 printk(KERN_INFO
"CPU %d: synchronized TICK with master CPU "
239 "(last diff %ld cycles, maxerr %lu cycles)\n",
240 smp_processor_id(), delta
, rt
);
243 static void smp_start_sync_tick_client(int cpu
);
245 static void smp_synchronize_one_tick(int cpu
)
247 unsigned long flags
, i
;
251 smp_start_sync_tick_client(cpu
);
253 /* wait for client to be ready */
257 /* now let the client proceed into his loop */
261 spin_lock_irqsave(&itc_sync_lock
, flags
);
263 for (i
= 0; i
< NUM_ROUNDS
*NUM_ITERS
; i
++) {
268 go
[SLAVE
] = tick_ops
->get_tick();
272 spin_unlock_irqrestore(&itc_sync_lock
, flags
);
275 #if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
276 /* XXX Put this in some common place. XXX */
277 static unsigned long kimage_addr_to_ra(void *p
)
279 unsigned long val
= (unsigned long) p
;
281 return kern_base
+ (val
- KERNBASE
);
284 static void ldom_startcpu_cpuid(unsigned int cpu
, unsigned long thread_reg
)
286 extern unsigned long sparc64_ttable_tl0
;
287 extern unsigned long kern_locked_tte_data
;
288 struct hvtramp_descr
*hdesc
;
289 unsigned long trampoline_ra
;
290 struct trap_per_cpu
*tb
;
291 u64 tte_vaddr
, tte_data
;
292 unsigned long hv_err
;
295 hdesc
= kzalloc(sizeof(*hdesc
) +
296 (sizeof(struct hvtramp_mapping
) *
297 num_kernel_image_mappings
- 1),
300 printk(KERN_ERR
"ldom_startcpu_cpuid: Cannot allocate "
306 hdesc
->num_mappings
= num_kernel_image_mappings
;
308 tb
= &trap_block
[cpu
];
311 hdesc
->fault_info_va
= (unsigned long) &tb
->fault_info
;
312 hdesc
->fault_info_pa
= kimage_addr_to_ra(&tb
->fault_info
);
314 hdesc
->thread_reg
= thread_reg
;
316 tte_vaddr
= (unsigned long) KERNBASE
;
317 tte_data
= kern_locked_tte_data
;
319 for (i
= 0; i
< hdesc
->num_mappings
; i
++) {
320 hdesc
->maps
[i
].vaddr
= tte_vaddr
;
321 hdesc
->maps
[i
].tte
= tte_data
;
322 tte_vaddr
+= 0x400000;
323 tte_data
+= 0x400000;
326 trampoline_ra
= kimage_addr_to_ra(hv_cpu_startup
);
328 hv_err
= sun4v_cpu_start(cpu
, trampoline_ra
,
329 kimage_addr_to_ra(&sparc64_ttable_tl0
),
332 printk(KERN_ERR
"ldom_startcpu_cpuid: sun4v_cpu_start() "
333 "gives error %lu\n", hv_err
);
337 extern unsigned long sparc64_cpu_startup
;
339 /* The OBP cpu startup callback truncates the 3rd arg cookie to
340 * 32-bits (I think) so to be safe we have it read the pointer
341 * contained here so we work on >4GB machines. -DaveM
343 static struct thread_info
*cpu_new_thread
= NULL
;
345 static int __devinit
smp_boot_one_cpu(unsigned int cpu
)
347 struct trap_per_cpu
*tb
= &trap_block
[cpu
];
348 unsigned long entry
=
349 (unsigned long)(&sparc64_cpu_startup
);
350 unsigned long cookie
=
351 (unsigned long)(&cpu_new_thread
);
352 struct task_struct
*p
;
359 cpu_new_thread
= task_thread_info(p
);
361 if (tlb_type
== hypervisor
) {
362 #if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
363 if (ldom_domaining_enabled
)
364 ldom_startcpu_cpuid(cpu
,
365 (unsigned long) cpu_new_thread
);
368 prom_startcpu_cpuid(cpu
, entry
, cookie
);
370 struct device_node
*dp
= of_find_node_by_cpuid(cpu
);
372 prom_startcpu(dp
->node
, entry
, cookie
);
375 for (timeout
= 0; timeout
< 50000; timeout
++) {
384 printk("Processor %d is stuck.\n", cpu
);
387 cpu_new_thread
= NULL
;
397 static void spitfire_xcall_helper(u64 data0
, u64 data1
, u64 data2
, u64 pstate
, unsigned long cpu
)
402 if (this_is_starfire
) {
403 /* map to real upaid */
404 cpu
= (((cpu
& 0x3c) << 1) |
405 ((cpu
& 0x40) >> 4) |
409 target
= (cpu
<< 14) | 0x70;
411 /* Ok, this is the real Spitfire Errata #54.
412 * One must read back from a UDB internal register
413 * after writes to the UDB interrupt dispatch, but
414 * before the membar Sync for that write.
415 * So we use the high UDB control register (ASI 0x7f,
416 * ADDR 0x20) for the dummy read. -DaveM
419 __asm__
__volatile__(
420 "wrpr %1, %2, %%pstate\n\t"
421 "stxa %4, [%0] %3\n\t"
422 "stxa %5, [%0+%8] %3\n\t"
424 "stxa %6, [%0+%8] %3\n\t"
426 "stxa %%g0, [%7] %3\n\t"
429 "ldxa [%%g1] 0x7f, %%g0\n\t"
432 : "r" (pstate
), "i" (PSTATE_IE
), "i" (ASI_INTR_W
),
433 "r" (data0
), "r" (data1
), "r" (data2
), "r" (target
),
434 "r" (0x10), "0" (tmp
)
437 /* NOTE: PSTATE_IE is still clear. */
440 __asm__
__volatile__("ldxa [%%g0] %1, %0"
442 : "i" (ASI_INTR_DISPATCH_STAT
));
444 __asm__
__volatile__("wrpr %0, 0x0, %%pstate"
451 } while (result
& 0x1);
452 __asm__
__volatile__("wrpr %0, 0x0, %%pstate"
455 printk("CPU[%d]: mondo stuckage result[%016lx]\n",
456 smp_processor_id(), result
);
463 static inline void spitfire_xcall_deliver(u64 data0
, u64 data1
, u64 data2
, cpumask_t mask
)
468 __asm__
__volatile__("rdpr %%pstate, %0" : "=r" (pstate
));
469 for_each_cpu_mask(i
, mask
)
470 spitfire_xcall_helper(data0
, data1
, data2
, pstate
, i
);
473 /* Cheetah now allows to send the whole 64-bytes of data in the interrupt
474 * packet, but we have no use for that. However we do take advantage of
475 * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
477 static void cheetah_xcall_deliver(u64 data0
, u64 data1
, u64 data2
, cpumask_t mask
)
479 u64 pstate
, ver
, busy_mask
;
480 int nack_busy_id
, is_jbus
, need_more
;
482 if (cpus_empty(mask
))
485 /* Unfortunately, someone at Sun had the brilliant idea to make the
486 * busy/nack fields hard-coded by ITID number for this Ultra-III
487 * derivative processor.
489 __asm__ ("rdpr %%ver, %0" : "=r" (ver
));
490 is_jbus
= ((ver
>> 32) == __JALAPENO_ID
||
491 (ver
>> 32) == __SERRANO_ID
);
493 __asm__
__volatile__("rdpr %%pstate, %0" : "=r" (pstate
));
497 __asm__
__volatile__("wrpr %0, %1, %%pstate\n\t"
498 : : "r" (pstate
), "i" (PSTATE_IE
));
500 /* Setup the dispatch data registers. */
501 __asm__
__volatile__("stxa %0, [%3] %6\n\t"
502 "stxa %1, [%4] %6\n\t"
503 "stxa %2, [%5] %6\n\t"
506 : "r" (data0
), "r" (data1
), "r" (data2
),
507 "r" (0x40), "r" (0x50), "r" (0x60),
515 for_each_cpu_mask(i
, mask
) {
516 u64 target
= (i
<< 14) | 0x70;
519 busy_mask
|= (0x1UL
<< (i
* 2));
521 target
|= (nack_busy_id
<< 24);
522 busy_mask
|= (0x1UL
<<
525 __asm__
__volatile__(
526 "stxa %%g0, [%0] %1\n\t"
529 : "r" (target
), "i" (ASI_INTR_W
));
531 if (nack_busy_id
== 32) {
538 /* Now, poll for completion. */
540 u64 dispatch_stat
, nack_mask
;
543 stuck
= 100000 * nack_busy_id
;
544 nack_mask
= busy_mask
<< 1;
546 __asm__
__volatile__("ldxa [%%g0] %1, %0"
547 : "=r" (dispatch_stat
)
548 : "i" (ASI_INTR_DISPATCH_STAT
));
549 if (!(dispatch_stat
& (busy_mask
| nack_mask
))) {
550 __asm__
__volatile__("wrpr %0, 0x0, %%pstate"
552 if (unlikely(need_more
)) {
554 for_each_cpu_mask(i
, mask
) {
566 } while (dispatch_stat
& busy_mask
);
568 __asm__
__volatile__("wrpr %0, 0x0, %%pstate"
571 if (dispatch_stat
& busy_mask
) {
572 /* Busy bits will not clear, continue instead
573 * of freezing up on this cpu.
575 printk("CPU[%d]: mondo stuckage result[%016lx]\n",
576 smp_processor_id(), dispatch_stat
);
578 int i
, this_busy_nack
= 0;
580 /* Delay some random time with interrupts enabled
581 * to prevent deadlock.
583 udelay(2 * nack_busy_id
);
585 /* Clear out the mask bits for cpus which did not
588 for_each_cpu_mask(i
, mask
) {
592 check_mask
= (0x2UL
<< (2*i
));
594 check_mask
= (0x2UL
<<
596 if ((dispatch_stat
& check_mask
) == 0)
599 if (this_busy_nack
== 64)
608 /* Multi-cpu list version. */
609 static void hypervisor_xcall_deliver(u64 data0
, u64 data1
, u64 data2
, cpumask_t mask
)
611 struct trap_per_cpu
*tb
;
614 cpumask_t error_mask
;
615 unsigned long flags
, status
;
616 int cnt
, retries
, this_cpu
, prev_sent
, i
;
618 if (cpus_empty(mask
))
621 /* We have to do this whole thing with interrupts fully disabled.
622 * Otherwise if we send an xcall from interrupt context it will
623 * corrupt both our mondo block and cpu list state.
625 * One consequence of this is that we cannot use timeout mechanisms
626 * that depend upon interrupts being delivered locally. So, for
627 * example, we cannot sample jiffies and expect it to advance.
629 * Fortunately, udelay() uses %stick/%tick so we can use that.
631 local_irq_save(flags
);
633 this_cpu
= smp_processor_id();
634 tb
= &trap_block
[this_cpu
];
636 mondo
= __va(tb
->cpu_mondo_block_pa
);
642 cpu_list
= __va(tb
->cpu_list_pa
);
644 /* Setup the initial cpu list. */
646 for_each_cpu_mask(i
, mask
)
649 cpus_clear(error_mask
);
653 int forward_progress
, n_sent
;
655 status
= sun4v_cpu_mondo_send(cnt
,
657 tb
->cpu_mondo_block_pa
);
659 /* HV_EOK means all cpus received the xcall, we're done. */
660 if (likely(status
== HV_EOK
))
663 /* First, see if we made any forward progress.
665 * The hypervisor indicates successful sends by setting
666 * cpu list entries to the value 0xffff.
669 for (i
= 0; i
< cnt
; i
++) {
670 if (likely(cpu_list
[i
] == 0xffff))
674 forward_progress
= 0;
675 if (n_sent
> prev_sent
)
676 forward_progress
= 1;
680 /* If we get a HV_ECPUERROR, then one or more of the cpus
681 * in the list are in error state. Use the cpu_state()
682 * hypervisor call to find out which cpus are in error state.
684 if (unlikely(status
== HV_ECPUERROR
)) {
685 for (i
= 0; i
< cnt
; i
++) {
693 err
= sun4v_cpu_state(cpu
);
695 err
== HV_CPU_STATE_ERROR
) {
696 cpu_list
[i
] = 0xffff;
697 cpu_set(cpu
, error_mask
);
700 } else if (unlikely(status
!= HV_EWOULDBLOCK
))
701 goto fatal_mondo_error
;
703 /* Don't bother rewriting the CPU list, just leave the
704 * 0xffff and non-0xffff entries in there and the
705 * hypervisor will do the right thing.
707 * Only advance timeout state if we didn't make any
710 if (unlikely(!forward_progress
)) {
711 if (unlikely(++retries
> 10000))
712 goto fatal_mondo_timeout
;
714 /* Delay a little bit to let other cpus catch up
715 * on their cpu mondo queue work.
721 local_irq_restore(flags
);
723 if (unlikely(!cpus_empty(error_mask
)))
724 goto fatal_mondo_cpu_error
;
728 fatal_mondo_cpu_error
:
729 printk(KERN_CRIT
"CPU[%d]: SUN4V mondo cpu error, some target cpus "
730 "were in error state\n",
732 printk(KERN_CRIT
"CPU[%d]: Error mask [ ", this_cpu
);
733 for_each_cpu_mask(i
, error_mask
)
739 local_irq_restore(flags
);
740 printk(KERN_CRIT
"CPU[%d]: SUN4V mondo timeout, no forward "
741 " progress after %d retries.\n",
743 goto dump_cpu_list_and_out
;
746 local_irq_restore(flags
);
747 printk(KERN_CRIT
"CPU[%d]: Unexpected SUN4V mondo error %lu\n",
749 printk(KERN_CRIT
"CPU[%d]: Args were cnt(%d) cpulist_pa(%lx) "
750 "mondo_block_pa(%lx)\n",
751 this_cpu
, cnt
, tb
->cpu_list_pa
, tb
->cpu_mondo_block_pa
);
753 dump_cpu_list_and_out
:
754 printk(KERN_CRIT
"CPU[%d]: CPU list [ ", this_cpu
);
755 for (i
= 0; i
< cnt
; i
++)
756 printk("%u ", cpu_list
[i
]);
760 /* Send cross call to all processors mentioned in MASK
763 static void smp_cross_call_masked(unsigned long *func
, u32 ctx
, u64 data1
, u64 data2
, cpumask_t mask
)
765 u64 data0
= (((u64
)ctx
)<<32 | (((u64
)func
) & 0xffffffff));
766 int this_cpu
= get_cpu();
768 cpus_and(mask
, mask
, cpu_online_map
);
769 cpu_clear(this_cpu
, mask
);
771 if (tlb_type
== spitfire
)
772 spitfire_xcall_deliver(data0
, data1
, data2
, mask
);
773 else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
)
774 cheetah_xcall_deliver(data0
, data1
, data2
, mask
);
776 hypervisor_xcall_deliver(data0
, data1
, data2
, mask
);
777 /* NOTE: Caller runs local copy on master. */
782 extern unsigned long xcall_sync_tick
;
784 static void smp_start_sync_tick_client(int cpu
)
786 cpumask_t mask
= cpumask_of_cpu(cpu
);
788 smp_cross_call_masked(&xcall_sync_tick
,
792 /* Send cross call to all processors except self. */
793 #define smp_cross_call(func, ctx, data1, data2) \
794 smp_cross_call_masked(func, ctx, data1, data2, cpu_online_map)
796 struct call_data_struct
{
797 void (*func
) (void *info
);
803 static struct call_data_struct
*call_data
;
805 extern unsigned long xcall_call_function
;
808 * smp_call_function(): Run a function on all other CPUs.
809 * @func: The function to run. This must be fast and non-blocking.
810 * @info: An arbitrary pointer to pass to the function.
811 * @nonatomic: currently unused.
812 * @wait: If true, wait (atomically) until function has completed on other CPUs.
814 * Returns 0 on success, else a negative status code. Does not return until
815 * remote CPUs are nearly ready to execute <<func>> or are or have executed.
817 * You must not call this function with disabled interrupts or from a
818 * hardware interrupt handler or from a bottom half handler.
820 static int smp_call_function_mask(void (*func
)(void *info
), void *info
,
821 int nonatomic
, int wait
, cpumask_t mask
)
823 struct call_data_struct data
;
826 /* Can deadlock when called with interrupts disabled */
827 WARN_ON(irqs_disabled());
831 atomic_set(&data
.finished
, 0);
834 spin_lock(&call_lock
);
836 cpu_clear(smp_processor_id(), mask
);
837 cpus
= cpus_weight(mask
);
844 smp_cross_call_masked(&xcall_call_function
, 0, 0, 0, mask
);
846 /* Wait for response */
847 while (atomic_read(&data
.finished
) != cpus
)
851 spin_unlock(&call_lock
);
856 int smp_call_function(void (*func
)(void *info
), void *info
,
857 int nonatomic
, int wait
)
859 return smp_call_function_mask(func
, info
, nonatomic
, wait
,
863 void smp_call_function_client(int irq
, struct pt_regs
*regs
)
865 void (*func
) (void *info
) = call_data
->func
;
866 void *info
= call_data
->info
;
868 clear_softint(1 << irq
);
869 if (call_data
->wait
) {
870 /* let initiator proceed only after completion */
872 atomic_inc(&call_data
->finished
);
874 /* let initiator proceed after getting data */
875 atomic_inc(&call_data
->finished
);
880 static void tsb_sync(void *info
)
882 struct trap_per_cpu
*tp
= &trap_block
[raw_smp_processor_id()];
883 struct mm_struct
*mm
= info
;
885 /* It is not valid to test "currrent->active_mm == mm" here.
887 * The value of "current" is not changed atomically with
888 * switch_mm(). But that's OK, we just need to check the
889 * current cpu's trap block PGD physical address.
891 if (tp
->pgd_paddr
== __pa(mm
->pgd
))
892 tsb_context_switch(mm
);
895 void smp_tsb_sync(struct mm_struct
*mm
)
897 smp_call_function_mask(tsb_sync
, mm
, 0, 1, mm
->cpu_vm_mask
);
900 extern unsigned long xcall_flush_tlb_mm
;
901 extern unsigned long xcall_flush_tlb_pending
;
902 extern unsigned long xcall_flush_tlb_kernel_range
;
903 extern unsigned long xcall_report_regs
;
904 extern unsigned long xcall_receive_signal
;
905 extern unsigned long xcall_new_mmu_context_version
;
907 #ifdef DCACHE_ALIASING_POSSIBLE
908 extern unsigned long xcall_flush_dcache_page_cheetah
;
910 extern unsigned long xcall_flush_dcache_page_spitfire
;
912 #ifdef CONFIG_DEBUG_DCFLUSH
913 extern atomic_t dcpage_flushes
;
914 extern atomic_t dcpage_flushes_xcall
;
917 static inline void __local_flush_dcache_page(struct page
*page
)
919 #ifdef DCACHE_ALIASING_POSSIBLE
920 __flush_dcache_page(page_address(page
),
921 ((tlb_type
== spitfire
) &&
922 page_mapping(page
) != NULL
));
924 if (page_mapping(page
) != NULL
&&
925 tlb_type
== spitfire
)
926 __flush_icache_page(__pa(page_address(page
)));
930 void smp_flush_dcache_page_impl(struct page
*page
, int cpu
)
932 cpumask_t mask
= cpumask_of_cpu(cpu
);
935 if (tlb_type
== hypervisor
)
938 #ifdef CONFIG_DEBUG_DCFLUSH
939 atomic_inc(&dcpage_flushes
);
942 this_cpu
= get_cpu();
944 if (cpu
== this_cpu
) {
945 __local_flush_dcache_page(page
);
946 } else if (cpu_online(cpu
)) {
947 void *pg_addr
= page_address(page
);
950 if (tlb_type
== spitfire
) {
952 ((u64
)&xcall_flush_dcache_page_spitfire
);
953 if (page_mapping(page
) != NULL
)
954 data0
|= ((u64
)1 << 32);
955 spitfire_xcall_deliver(data0
,
959 } else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
960 #ifdef DCACHE_ALIASING_POSSIBLE
962 ((u64
)&xcall_flush_dcache_page_cheetah
);
963 cheetah_xcall_deliver(data0
,
968 #ifdef CONFIG_DEBUG_DCFLUSH
969 atomic_inc(&dcpage_flushes_xcall
);
976 void flush_dcache_page_all(struct mm_struct
*mm
, struct page
*page
)
978 void *pg_addr
= page_address(page
);
979 cpumask_t mask
= cpu_online_map
;
983 if (tlb_type
== hypervisor
)
986 this_cpu
= get_cpu();
988 cpu_clear(this_cpu
, mask
);
990 #ifdef CONFIG_DEBUG_DCFLUSH
991 atomic_inc(&dcpage_flushes
);
993 if (cpus_empty(mask
))
995 if (tlb_type
== spitfire
) {
996 data0
= ((u64
)&xcall_flush_dcache_page_spitfire
);
997 if (page_mapping(page
) != NULL
)
998 data0
|= ((u64
)1 << 32);
999 spitfire_xcall_deliver(data0
,
1003 } else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
1004 #ifdef DCACHE_ALIASING_POSSIBLE
1005 data0
= ((u64
)&xcall_flush_dcache_page_cheetah
);
1006 cheetah_xcall_deliver(data0
,
1011 #ifdef CONFIG_DEBUG_DCFLUSH
1012 atomic_inc(&dcpage_flushes_xcall
);
1015 __local_flush_dcache_page(page
);
1020 static void __smp_receive_signal_mask(cpumask_t mask
)
1022 smp_cross_call_masked(&xcall_receive_signal
, 0, 0, 0, mask
);
1025 void smp_receive_signal(int cpu
)
1027 cpumask_t mask
= cpumask_of_cpu(cpu
);
1029 if (cpu_online(cpu
))
1030 __smp_receive_signal_mask(mask
);
1033 void smp_receive_signal_client(int irq
, struct pt_regs
*regs
)
1035 clear_softint(1 << irq
);
1038 void smp_new_mmu_context_version_client(int irq
, struct pt_regs
*regs
)
1040 struct mm_struct
*mm
;
1041 unsigned long flags
;
1043 clear_softint(1 << irq
);
1045 /* See if we need to allocate a new TLB context because
1046 * the version of the one we are using is now out of date.
1048 mm
= current
->active_mm
;
1049 if (unlikely(!mm
|| (mm
== &init_mm
)))
1052 spin_lock_irqsave(&mm
->context
.lock
, flags
);
1054 if (unlikely(!CTX_VALID(mm
->context
)))
1055 get_new_mmu_context(mm
);
1057 spin_unlock_irqrestore(&mm
->context
.lock
, flags
);
1059 load_secondary_context(mm
);
1060 __flush_tlb_mm(CTX_HWBITS(mm
->context
),
1064 void smp_new_mmu_context_version(void)
1066 smp_cross_call(&xcall_new_mmu_context_version
, 0, 0, 0);
1069 void smp_report_regs(void)
1071 smp_cross_call(&xcall_report_regs
, 0, 0, 0);
1074 /* We know that the window frames of the user have been flushed
1075 * to the stack before we get here because all callers of us
1076 * are flush_tlb_*() routines, and these run after flush_cache_*()
1077 * which performs the flushw.
1079 * The SMP TLB coherency scheme we use works as follows:
1081 * 1) mm->cpu_vm_mask is a bit mask of which cpus an address
1082 * space has (potentially) executed on, this is the heuristic
1083 * we use to avoid doing cross calls.
1085 * Also, for flushing from kswapd and also for clones, we
1086 * use cpu_vm_mask as the list of cpus to make run the TLB.
1088 * 2) TLB context numbers are shared globally across all processors
1089 * in the system, this allows us to play several games to avoid
1092 * One invariant is that when a cpu switches to a process, and
1093 * that processes tsk->active_mm->cpu_vm_mask does not have the
1094 * current cpu's bit set, that tlb context is flushed locally.
1096 * If the address space is non-shared (ie. mm->count == 1) we avoid
1097 * cross calls when we want to flush the currently running process's
1098 * tlb state. This is done by clearing all cpu bits except the current
1099 * processor's in current->active_mm->cpu_vm_mask and performing the
1100 * flush locally only. This will force any subsequent cpus which run
1101 * this task to flush the context from the local tlb if the process
1102 * migrates to another cpu (again).
1104 * 3) For shared address spaces (threads) and swapping we bite the
1105 * bullet for most cases and perform the cross call (but only to
1106 * the cpus listed in cpu_vm_mask).
1108 * The performance gain from "optimizing" away the cross call for threads is
1109 * questionable (in theory the big win for threads is the massive sharing of
1110 * address space state across processors).
1113 /* This currently is only used by the hugetlb arch pre-fault
1114 * hook on UltraSPARC-III+ and later when changing the pagesize
1115 * bits of the context register for an address space.
1117 void smp_flush_tlb_mm(struct mm_struct
*mm
)
1119 u32 ctx
= CTX_HWBITS(mm
->context
);
1120 int cpu
= get_cpu();
1122 if (atomic_read(&mm
->mm_users
) == 1) {
1123 mm
->cpu_vm_mask
= cpumask_of_cpu(cpu
);
1124 goto local_flush_and_out
;
1127 smp_cross_call_masked(&xcall_flush_tlb_mm
,
1131 local_flush_and_out
:
1132 __flush_tlb_mm(ctx
, SECONDARY_CONTEXT
);
1137 void smp_flush_tlb_pending(struct mm_struct
*mm
, unsigned long nr
, unsigned long *vaddrs
)
1139 u32 ctx
= CTX_HWBITS(mm
->context
);
1140 int cpu
= get_cpu();
1142 if (mm
== current
->active_mm
&& atomic_read(&mm
->mm_users
) == 1)
1143 mm
->cpu_vm_mask
= cpumask_of_cpu(cpu
);
1145 smp_cross_call_masked(&xcall_flush_tlb_pending
,
1146 ctx
, nr
, (unsigned long) vaddrs
,
1149 __flush_tlb_pending(ctx
, nr
, vaddrs
);
1154 void smp_flush_tlb_kernel_range(unsigned long start
, unsigned long end
)
1157 end
= PAGE_ALIGN(end
);
1159 smp_cross_call(&xcall_flush_tlb_kernel_range
,
1162 __flush_tlb_kernel_range(start
, end
);
1167 /* #define CAPTURE_DEBUG */
1168 extern unsigned long xcall_capture
;
1170 static atomic_t smp_capture_depth
= ATOMIC_INIT(0);
1171 static atomic_t smp_capture_registry
= ATOMIC_INIT(0);
1172 static unsigned long penguins_are_doing_time
;
1174 void smp_capture(void)
1176 int result
= atomic_add_ret(1, &smp_capture_depth
);
1179 int ncpus
= num_online_cpus();
1181 #ifdef CAPTURE_DEBUG
1182 printk("CPU[%d]: Sending penguins to jail...",
1183 smp_processor_id());
1185 penguins_are_doing_time
= 1;
1186 membar_storestore_loadstore();
1187 atomic_inc(&smp_capture_registry
);
1188 smp_cross_call(&xcall_capture
, 0, 0, 0);
1189 while (atomic_read(&smp_capture_registry
) != ncpus
)
1191 #ifdef CAPTURE_DEBUG
1197 void smp_release(void)
1199 if (atomic_dec_and_test(&smp_capture_depth
)) {
1200 #ifdef CAPTURE_DEBUG
1201 printk("CPU[%d]: Giving pardon to "
1202 "imprisoned penguins\n",
1203 smp_processor_id());
1205 penguins_are_doing_time
= 0;
1206 membar_storeload_storestore();
1207 atomic_dec(&smp_capture_registry
);
1211 /* Imprisoned penguins run with %pil == 15, but PSTATE_IE set, so they
1212 * can service tlb flush xcalls...
1214 extern void prom_world(int);
1216 void smp_penguin_jailcell(int irq
, struct pt_regs
*regs
)
1218 clear_softint(1 << irq
);
1222 __asm__
__volatile__("flushw");
1224 atomic_inc(&smp_capture_registry
);
1225 membar_storeload_storestore();
1226 while (penguins_are_doing_time
)
1228 atomic_dec(&smp_capture_registry
);
1234 /* /proc/profile writes can call this, don't __init it please. */
1235 int setup_profiling_timer(unsigned int multiplier
)
1240 void __init
smp_prepare_cpus(unsigned int max_cpus
)
1244 void __devinit
smp_prepare_boot_cpu(void)
1248 void __devinit
smp_fill_in_sib_core_maps(void)
1252 for_each_present_cpu(i
) {
1255 cpus_clear(cpu_core_map
[i
]);
1256 if (cpu_data(i
).core_id
== 0) {
1257 cpu_set(i
, cpu_core_map
[i
]);
1261 for_each_present_cpu(j
) {
1262 if (cpu_data(i
).core_id
==
1263 cpu_data(j
).core_id
)
1264 cpu_set(j
, cpu_core_map
[i
]);
1268 for_each_present_cpu(i
) {
1271 cpus_clear(per_cpu(cpu_sibling_map
, i
));
1272 if (cpu_data(i
).proc_id
== -1) {
1273 cpu_set(i
, per_cpu(cpu_sibling_map
, i
));
1277 for_each_present_cpu(j
) {
1278 if (cpu_data(i
).proc_id
==
1279 cpu_data(j
).proc_id
)
1280 cpu_set(j
, per_cpu(cpu_sibling_map
, i
));
1285 int __cpuinit
__cpu_up(unsigned int cpu
)
1287 int ret
= smp_boot_one_cpu(cpu
);
1290 cpu_set(cpu
, smp_commenced_mask
);
1291 while (!cpu_isset(cpu
, cpu_online_map
))
1293 if (!cpu_isset(cpu
, cpu_online_map
)) {
1296 /* On SUN4V, writes to %tick and %stick are
1299 if (tlb_type
!= hypervisor
)
1300 smp_synchronize_one_tick(cpu
);
1306 #ifdef CONFIG_HOTPLUG_CPU
1307 void cpu_play_dead(void)
1309 int cpu
= smp_processor_id();
1310 unsigned long pstate
;
1314 if (tlb_type
== hypervisor
) {
1315 struct trap_per_cpu
*tb
= &trap_block
[cpu
];
1317 sun4v_cpu_qconf(HV_CPU_QUEUE_CPU_MONDO
,
1318 tb
->cpu_mondo_pa
, 0);
1319 sun4v_cpu_qconf(HV_CPU_QUEUE_DEVICE_MONDO
,
1320 tb
->dev_mondo_pa
, 0);
1321 sun4v_cpu_qconf(HV_CPU_QUEUE_RES_ERROR
,
1322 tb
->resum_mondo_pa
, 0);
1323 sun4v_cpu_qconf(HV_CPU_QUEUE_NONRES_ERROR
,
1324 tb
->nonresum_mondo_pa
, 0);
1327 cpu_clear(cpu
, smp_commenced_mask
);
1328 membar_safe("#Sync");
1330 local_irq_disable();
1332 __asm__
__volatile__(
1333 "rdpr %%pstate, %0\n\t"
1334 "wrpr %0, %1, %%pstate"
1342 int __cpu_disable(void)
1344 int cpu
= smp_processor_id();
1348 for_each_cpu_mask(i
, cpu_core_map
[cpu
])
1349 cpu_clear(cpu
, cpu_core_map
[i
]);
1350 cpus_clear(cpu_core_map
[cpu
]);
1352 for_each_cpu_mask(i
, per_cpu(cpu_sibling_map
, cpu
))
1353 cpu_clear(cpu
, per_cpu(cpu_sibling_map
, i
));
1354 cpus_clear(per_cpu(cpu_sibling_map
, cpu
));
1361 spin_lock(&call_lock
);
1362 cpu_clear(cpu
, cpu_online_map
);
1363 spin_unlock(&call_lock
);
1367 /* Make sure no interrupts point to this cpu. */
1372 local_irq_disable();
1377 void __cpu_die(unsigned int cpu
)
1381 for (i
= 0; i
< 100; i
++) {
1383 if (!cpu_isset(cpu
, smp_commenced_mask
))
1387 if (cpu_isset(cpu
, smp_commenced_mask
)) {
1388 printk(KERN_ERR
"CPU %u didn't die...\n", cpu
);
1390 #if defined(CONFIG_SUN_LDOMS)
1391 unsigned long hv_err
;
1395 hv_err
= sun4v_cpu_stop(cpu
);
1396 if (hv_err
== HV_EOK
) {
1397 cpu_clear(cpu
, cpu_present_map
);
1400 } while (--limit
> 0);
1402 printk(KERN_ERR
"sun4v_cpu_stop() fails err=%lu\n",
1410 void __init
smp_cpus_done(unsigned int max_cpus
)
1414 void smp_send_reschedule(int cpu
)
1416 smp_receive_signal(cpu
);
1419 /* This is a nop because we capture all other cpus
1420 * anyways when making the PROM active.
1422 void smp_send_stop(void)
1426 unsigned long __per_cpu_base __read_mostly
;
1427 unsigned long __per_cpu_shift __read_mostly
;
1429 EXPORT_SYMBOL(__per_cpu_base
);
1430 EXPORT_SYMBOL(__per_cpu_shift
);
1432 void __init
real_setup_per_cpu_areas(void)
1434 unsigned long goal
, size
, i
;
1437 /* Copy section for each CPU (we discard the original) */
1438 goal
= PERCPU_ENOUGH_ROOM
;
1440 __per_cpu_shift
= PAGE_SHIFT
;
1441 for (size
= PAGE_SIZE
; size
< goal
; size
<<= 1UL)
1444 ptr
= alloc_bootmem_pages(size
* NR_CPUS
);
1446 __per_cpu_base
= ptr
- __per_cpu_start
;
1448 for (i
= 0; i
< NR_CPUS
; i
++, ptr
+= size
)
1449 memcpy(ptr
, __per_cpu_start
, __per_cpu_end
- __per_cpu_start
);
1451 /* Setup %g5 for the boot cpu. */
1452 __local_per_cpu_offset
= __per_cpu_offset(smp_processor_id());