arch/sparc64/kernel/trampoline.S

   1 /* $Id: trampoline.S,v 1.26 2002/02/09 19:49:30 davem Exp $
   2  * trampoline.S: Jump start slave processors on sparc64.
   3  *
   4  * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
   5  */
   6
   7 #include <linux/init.h>
   8
   9 #include <asm/head.h>
  10 #include <asm/asi.h>
  11 #include <asm/lsu.h>
  12 #include <asm/dcr.h>
  13 #include <asm/dcu.h>
  14 #include <asm/pstate.h>
  15 #include <asm/page.h>
  16 #include <asm/pgtable.h>
  17 #include <asm/spitfire.h>
  18 #include <asm/processor.h>
  19 #include <asm/thread_info.h>
  20 #include <asm/mmu.h>
  21 #include <asm/hypervisor.h>
  22 #include <asm/cpudata.h>
  23
  24         .data
  25         .align  8
  26 call_method:
  27         .asciz  "call-method"
  28         .align  8
  29 itlb_load:
  30         .asciz  "SUNW,itlb-load"
  31         .align  8
  32 dtlb_load:
  33         .asciz  "SUNW,dtlb-load"
  34
  35         /* XXX __cpuinit this thing XXX */
  36 #define TRAMP_STACK_SIZE        1024
  37         .align  16
  38 tramp_stack:
  39         .skip   TRAMP_STACK_SIZE
  40
  41         __CPUINIT
  42         .align          8
  43         .globl          sparc64_cpu_startup, sparc64_cpu_startup_end
  44 sparc64_cpu_startup:
  45         BRANCH_IF_SUN4V(g1, niagara_startup)
  46         BRANCH_IF_CHEETAH_BASE(g1, g5, cheetah_startup)
  47         BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1, g5, cheetah_plus_startup)
  48
  49         ba,pt   %xcc, spitfire_startup
  50          nop
  51
  52 cheetah_plus_startup:
  53         /* Preserve OBP chosen DCU and DCR register settings.  */
  54         ba,pt   %xcc, cheetah_generic_startup
  55          nop
  56
  57 cheetah_startup:
  58         mov     DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1
  59         wr      %g1, %asr18
  60
  61         sethi   %uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g5
  62         or      %g5, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g5
  63         sllx    %g5, 32, %g5
  64         or      %g5, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g5
  65         stxa    %g5, [%g0] ASI_DCU_CONTROL_REG
  66         membar  #Sync
  67         /* fallthru */
  68
  69 cheetah_generic_startup:
  70         mov     TSB_EXTENSION_P, %g3
  71         stxa    %g0, [%g3] ASI_DMMU
  72         stxa    %g0, [%g3] ASI_IMMU
  73         membar  #Sync
  74
  75         mov     TSB_EXTENSION_S, %g3
  76         stxa    %g0, [%g3] ASI_DMMU
  77         membar  #Sync
  78
  79         mov     TSB_EXTENSION_N, %g3
  80         stxa    %g0, [%g3] ASI_DMMU
  81         stxa    %g0, [%g3] ASI_IMMU
  82         membar  #Sync
  83         /* fallthru */
  84
  85 niagara_startup:
  86         /* Disable STICK_INT interrupts. */
  87         sethi           %hi(0x80000000), %g5
  88         sllx            %g5, 32, %g5
  89         wr              %g5, %asr25
  90
  91         ba,pt           %xcc, startup_continue
  92          nop
  93
  94 spitfire_startup:
  95         mov             (LSU_CONTROL_IC | LSU_CONTROL_DC | LSU_CONTROL_IM | LSU_CONTROL_DM), %g1
  96         stxa            %g1, [%g0] ASI_LSU_CONTROL
  97         membar          #Sync
  98
  99 startup_continue:
 100         mov             %o0, %l0
 101         BRANCH_IF_SUN4V(g1, niagara_lock_tlb)
 102
 103         sethi           %hi(0x80000000), %g2
 104         sllx            %g2, 32, %g2
 105         wr              %g2, 0, %tick_cmpr
 106
 107         /* Call OBP by hand to lock KERNBASE into i/d tlbs.
 108          * We lock 2 consequetive entries if we are 'bigkernel'.
 109          */
 110         sethi           %hi(prom_entry_lock), %g2
 111 1:      ldstub          [%g2 + %lo(prom_entry_lock)], %g1
 112         membar          #StoreLoad | #StoreStore
 113         brnz,pn         %g1, 1b
 114          nop
 115
 116         sethi           %hi(p1275buf), %g2
 117         or              %g2, %lo(p1275buf), %g2
 118         ldx             [%g2 + 0x10], %l2
 119         add             %l2, -(192 + 128), %sp
 120         flushw
 121
 122         sethi           %hi(call_method), %g2
 123         or              %g2, %lo(call_method), %g2
 124         stx             %g2, [%sp + 2047 + 128 + 0x00]
 125         mov             5, %g2
 126         stx             %g2, [%sp + 2047 + 128 + 0x08]
 127         mov             1, %g2
 128         stx             %g2, [%sp + 2047 + 128 + 0x10]
 129         sethi           %hi(itlb_load), %g2
 130         or              %g2, %lo(itlb_load), %g2
 131         stx             %g2, [%sp + 2047 + 128 + 0x18]
 132         sethi           %hi(prom_mmu_ihandle_cache), %g2
 133         lduw            [%g2 + %lo(prom_mmu_ihandle_cache)], %g2
 134         stx             %g2, [%sp + 2047 + 128 + 0x20]
 135         sethi           %hi(KERNBASE), %g2
 136         stx             %g2, [%sp + 2047 + 128 + 0x28]
 137         sethi           %hi(kern_locked_tte_data), %g2
 138         ldx             [%g2 + %lo(kern_locked_tte_data)], %g2
 139         stx             %g2, [%sp + 2047 + 128 + 0x30]
 140
 141         mov             15, %g2
 142         BRANCH_IF_ANY_CHEETAH(g1,g5,1f)
 143
 144         mov             63, %g2
 145 1:
 146         stx             %g2, [%sp + 2047 + 128 + 0x38]
 147         sethi           %hi(p1275buf), %g2
 148         or              %g2, %lo(p1275buf), %g2
 149         ldx             [%g2 + 0x08], %o1
 150         call            %o1
 151          add            %sp, (2047 + 128), %o0
 152
 153         sethi           %hi(bigkernel), %g2
 154         lduw            [%g2 + %lo(bigkernel)], %g2
 155         brz,pt          %g2, do_dtlb
 156          nop
 157
 158         sethi           %hi(call_method), %g2
 159         or              %g2, %lo(call_method), %g2
 160         stx             %g2, [%sp + 2047 + 128 + 0x00]
 161         mov             5, %g2
 162         stx             %g2, [%sp + 2047 + 128 + 0x08]
 163         mov             1, %g2
 164         stx             %g2, [%sp + 2047 + 128 + 0x10]
 165         sethi           %hi(itlb_load), %g2
 166         or              %g2, %lo(itlb_load), %g2
 167         stx             %g2, [%sp + 2047 + 128 + 0x18]
 168         sethi           %hi(prom_mmu_ihandle_cache), %g2
 169         lduw            [%g2 + %lo(prom_mmu_ihandle_cache)], %g2
 170         stx             %g2, [%sp + 2047 + 128 + 0x20]
 171         sethi           %hi(KERNBASE + 0x400000), %g2
 172         stx             %g2, [%sp + 2047 + 128 + 0x28]
 173         sethi           %hi(kern_locked_tte_data), %g2
 174         ldx             [%g2 + %lo(kern_locked_tte_data)], %g2
 175         sethi           %hi(0x400000), %g1
 176         add             %g2, %g1, %g2
 177         stx             %g2, [%sp + 2047 + 128 + 0x30]
 178
 179         mov             14, %g2
 180         BRANCH_IF_ANY_CHEETAH(g1,g5,1f)
 181
 182         mov             62, %g2
 183 1:
 184         stx             %g2, [%sp + 2047 + 128 + 0x38]
 185         sethi           %hi(p1275buf), %g2
 186         or              %g2, %lo(p1275buf), %g2
 187         ldx             [%g2 + 0x08], %o1
 188         call            %o1
 189          add            %sp, (2047 + 128), %o0
 190
 191 do_dtlb:
 192         sethi           %hi(call_method), %g2
 193         or              %g2, %lo(call_method), %g2
 194         stx             %g2, [%sp + 2047 + 128 + 0x00]
 195         mov             5, %g2
 196         stx             %g2, [%sp + 2047 + 128 + 0x08]
 197         mov             1, %g2
 198         stx             %g2, [%sp + 2047 + 128 + 0x10]
 199         sethi           %hi(dtlb_load), %g2
 200         or              %g2, %lo(dtlb_load), %g2
 201         stx             %g2, [%sp + 2047 + 128 + 0x18]
 202         sethi           %hi(prom_mmu_ihandle_cache), %g2
 203         lduw            [%g2 + %lo(prom_mmu_ihandle_cache)], %g2
 204         stx             %g2, [%sp + 2047 + 128 + 0x20]
 205         sethi           %hi(KERNBASE), %g2
 206         stx             %g2, [%sp + 2047 + 128 + 0x28]
 207         sethi           %hi(kern_locked_tte_data), %g2
 208         ldx             [%g2 + %lo(kern_locked_tte_data)], %g2
 209         stx             %g2, [%sp + 2047 + 128 + 0x30]
 210
 211         mov             15, %g2
 212         BRANCH_IF_ANY_CHEETAH(g1,g5,1f)
 213
 214         mov             63, %g2
 215 1:
 216
 217         stx             %g2, [%sp + 2047 + 128 + 0x38]
 218         sethi           %hi(p1275buf), %g2
 219         or              %g2, %lo(p1275buf), %g2
 220         ldx             [%g2 + 0x08], %o1
 221         call            %o1
 222          add            %sp, (2047 + 128), %o0
 223
 224         sethi           %hi(bigkernel), %g2
 225         lduw            [%g2 + %lo(bigkernel)], %g2
 226         brz,pt          %g2, do_unlock
 227          nop
 228
 229         sethi           %hi(call_method), %g2
 230         or              %g2, %lo(call_method), %g2
 231         stx             %g2, [%sp + 2047 + 128 + 0x00]
 232         mov             5, %g2
 233         stx             %g2, [%sp + 2047 + 128 + 0x08]
 234         mov             1, %g2
 235         stx             %g2, [%sp + 2047 + 128 + 0x10]
 236         sethi           %hi(dtlb_load), %g2
 237         or              %g2, %lo(dtlb_load), %g2
 238         stx             %g2, [%sp + 2047 + 128 + 0x18]
 239         sethi           %hi(prom_mmu_ihandle_cache), %g2
 240         lduw            [%g2 + %lo(prom_mmu_ihandle_cache)], %g2
 241         stx             %g2, [%sp + 2047 + 128 + 0x20]
 242         sethi           %hi(KERNBASE + 0x400000), %g2
 243         stx             %g2, [%sp + 2047 + 128 + 0x28]
 244         sethi           %hi(kern_locked_tte_data), %g2
 245         ldx             [%g2 + %lo(kern_locked_tte_data)], %g2
 246         sethi           %hi(0x400000), %g1
 247         add             %g2, %g1, %g2
 248         stx             %g2, [%sp + 2047 + 128 + 0x30]
 249
 250         mov             14, %g2
 251         BRANCH_IF_ANY_CHEETAH(g1,g5,1f)
 252
 253         mov             62, %g2
 254 1:
 255
 256         stx             %g2, [%sp + 2047 + 128 + 0x38]
 257         sethi           %hi(p1275buf), %g2
 258         or              %g2, %lo(p1275buf), %g2
 259         ldx             [%g2 + 0x08], %o1
 260         call            %o1
 261          add            %sp, (2047 + 128), %o0
 262
 263 do_unlock:
 264         sethi           %hi(prom_entry_lock), %g2
 265         stb             %g0, [%g2 + %lo(prom_entry_lock)]
 266         membar          #StoreStore | #StoreLoad
 267
 268         ba,pt           %xcc, after_lock_tlb
 269          nop
 270
 271 niagara_lock_tlb:
 272         mov             HV_FAST_MMU_MAP_PERM_ADDR, %o5
 273         sethi           %hi(KERNBASE), %o0
 274         clr             %o1
 275         sethi           %hi(kern_locked_tte_data), %o2
 276         ldx             [%o2 + %lo(kern_locked_tte_data)], %o2
 277         mov             HV_MMU_IMMU, %o3
 278         ta              HV_FAST_TRAP
 279
 280         mov             HV_FAST_MMU_MAP_PERM_ADDR, %o5
 281         sethi           %hi(KERNBASE), %o0
 282         clr             %o1
 283         sethi           %hi(kern_locked_tte_data), %o2
 284         ldx             [%o2 + %lo(kern_locked_tte_data)], %o2
 285         mov             HV_MMU_DMMU, %o3
 286         ta              HV_FAST_TRAP
 287
 288         sethi           %hi(bigkernel), %g2
 289         lduw            [%g2 + %lo(bigkernel)], %g2
 290         brz,pt          %g2, after_lock_tlb
 291          nop
 292
 293         mov             HV_FAST_MMU_MAP_PERM_ADDR, %o5
 294         sethi           %hi(KERNBASE + 0x400000), %o0
 295         clr             %o1
 296         sethi           %hi(kern_locked_tte_data), %o2
 297         ldx             [%o2 + %lo(kern_locked_tte_data)], %o2
 298         sethi           %hi(0x400000), %o3
 299         add             %o2, %o3, %o2
 300         mov             HV_MMU_IMMU, %o3
 301         ta              HV_FAST_TRAP
 302
 303         mov             HV_FAST_MMU_MAP_PERM_ADDR, %o5
 304         sethi           %hi(KERNBASE + 0x400000), %o0
 305         clr             %o1
 306         sethi           %hi(kern_locked_tte_data), %o2
 307         ldx             [%o2 + %lo(kern_locked_tte_data)], %o2
 308         sethi           %hi(0x400000), %o3
 309         add             %o2, %o3, %o2
 310         mov             HV_MMU_DMMU, %o3
 311         ta              HV_FAST_TRAP
 312
 313 after_lock_tlb:
 314         wrpr            %g0, (PSTATE_PRIV | PSTATE_PEF), %pstate
 315         wr              %g0, 0, %fprs
 316
 317         wr              %g0, ASI_P, %asi
 318
 319         mov             PRIMARY_CONTEXT, %g7
 320
 321 661:    stxa            %g0, [%g7] ASI_DMMU
 322         .section        .sun4v_1insn_patch, "ax"
 323         .word           661b
 324         stxa            %g0, [%g7] ASI_MMU
 325         .previous
 326
 327         membar          #Sync
 328         mov             SECONDARY_CONTEXT, %g7
 329
 330 661:    stxa            %g0, [%g7] ASI_DMMU
 331         .section        .sun4v_1insn_patch, "ax"
 332         .word           661b
 333         stxa            %g0, [%g7] ASI_MMU
 334         .previous
 335
 336         membar          #Sync
 337
 338         /* Everything we do here, until we properly take over the
 339          * trap table, must be done with extreme care.  We cannot
 340          * make any references to %g6 (current thread pointer),
 341          * %g4 (current task pointer), or %g5 (base of current cpu's
 342          * per-cpu area) until we properly take over the trap table
 343          * from the firmware and hypervisor.
 344          *
 345          * Get onto temporary stack which is in the locked kernel image.
 346          */
 347         sethi           %hi(tramp_stack), %g1
 348         or              %g1, %lo(tramp_stack), %g1
 349         add             %g1, TRAMP_STACK_SIZE, %g1
 350         sub             %g1, STACKFRAME_SZ + STACK_BIAS + 256, %sp
 351         mov             0, %fp
 352
 353         /* Put garbage in these registers to trap any access to them.  */
 354         set             0xdeadbeef, %g4
 355         set             0xdeadbeef, %g5
 356         set             0xdeadbeef, %g6
 357
 358         call            init_irqwork_curcpu
 359          nop
 360
 361         sethi           %hi(tlb_type), %g3
 362         lduw            [%g3 + %lo(tlb_type)], %g2
 363         cmp             %g2, 3
 364         bne,pt          %icc, 1f
 365          nop
 366
 367         call            hard_smp_processor_id
 368          nop
 369
 370         call            sun4v_register_mondo_queues
 371          nop
 372
 373 1:      call            init_cur_cpu_trap
 374          ldx            [%l0], %o0
 375
 376         /* Start using proper page size encodings in ctx register.  */
 377         sethi           %hi(sparc64_kern_pri_context), %g3
 378         ldx             [%g3 + %lo(sparc64_kern_pri_context)], %g2
 379         mov             PRIMARY_CONTEXT, %g1
 380
 381 661:    stxa            %g2, [%g1] ASI_DMMU
 382         .section        .sun4v_1insn_patch, "ax"
 383         .word           661b
 384         stxa            %g2, [%g1] ASI_MMU
 385         .previous
 386
 387         membar          #Sync
 388
 389         wrpr            %g0, 0, %wstate
 390
 391         /* As a hack, put &init_thread_union into %g6.
 392          * prom_world() loads from here to restore the %asi
 393          * register.
 394          */
 395         sethi           %hi(init_thread_union), %g6
 396         or              %g6, %lo(init_thread_union), %g6
 397
 398         sethi           %hi(is_sun4v), %o0
 399         lduw            [%o0 + %lo(is_sun4v)], %o0
 400         brz,pt          %o0, 1f
 401          nop
 402
 403         TRAP_LOAD_TRAP_BLOCK(%g2, %g3)
 404         add             %g2, TRAP_PER_CPU_FAULT_INFO, %g2
 405         stxa            %g2, [%g0] ASI_SCRATCHPAD
 406
 407         /* Compute physical address:
 408          *
 409          * paddr = kern_base + (mmfsa_vaddr - KERNBASE)
 410          */
 411         sethi           %hi(KERNBASE), %g3
 412         sub             %g2, %g3, %g2
 413         sethi           %hi(kern_base), %g3
 414         ldx             [%g3 + %lo(kern_base)], %g3
 415         add             %g2, %g3, %o1
 416         sethi           %hi(sparc64_ttable_tl0), %o0
 417
 418         set             prom_set_trap_table_name, %g2
 419         stx             %g2, [%sp + 2047 + 128 + 0x00]
 420         mov             2, %g2
 421         stx             %g2, [%sp + 2047 + 128 + 0x08]
 422         mov             0, %g2
 423         stx             %g2, [%sp + 2047 + 128 + 0x10]
 424         stx             %o0, [%sp + 2047 + 128 + 0x18]
 425         stx             %o1, [%sp + 2047 + 128 + 0x20]
 426         sethi           %hi(p1275buf), %g2
 427         or              %g2, %lo(p1275buf), %g2
 428         ldx             [%g2 + 0x08], %o1
 429         call            %o1
 430          add            %sp, (2047 + 128), %o0
 431
 432         ba,pt           %xcc, 2f
 433          nop
 434
 435 1:      sethi           %hi(sparc64_ttable_tl0), %o0
 436         set             prom_set_trap_table_name, %g2
 437         stx             %g2, [%sp + 2047 + 128 + 0x00]
 438         mov             1, %g2
 439         stx             %g2, [%sp + 2047 + 128 + 0x08]
 440         mov             0, %g2
 441         stx             %g2, [%sp + 2047 + 128 + 0x10]
 442         stx             %o0, [%sp + 2047 + 128 + 0x18]
 443         sethi           %hi(p1275buf), %g2
 444         or              %g2, %lo(p1275buf), %g2
 445         ldx             [%g2 + 0x08], %o1
 446         call            %o1
 447          add            %sp, (2047 + 128), %o0
 448
 449 2:      ldx             [%l0], %g6
 450         ldx             [%g6 + TI_TASK], %g4
 451
 452         mov             1, %g5
 453         sllx            %g5, THREAD_SHIFT, %g5
 454         sub             %g5, (STACKFRAME_SZ + STACK_BIAS), %g5
 455         add             %g6, %g5, %sp
 456         mov             0, %fp
 457
 458         rdpr            %pstate, %o1
 459         or              %o1, PSTATE_IE, %o1
 460         wrpr            %o1, 0, %pstate
 461
 462         call            smp_callin
 463          nop
 464         call            cpu_idle
 465          mov            0, %o0
 466         call            cpu_panic
 467          nop
 468 1:      b,a,pt          %xcc, 1b
 469
 470         .align          8
 471 sparc64_cpu_startup_end: