1 /* $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
2 * arch/sparc64/mm/init.c
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 #include <linux/config.h>
9 #include <linux/module.h>
10 #include <linux/kernel.h>
11 #include <linux/sched.h>
12 #include <linux/string.h>
13 #include <linux/init.h>
14 #include <linux/bootmem.h>
16 #include <linux/hugetlb.h>
17 #include <linux/slab.h>
18 #include <linux/initrd.h>
19 #include <linux/swap.h>
20 #include <linux/pagemap.h>
22 #include <linux/seq_file.h>
23 #include <linux/kprobes.h>
24 #include <linux/cache.h>
25 #include <linux/sort.h>
28 #include <asm/system.h>
30 #include <asm/pgalloc.h>
31 #include <asm/pgtable.h>
32 #include <asm/oplib.h>
33 #include <asm/iommu.h>
35 #include <asm/uaccess.h>
36 #include <asm/mmu_context.h>
37 #include <asm/tlbflush.h>
39 #include <asm/starfire.h>
41 #include <asm/spitfire.h>
42 #include <asm/sections.h>
44 #include <asm/hypervisor.h>
46 extern void device_scan(void);
48 #define MAX_PHYS_ADDRESS (1UL << 42UL)
49 #define KPTE_BITMAP_CHUNK_SZ (256UL * 1024UL * 1024UL)
50 #define KPTE_BITMAP_BYTES \
51 ((MAX_PHYS_ADDRESS / KPTE_BITMAP_CHUNK_SZ) / 8)
53 unsigned long kern_linear_pte_xor
[2] __read_mostly
;
55 /* A bitmap, one bit for every 256MB of physical memory. If the bit
56 * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
57 * if set we should use a 256MB page (via kern_linear_pte_xor[1]).
59 unsigned long kpte_linear_bitmap
[KPTE_BITMAP_BYTES
/ sizeof(unsigned long)];
61 /* A special kernel TSB for 4MB and 256MB linear mappings. */
62 struct tsb swapper_4m_tsb
[KERNEL_TSB4M_NENTRIES
];
66 static struct linux_prom64_registers pavail
[MAX_BANKS
] __initdata
;
67 static struct linux_prom64_registers pavail_rescan
[MAX_BANKS
] __initdata
;
68 static int pavail_ents __initdata
;
69 static int pavail_rescan_ents __initdata
;
71 static int cmp_p64(const void *a
, const void *b
)
73 const struct linux_prom64_registers
*x
= a
, *y
= b
;
75 if (x
->phys_addr
> y
->phys_addr
)
77 if (x
->phys_addr
< y
->phys_addr
)
82 static void __init
read_obp_memory(const char *property
,
83 struct linux_prom64_registers
*regs
,
86 int node
= prom_finddevice("/memory");
87 int prop_size
= prom_getproplen(node
, property
);
90 ents
= prop_size
/ sizeof(struct linux_prom64_registers
);
91 if (ents
> MAX_BANKS
) {
92 prom_printf("The machine has more %s property entries than "
93 "this kernel can support (%d).\n",
98 ret
= prom_getproperty(node
, property
, (char *) regs
, prop_size
);
100 prom_printf("Couldn't get %s property from /memory.\n");
106 /* Sanitize what we got from the firmware, by page aligning
109 for (i
= 0; i
< ents
; i
++) {
110 unsigned long base
, size
;
112 base
= regs
[i
].phys_addr
;
113 size
= regs
[i
].reg_size
;
116 if (base
& ~PAGE_MASK
) {
117 unsigned long new_base
= PAGE_ALIGN(base
);
119 size
-= new_base
- base
;
120 if ((long) size
< 0L)
124 regs
[i
].phys_addr
= base
;
125 regs
[i
].reg_size
= size
;
127 sort(regs
, ents
, sizeof(struct linux_prom64_registers
),
131 unsigned long *sparc64_valid_addr_bitmap __read_mostly
;
133 /* Kernel physical address base and size in bytes. */
134 unsigned long kern_base __read_mostly
;
135 unsigned long kern_size __read_mostly
;
137 /* get_new_mmu_context() uses "cache + 1". */
138 DEFINE_SPINLOCK(ctx_alloc_lock
);
139 unsigned long tlb_context_cache
= CTX_FIRST_VERSION
- 1;
140 #define CTX_BMAP_SLOTS (1UL << (CTX_NR_BITS - 6))
141 unsigned long mmu_context_bmap
[CTX_BMAP_SLOTS
];
143 /* References to special section boundaries */
144 extern char _start
[], _end
[];
146 /* Initial ramdisk setup */
147 extern unsigned long sparc_ramdisk_image64
;
148 extern unsigned int sparc_ramdisk_image
;
149 extern unsigned int sparc_ramdisk_size
;
151 struct page
*mem_map_zero __read_mostly
;
153 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly
;
155 unsigned long sparc64_kern_pri_context __read_mostly
;
156 unsigned long sparc64_kern_pri_nuc_bits __read_mostly
;
157 unsigned long sparc64_kern_sec_context __read_mostly
;
161 kmem_cache_t
*pgtable_cache __read_mostly
;
163 static void zero_ctor(void *addr
, kmem_cache_t
*cache
, unsigned long flags
)
168 extern void tsb_cache_init(void);
170 void pgtable_cache_init(void)
172 pgtable_cache
= kmem_cache_create("pgtable_cache",
173 PAGE_SIZE
, PAGE_SIZE
,
175 SLAB_MUST_HWCACHE_ALIGN
,
178 if (!pgtable_cache
) {
179 prom_printf("Could not create pgtable_cache\n");
185 #ifdef CONFIG_DEBUG_DCFLUSH
186 atomic_t dcpage_flushes
= ATOMIC_INIT(0);
188 atomic_t dcpage_flushes_xcall
= ATOMIC_INIT(0);
192 inline void flush_dcache_page_impl(struct page
*page
)
194 BUG_ON(tlb_type
== hypervisor
);
195 #ifdef CONFIG_DEBUG_DCFLUSH
196 atomic_inc(&dcpage_flushes
);
199 #ifdef DCACHE_ALIASING_POSSIBLE
200 __flush_dcache_page(page_address(page
),
201 ((tlb_type
== spitfire
) &&
202 page_mapping(page
) != NULL
));
204 if (page_mapping(page
) != NULL
&&
205 tlb_type
== spitfire
)
206 __flush_icache_page(__pa(page_address(page
)));
210 #define PG_dcache_dirty PG_arch_1
211 #define PG_dcache_cpu_shift 24UL
212 #define PG_dcache_cpu_mask (256UL - 1UL)
215 #error D-cache dirty tracking and thread_info->cpu need fixing for > 256 cpus
218 #define dcache_dirty_cpu(page) \
219 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
221 static __inline__
void set_dcache_dirty(struct page
*page
, int this_cpu
)
223 unsigned long mask
= this_cpu
;
224 unsigned long non_cpu_bits
;
226 non_cpu_bits
= ~(PG_dcache_cpu_mask
<< PG_dcache_cpu_shift
);
227 mask
= (mask
<< PG_dcache_cpu_shift
) | (1UL << PG_dcache_dirty
);
229 __asm__
__volatile__("1:\n\t"
231 "and %%g7, %1, %%g1\n\t"
232 "or %%g1, %0, %%g1\n\t"
233 "casx [%2], %%g7, %%g1\n\t"
235 "membar #StoreLoad | #StoreStore\n\t"
236 "bne,pn %%xcc, 1b\n\t"
239 : "r" (mask
), "r" (non_cpu_bits
), "r" (&page
->flags
)
243 static __inline__
void clear_dcache_dirty_cpu(struct page
*page
, unsigned long cpu
)
245 unsigned long mask
= (1UL << PG_dcache_dirty
);
247 __asm__
__volatile__("! test_and_clear_dcache_dirty\n"
250 "srlx %%g7, %4, %%g1\n\t"
251 "and %%g1, %3, %%g1\n\t"
253 "bne,pn %%icc, 2f\n\t"
254 " andn %%g7, %1, %%g1\n\t"
255 "casx [%2], %%g7, %%g1\n\t"
257 "membar #StoreLoad | #StoreStore\n\t"
258 "bne,pn %%xcc, 1b\n\t"
262 : "r" (cpu
), "r" (mask
), "r" (&page
->flags
),
263 "i" (PG_dcache_cpu_mask
),
264 "i" (PG_dcache_cpu_shift
)
268 static inline void tsb_insert(struct tsb
*ent
, unsigned long tag
, unsigned long pte
)
270 unsigned long tsb_addr
= (unsigned long) ent
;
272 if (tlb_type
== cheetah_plus
|| tlb_type
== hypervisor
)
273 tsb_addr
= __pa(tsb_addr
);
275 __tsb_insert(tsb_addr
, tag
, pte
);
278 unsigned long _PAGE_ALL_SZ_BITS __read_mostly
;
279 unsigned long _PAGE_SZBITS __read_mostly
;
281 void update_mmu_cache(struct vm_area_struct
*vma
, unsigned long address
, pte_t pte
)
283 struct mm_struct
*mm
;
285 unsigned long tag
, flags
;
287 if (tlb_type
!= hypervisor
) {
288 unsigned long pfn
= pte_pfn(pte
);
289 unsigned long pg_flags
;
292 if (pfn_valid(pfn
) &&
293 (page
= pfn_to_page(pfn
), page_mapping(page
)) &&
294 ((pg_flags
= page
->flags
) & (1UL << PG_dcache_dirty
))) {
295 int cpu
= ((pg_flags
>> PG_dcache_cpu_shift
) &
297 int this_cpu
= get_cpu();
299 /* This is just to optimize away some function calls
303 flush_dcache_page_impl(page
);
305 smp_flush_dcache_page_impl(page
, cpu
);
307 clear_dcache_dirty_cpu(page
, cpu
);
315 spin_lock_irqsave(&mm
->context
.lock
, flags
);
317 tsb
= &mm
->context
.tsb
[(address
>> PAGE_SHIFT
) &
318 (mm
->context
.tsb_nentries
- 1UL)];
319 tag
= (address
>> 22UL);
320 tsb_insert(tsb
, tag
, pte_val(pte
));
322 spin_unlock_irqrestore(&mm
->context
.lock
, flags
);
325 void flush_dcache_page(struct page
*page
)
327 struct address_space
*mapping
;
330 if (tlb_type
== hypervisor
)
333 /* Do not bother with the expensive D-cache flush if it
334 * is merely the zero page. The 'bigcore' testcase in GDB
335 * causes this case to run millions of times.
337 if (page
== ZERO_PAGE(0))
340 this_cpu
= get_cpu();
342 mapping
= page_mapping(page
);
343 if (mapping
&& !mapping_mapped(mapping
)) {
344 int dirty
= test_bit(PG_dcache_dirty
, &page
->flags
);
346 int dirty_cpu
= dcache_dirty_cpu(page
);
348 if (dirty_cpu
== this_cpu
)
350 smp_flush_dcache_page_impl(page
, dirty_cpu
);
352 set_dcache_dirty(page
, this_cpu
);
354 /* We could delay the flush for the !page_mapping
355 * case too. But that case is for exec env/arg
356 * pages and those are %99 certainly going to get
357 * faulted into the tlb (and thus flushed) anyways.
359 flush_dcache_page_impl(page
);
366 void __kprobes
flush_icache_range(unsigned long start
, unsigned long end
)
368 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
369 if (tlb_type
== spitfire
) {
372 for (kaddr
= start
; kaddr
< end
; kaddr
+= PAGE_SIZE
)
373 __flush_icache_page(__get_phys(kaddr
));
379 printk("Mem-info:\n");
381 printk("Free swap: %6ldkB\n",
382 nr_swap_pages
<< (PAGE_SHIFT
-10));
383 printk("%ld pages of RAM\n", num_physpages
);
384 printk("%d free pages\n", nr_free_pages());
387 void mmu_info(struct seq_file
*m
)
389 if (tlb_type
== cheetah
)
390 seq_printf(m
, "MMU Type\t: Cheetah\n");
391 else if (tlb_type
== cheetah_plus
)
392 seq_printf(m
, "MMU Type\t: Cheetah+\n");
393 else if (tlb_type
== spitfire
)
394 seq_printf(m
, "MMU Type\t: Spitfire\n");
395 else if (tlb_type
== hypervisor
)
396 seq_printf(m
, "MMU Type\t: Hypervisor (sun4v)\n");
398 seq_printf(m
, "MMU Type\t: ???\n");
400 #ifdef CONFIG_DEBUG_DCFLUSH
401 seq_printf(m
, "DCPageFlushes\t: %d\n",
402 atomic_read(&dcpage_flushes
));
404 seq_printf(m
, "DCPageFlushesXC\t: %d\n",
405 atomic_read(&dcpage_flushes_xcall
));
406 #endif /* CONFIG_SMP */
407 #endif /* CONFIG_DEBUG_DCFLUSH */
410 struct linux_prom_translation
{
416 /* Exported for kernel TLB miss handling in ktlb.S */
417 struct linux_prom_translation prom_trans
[512] __read_mostly
;
418 unsigned int prom_trans_ents __read_mostly
;
420 /* Exported for SMP bootup purposes. */
421 unsigned long kern_locked_tte_data
;
423 /* The obp translations are saved based on 8k pagesize, since obp can
424 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
425 * HI_OBP_ADDRESS range are handled in ktlb.S.
427 static inline int in_obp_range(unsigned long vaddr
)
429 return (vaddr
>= LOW_OBP_ADDRESS
&&
430 vaddr
< HI_OBP_ADDRESS
);
433 static int cmp_ptrans(const void *a
, const void *b
)
435 const struct linux_prom_translation
*x
= a
, *y
= b
;
437 if (x
->virt
> y
->virt
)
439 if (x
->virt
< y
->virt
)
444 /* Read OBP translations property into 'prom_trans[]'. */
445 static void __init
read_obp_translations(void)
447 int n
, node
, ents
, first
, last
, i
;
449 node
= prom_finddevice("/virtual-memory");
450 n
= prom_getproplen(node
, "translations");
451 if (unlikely(n
== 0 || n
== -1)) {
452 prom_printf("prom_mappings: Couldn't get size.\n");
455 if (unlikely(n
> sizeof(prom_trans
))) {
456 prom_printf("prom_mappings: Size %Zd is too big.\n", n
);
460 if ((n
= prom_getproperty(node
, "translations",
461 (char *)&prom_trans
[0],
462 sizeof(prom_trans
))) == -1) {
463 prom_printf("prom_mappings: Couldn't get property.\n");
467 n
= n
/ sizeof(struct linux_prom_translation
);
471 sort(prom_trans
, ents
, sizeof(struct linux_prom_translation
),
474 /* Now kick out all the non-OBP entries. */
475 for (i
= 0; i
< ents
; i
++) {
476 if (in_obp_range(prom_trans
[i
].virt
))
480 for (; i
< ents
; i
++) {
481 if (!in_obp_range(prom_trans
[i
].virt
))
486 for (i
= 0; i
< (last
- first
); i
++) {
487 struct linux_prom_translation
*src
= &prom_trans
[i
+ first
];
488 struct linux_prom_translation
*dest
= &prom_trans
[i
];
492 for (; i
< ents
; i
++) {
493 struct linux_prom_translation
*dest
= &prom_trans
[i
];
494 dest
->virt
= dest
->size
= dest
->data
= 0x0UL
;
497 prom_trans_ents
= last
- first
;
499 if (tlb_type
== spitfire
) {
500 /* Clear diag TTE bits. */
501 for (i
= 0; i
< prom_trans_ents
; i
++)
502 prom_trans
[i
].data
&= ~0x0003fe0000000000UL
;
506 static void __init
hypervisor_tlb_lock(unsigned long vaddr
,
510 register unsigned long func
asm("%o5");
511 register unsigned long arg0
asm("%o0");
512 register unsigned long arg1
asm("%o1");
513 register unsigned long arg2
asm("%o2");
514 register unsigned long arg3
asm("%o3");
516 func
= HV_FAST_MMU_MAP_PERM_ADDR
;
521 __asm__
__volatile__("ta 0x80"
522 : "=&r" (func
), "=&r" (arg0
),
523 "=&r" (arg1
), "=&r" (arg2
),
525 : "0" (func
), "1" (arg0
), "2" (arg1
),
526 "3" (arg2
), "4" (arg3
));
528 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
529 "errors with %lx\n", vaddr
, 0, pte
, mmu
, arg0
);
534 static unsigned long kern_large_tte(unsigned long paddr
);
536 static void __init
remap_kernel(void)
538 unsigned long phys_page
, tte_vaddr
, tte_data
;
539 int tlb_ent
= sparc64_highest_locked_tlbent();
541 tte_vaddr
= (unsigned long) KERNBASE
;
542 phys_page
= (prom_boot_mapping_phys_low
>> 22UL) << 22UL;
543 tte_data
= kern_large_tte(phys_page
);
545 kern_locked_tte_data
= tte_data
;
547 /* Now lock us into the TLBs via Hypervisor or OBP. */
548 if (tlb_type
== hypervisor
) {
549 hypervisor_tlb_lock(tte_vaddr
, tte_data
, HV_MMU_DMMU
);
550 hypervisor_tlb_lock(tte_vaddr
, tte_data
, HV_MMU_IMMU
);
552 tte_vaddr
+= 0x400000;
553 tte_data
+= 0x400000;
554 hypervisor_tlb_lock(tte_vaddr
, tte_data
, HV_MMU_DMMU
);
555 hypervisor_tlb_lock(tte_vaddr
, tte_data
, HV_MMU_IMMU
);
558 prom_dtlb_load(tlb_ent
, tte_data
, tte_vaddr
);
559 prom_itlb_load(tlb_ent
, tte_data
, tte_vaddr
);
562 prom_dtlb_load(tlb_ent
,
564 tte_vaddr
+ 0x400000);
565 prom_itlb_load(tlb_ent
,
567 tte_vaddr
+ 0x400000);
569 sparc64_highest_unlocked_tlb_ent
= tlb_ent
- 1;
571 if (tlb_type
== cheetah_plus
) {
572 sparc64_kern_pri_context
= (CTX_CHEETAH_PLUS_CTX0
|
573 CTX_CHEETAH_PLUS_NUC
);
574 sparc64_kern_pri_nuc_bits
= CTX_CHEETAH_PLUS_NUC
;
575 sparc64_kern_sec_context
= CTX_CHEETAH_PLUS_CTX0
;
580 static void __init
inherit_prom_mappings(void)
582 read_obp_translations();
584 /* Now fixup OBP's idea about where we really are mapped. */
585 prom_printf("Remapping the kernel... ");
587 prom_printf("done.\n");
590 void prom_world(int enter
)
593 set_fs((mm_segment_t
) { get_thread_current_ds() });
595 __asm__
__volatile__("flushw");
598 #ifdef DCACHE_ALIASING_POSSIBLE
599 void __flush_dcache_range(unsigned long start
, unsigned long end
)
603 if (tlb_type
== spitfire
) {
606 for (va
= start
; va
< end
; va
+= 32) {
607 spitfire_put_dcache_tag(va
& 0x3fe0, 0x0);
611 } else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
614 for (va
= start
; va
< end
; va
+= 32)
615 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
619 "i" (ASI_DCACHE_INVALIDATE
));
622 #endif /* DCACHE_ALIASING_POSSIBLE */
624 /* Caller does TLB context flushing on local CPU if necessary.
625 * The caller also ensures that CTX_VALID(mm->context) is false.
627 * We must be careful about boundary cases so that we never
628 * let the user have CTX 0 (nucleus) or we ever use a CTX
629 * version of zero (and thus NO_CONTEXT would not be caught
630 * by version mis-match tests in mmu_context.h).
632 * Always invoked with interrupts disabled.
634 void get_new_mmu_context(struct mm_struct
*mm
)
636 unsigned long ctx
, new_ctx
;
637 unsigned long orig_pgsz_bits
;
641 spin_lock_irqsave(&ctx_alloc_lock
, flags
);
642 orig_pgsz_bits
= (mm
->context
.sparc64_ctx_val
& CTX_PGSZ_MASK
);
643 ctx
= (tlb_context_cache
+ 1) & CTX_NR_MASK
;
644 new_ctx
= find_next_zero_bit(mmu_context_bmap
, 1 << CTX_NR_BITS
, ctx
);
646 if (new_ctx
>= (1 << CTX_NR_BITS
)) {
647 new_ctx
= find_next_zero_bit(mmu_context_bmap
, ctx
, 1);
648 if (new_ctx
>= ctx
) {
650 new_ctx
= (tlb_context_cache
& CTX_VERSION_MASK
) +
653 new_ctx
= CTX_FIRST_VERSION
;
655 /* Don't call memset, for 16 entries that's just
658 mmu_context_bmap
[0] = 3;
659 mmu_context_bmap
[1] = 0;
660 mmu_context_bmap
[2] = 0;
661 mmu_context_bmap
[3] = 0;
662 for (i
= 4; i
< CTX_BMAP_SLOTS
; i
+= 4) {
663 mmu_context_bmap
[i
+ 0] = 0;
664 mmu_context_bmap
[i
+ 1] = 0;
665 mmu_context_bmap
[i
+ 2] = 0;
666 mmu_context_bmap
[i
+ 3] = 0;
672 mmu_context_bmap
[new_ctx
>>6] |= (1UL << (new_ctx
& 63));
673 new_ctx
|= (tlb_context_cache
& CTX_VERSION_MASK
);
675 tlb_context_cache
= new_ctx
;
676 mm
->context
.sparc64_ctx_val
= new_ctx
| orig_pgsz_bits
;
677 spin_unlock_irqrestore(&ctx_alloc_lock
, flags
);
679 if (unlikely(new_version
))
680 smp_new_mmu_context_version();
683 void sparc_ultra_dump_itlb(void)
687 if (tlb_type
== spitfire
) {
688 printk ("Contents of itlb: ");
689 for (slot
= 0; slot
< 14; slot
++) printk (" ");
690 printk ("%2x:%016lx,%016lx\n",
692 spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0));
693 for (slot
= 1; slot
< 64; slot
+=3) {
694 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
696 spitfire_get_itlb_tag(slot
), spitfire_get_itlb_data(slot
),
698 spitfire_get_itlb_tag(slot
+1), spitfire_get_itlb_data(slot
+1),
700 spitfire_get_itlb_tag(slot
+2), spitfire_get_itlb_data(slot
+2));
702 } else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
703 printk ("Contents of itlb0:\n");
704 for (slot
= 0; slot
< 16; slot
+=2) {
705 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
707 cheetah_get_litlb_tag(slot
), cheetah_get_litlb_data(slot
),
709 cheetah_get_litlb_tag(slot
+1), cheetah_get_litlb_data(slot
+1));
711 printk ("Contents of itlb2:\n");
712 for (slot
= 0; slot
< 128; slot
+=2) {
713 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
715 cheetah_get_itlb_tag(slot
), cheetah_get_itlb_data(slot
),
717 cheetah_get_itlb_tag(slot
+1), cheetah_get_itlb_data(slot
+1));
722 void sparc_ultra_dump_dtlb(void)
726 if (tlb_type
== spitfire
) {
727 printk ("Contents of dtlb: ");
728 for (slot
= 0; slot
< 14; slot
++) printk (" ");
729 printk ("%2x:%016lx,%016lx\n", 0,
730 spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0));
731 for (slot
= 1; slot
< 64; slot
+=3) {
732 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
734 spitfire_get_dtlb_tag(slot
), spitfire_get_dtlb_data(slot
),
736 spitfire_get_dtlb_tag(slot
+1), spitfire_get_dtlb_data(slot
+1),
738 spitfire_get_dtlb_tag(slot
+2), spitfire_get_dtlb_data(slot
+2));
740 } else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
741 printk ("Contents of dtlb0:\n");
742 for (slot
= 0; slot
< 16; slot
+=2) {
743 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
745 cheetah_get_ldtlb_tag(slot
), cheetah_get_ldtlb_data(slot
),
747 cheetah_get_ldtlb_tag(slot
+1), cheetah_get_ldtlb_data(slot
+1));
749 printk ("Contents of dtlb2:\n");
750 for (slot
= 0; slot
< 512; slot
+=2) {
751 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
753 cheetah_get_dtlb_tag(slot
, 2), cheetah_get_dtlb_data(slot
, 2),
755 cheetah_get_dtlb_tag(slot
+1, 2), cheetah_get_dtlb_data(slot
+1, 2));
757 if (tlb_type
== cheetah_plus
) {
758 printk ("Contents of dtlb3:\n");
759 for (slot
= 0; slot
< 512; slot
+=2) {
760 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
762 cheetah_get_dtlb_tag(slot
, 3), cheetah_get_dtlb_data(slot
, 3),
764 cheetah_get_dtlb_tag(slot
+1, 3), cheetah_get_dtlb_data(slot
+1, 3));
770 extern unsigned long cmdline_memory_size
;
772 /* Find a free area for the bootmem map, avoiding the kernel image
773 * and the initial ramdisk.
775 static unsigned long __init
choose_bootmap_pfn(unsigned long start_pfn
,
776 unsigned long end_pfn
)
778 unsigned long avoid_start
, avoid_end
, bootmap_size
;
781 bootmap_size
= ((end_pfn
- start_pfn
) + 7) / 8;
782 bootmap_size
= ALIGN(bootmap_size
, sizeof(long));
784 avoid_start
= avoid_end
= 0;
785 #ifdef CONFIG_BLK_DEV_INITRD
786 avoid_start
= initrd_start
;
787 avoid_end
= PAGE_ALIGN(initrd_end
);
790 #ifdef CONFIG_DEBUG_BOOTMEM
791 prom_printf("choose_bootmap_pfn: kern[%lx:%lx] avoid[%lx:%lx]\n",
792 kern_base
, PAGE_ALIGN(kern_base
+ kern_size
),
793 avoid_start
, avoid_end
);
795 for (i
= 0; i
< pavail_ents
; i
++) {
796 unsigned long start
, end
;
798 start
= pavail
[i
].phys_addr
;
799 end
= start
+ pavail
[i
].reg_size
;
801 while (start
< end
) {
802 if (start
>= kern_base
&&
803 start
< PAGE_ALIGN(kern_base
+ kern_size
)) {
804 start
= PAGE_ALIGN(kern_base
+ kern_size
);
807 if (start
>= avoid_start
&& start
< avoid_end
) {
812 if ((end
- start
) < bootmap_size
)
815 if (start
< kern_base
&&
816 (start
+ bootmap_size
) > kern_base
) {
817 start
= PAGE_ALIGN(kern_base
+ kern_size
);
821 if (start
< avoid_start
&&
822 (start
+ bootmap_size
) > avoid_start
) {
827 /* OK, it doesn't overlap anything, use it. */
828 #ifdef CONFIG_DEBUG_BOOTMEM
829 prom_printf("choose_bootmap_pfn: Using %lx [%lx]\n",
830 start
>> PAGE_SHIFT
, start
);
832 return start
>> PAGE_SHIFT
;
836 prom_printf("Cannot find free area for bootmap, aborting.\n");
840 static unsigned long __init
bootmem_init(unsigned long *pages_avail
,
841 unsigned long phys_base
)
843 unsigned long bootmap_size
, end_pfn
;
844 unsigned long end_of_phys_memory
= 0UL;
845 unsigned long bootmap_pfn
, bytes_avail
, size
;
848 #ifdef CONFIG_DEBUG_BOOTMEM
849 prom_printf("bootmem_init: Scan pavail, ");
853 for (i
= 0; i
< pavail_ents
; i
++) {
854 end_of_phys_memory
= pavail
[i
].phys_addr
+
856 bytes_avail
+= pavail
[i
].reg_size
;
857 if (cmdline_memory_size
) {
858 if (bytes_avail
> cmdline_memory_size
) {
859 unsigned long slack
= bytes_avail
- cmdline_memory_size
;
861 bytes_avail
-= slack
;
862 end_of_phys_memory
-= slack
;
864 pavail
[i
].reg_size
-= slack
;
865 if ((long)pavail
[i
].reg_size
<= 0L) {
866 pavail
[i
].phys_addr
= 0xdeadbeefUL
;
867 pavail
[i
].reg_size
= 0UL;
870 pavail
[i
+1].reg_size
= 0Ul;
871 pavail
[i
+1].phys_addr
= 0xdeadbeefUL
;
879 *pages_avail
= bytes_avail
>> PAGE_SHIFT
;
881 end_pfn
= end_of_phys_memory
>> PAGE_SHIFT
;
883 #ifdef CONFIG_BLK_DEV_INITRD
884 /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
885 if (sparc_ramdisk_image
|| sparc_ramdisk_image64
) {
886 unsigned long ramdisk_image
= sparc_ramdisk_image
?
887 sparc_ramdisk_image
: sparc_ramdisk_image64
;
888 if (ramdisk_image
>= (unsigned long)_end
- 2 * PAGE_SIZE
)
889 ramdisk_image
-= KERNBASE
;
890 initrd_start
= ramdisk_image
+ phys_base
;
891 initrd_end
= initrd_start
+ sparc_ramdisk_size
;
892 if (initrd_end
> end_of_phys_memory
) {
893 printk(KERN_CRIT
"initrd extends beyond end of memory "
894 "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
895 initrd_end
, end_of_phys_memory
);
901 /* Initialize the boot-time allocator. */
902 max_pfn
= max_low_pfn
= end_pfn
;
903 min_low_pfn
= (phys_base
>> PAGE_SHIFT
);
905 bootmap_pfn
= choose_bootmap_pfn(min_low_pfn
, end_pfn
);
907 #ifdef CONFIG_DEBUG_BOOTMEM
908 prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
909 min_low_pfn
, bootmap_pfn
, max_low_pfn
);
911 bootmap_size
= init_bootmem_node(NODE_DATA(0), bootmap_pfn
,
912 min_low_pfn
, end_pfn
);
914 /* Now register the available physical memory with the
917 for (i
= 0; i
< pavail_ents
; i
++) {
918 #ifdef CONFIG_DEBUG_BOOTMEM
919 prom_printf("free_bootmem(pavail:%d): base[%lx] size[%lx]\n",
920 i
, pavail
[i
].phys_addr
, pavail
[i
].reg_size
);
922 free_bootmem(pavail
[i
].phys_addr
, pavail
[i
].reg_size
);
925 #ifdef CONFIG_BLK_DEV_INITRD
927 size
= initrd_end
- initrd_start
;
929 /* Resert the initrd image area. */
930 #ifdef CONFIG_DEBUG_BOOTMEM
931 prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
932 initrd_start
, initrd_end
);
934 reserve_bootmem(initrd_start
, size
);
935 *pages_avail
-= PAGE_ALIGN(size
) >> PAGE_SHIFT
;
937 initrd_start
+= PAGE_OFFSET
;
938 initrd_end
+= PAGE_OFFSET
;
941 /* Reserve the kernel text/data/bss. */
942 #ifdef CONFIG_DEBUG_BOOTMEM
943 prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base
, kern_size
);
945 reserve_bootmem(kern_base
, kern_size
);
946 *pages_avail
-= PAGE_ALIGN(kern_size
) >> PAGE_SHIFT
;
948 /* Reserve the bootmem map. We do not account for it
949 * in pages_avail because we will release that memory
950 * in free_all_bootmem.
953 #ifdef CONFIG_DEBUG_BOOTMEM
954 prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
955 (bootmap_pfn
<< PAGE_SHIFT
), size
);
957 reserve_bootmem((bootmap_pfn
<< PAGE_SHIFT
), size
);
958 *pages_avail
-= PAGE_ALIGN(size
) >> PAGE_SHIFT
;
960 for (i
= 0; i
< pavail_ents
; i
++) {
961 unsigned long start_pfn
, end_pfn
;
963 start_pfn
= pavail
[i
].phys_addr
>> PAGE_SHIFT
;
964 end_pfn
= (start_pfn
+ (pavail
[i
].reg_size
>> PAGE_SHIFT
));
965 #ifdef CONFIG_DEBUG_BOOTMEM
966 prom_printf("memory_present(0, %lx, %lx)\n",
969 memory_present(0, start_pfn
, end_pfn
);
977 static struct linux_prom64_registers pall
[MAX_BANKS
] __initdata
;
978 static int pall_ents __initdata
;
980 #ifdef CONFIG_DEBUG_PAGEALLOC
981 static unsigned long kernel_map_range(unsigned long pstart
, unsigned long pend
, pgprot_t prot
)
983 unsigned long vstart
= PAGE_OFFSET
+ pstart
;
984 unsigned long vend
= PAGE_OFFSET
+ pend
;
985 unsigned long alloc_bytes
= 0UL;
987 if ((vstart
& ~PAGE_MASK
) || (vend
& ~PAGE_MASK
)) {
988 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
993 while (vstart
< vend
) {
994 unsigned long this_end
, paddr
= __pa(vstart
);
995 pgd_t
*pgd
= pgd_offset_k(vstart
);
1000 pud
= pud_offset(pgd
, vstart
);
1001 if (pud_none(*pud
)) {
1004 new = __alloc_bootmem(PAGE_SIZE
, PAGE_SIZE
, PAGE_SIZE
);
1005 alloc_bytes
+= PAGE_SIZE
;
1006 pud_populate(&init_mm
, pud
, new);
1009 pmd
= pmd_offset(pud
, vstart
);
1010 if (!pmd_present(*pmd
)) {
1013 new = __alloc_bootmem(PAGE_SIZE
, PAGE_SIZE
, PAGE_SIZE
);
1014 alloc_bytes
+= PAGE_SIZE
;
1015 pmd_populate_kernel(&init_mm
, pmd
, new);
1018 pte
= pte_offset_kernel(pmd
, vstart
);
1019 this_end
= (vstart
+ PMD_SIZE
) & PMD_MASK
;
1020 if (this_end
> vend
)
1023 while (vstart
< this_end
) {
1024 pte_val(*pte
) = (paddr
| pgprot_val(prot
));
1026 vstart
+= PAGE_SIZE
;
1035 extern unsigned int kvmap_linear_patch
[1];
1036 #endif /* CONFIG_DEBUG_PAGEALLOC */
1038 static void __init
mark_kpte_bitmap(unsigned long start
, unsigned long end
)
1040 const unsigned long shift_256MB
= 28;
1041 const unsigned long mask_256MB
= ((1UL << shift_256MB
) - 1UL);
1042 const unsigned long size_256MB
= (1UL << shift_256MB
);
1044 while (start
< end
) {
1047 remains
= end
- start
;
1048 if (remains
< size_256MB
)
1051 if (start
& mask_256MB
) {
1052 start
= (start
+ size_256MB
) & ~mask_256MB
;
1056 while (remains
>= size_256MB
) {
1057 unsigned long index
= start
>> shift_256MB
;
1059 __set_bit(index
, kpte_linear_bitmap
);
1061 start
+= size_256MB
;
1062 remains
-= size_256MB
;
1067 static void __init
kernel_physical_mapping_init(void)
1070 #ifdef CONFIG_DEBUG_PAGEALLOC
1071 unsigned long mem_alloced
= 0UL;
1074 read_obp_memory("reg", &pall
[0], &pall_ents
);
1076 for (i
= 0; i
< pall_ents
; i
++) {
1077 unsigned long phys_start
, phys_end
;
1079 phys_start
= pall
[i
].phys_addr
;
1080 phys_end
= phys_start
+ pall
[i
].reg_size
;
1082 mark_kpte_bitmap(phys_start
, phys_end
);
1084 #ifdef CONFIG_DEBUG_PAGEALLOC
1085 mem_alloced
+= kernel_map_range(phys_start
, phys_end
,
1090 #ifdef CONFIG_DEBUG_PAGEALLOC
1091 printk("Allocated %ld bytes for kernel page tables.\n",
1094 kvmap_linear_patch
[0] = 0x01000000; /* nop */
1095 flushi(&kvmap_linear_patch
[0]);
1101 #ifdef CONFIG_DEBUG_PAGEALLOC
1102 void kernel_map_pages(struct page
*page
, int numpages
, int enable
)
1104 unsigned long phys_start
= page_to_pfn(page
) << PAGE_SHIFT
;
1105 unsigned long phys_end
= phys_start
+ (numpages
* PAGE_SIZE
);
1107 kernel_map_range(phys_start
, phys_end
,
1108 (enable
? PAGE_KERNEL
: __pgprot(0)));
1110 flush_tsb_kernel_range(PAGE_OFFSET
+ phys_start
,
1111 PAGE_OFFSET
+ phys_end
);
1113 /* we should perform an IPI and flush all tlbs,
1114 * but that can deadlock->flush only current cpu.
1116 __flush_tlb_kernel_range(PAGE_OFFSET
+ phys_start
,
1117 PAGE_OFFSET
+ phys_end
);
1121 unsigned long __init
find_ecache_flush_span(unsigned long size
)
1125 for (i
= 0; i
< pavail_ents
; i
++) {
1126 if (pavail
[i
].reg_size
>= size
)
1127 return pavail
[i
].phys_addr
;
1133 static void __init
tsb_phys_patch(void)
1135 struct tsb_ldquad_phys_patch_entry
*pquad
;
1136 struct tsb_phys_patch_entry
*p
;
1138 pquad
= &__tsb_ldquad_phys_patch
;
1139 while (pquad
< &__tsb_ldquad_phys_patch_end
) {
1140 unsigned long addr
= pquad
->addr
;
1142 if (tlb_type
== hypervisor
)
1143 *(unsigned int *) addr
= pquad
->sun4v_insn
;
1145 *(unsigned int *) addr
= pquad
->sun4u_insn
;
1147 __asm__
__volatile__("flush %0"
1154 p
= &__tsb_phys_patch
;
1155 while (p
< &__tsb_phys_patch_end
) {
1156 unsigned long addr
= p
->addr
;
1158 *(unsigned int *) addr
= p
->insn
;
1160 __asm__
__volatile__("flush %0"
1168 /* Don't mark as init, we give this to the Hypervisor. */
1169 static struct hv_tsb_descr ktsb_descr
[2];
1170 extern struct tsb swapper_tsb
[KERNEL_TSB_NENTRIES
];
1172 static void __init
sun4v_ktsb_init(void)
1174 unsigned long ktsb_pa
;
1176 /* First KTSB for PAGE_SIZE mappings. */
1177 ktsb_pa
= kern_base
+ ((unsigned long)&swapper_tsb
[0] - KERNBASE
);
1179 switch (PAGE_SIZE
) {
1182 ktsb_descr
[0].pgsz_idx
= HV_PGSZ_IDX_8K
;
1183 ktsb_descr
[0].pgsz_mask
= HV_PGSZ_MASK_8K
;
1187 ktsb_descr
[0].pgsz_idx
= HV_PGSZ_IDX_64K
;
1188 ktsb_descr
[0].pgsz_mask
= HV_PGSZ_MASK_64K
;
1192 ktsb_descr
[0].pgsz_idx
= HV_PGSZ_IDX_512K
;
1193 ktsb_descr
[0].pgsz_mask
= HV_PGSZ_MASK_512K
;
1196 case 4 * 1024 * 1024:
1197 ktsb_descr
[0].pgsz_idx
= HV_PGSZ_IDX_4MB
;
1198 ktsb_descr
[0].pgsz_mask
= HV_PGSZ_MASK_4MB
;
1202 ktsb_descr
[0].assoc
= 1;
1203 ktsb_descr
[0].num_ttes
= KERNEL_TSB_NENTRIES
;
1204 ktsb_descr
[0].ctx_idx
= 0;
1205 ktsb_descr
[0].tsb_base
= ktsb_pa
;
1206 ktsb_descr
[0].resv
= 0;
1208 /* Second KTSB for 4MB/256MB mappings. */
1209 ktsb_pa
= (kern_base
+
1210 ((unsigned long)&swapper_4m_tsb
[0] - KERNBASE
));
1212 ktsb_descr
[1].pgsz_idx
= HV_PGSZ_IDX_4MB
;
1213 ktsb_descr
[1].pgsz_mask
= (HV_PGSZ_MASK_4MB
|
1214 HV_PGSZ_MASK_256MB
);
1215 ktsb_descr
[1].assoc
= 1;
1216 ktsb_descr
[1].num_ttes
= KERNEL_TSB4M_NENTRIES
;
1217 ktsb_descr
[1].ctx_idx
= 0;
1218 ktsb_descr
[1].tsb_base
= ktsb_pa
;
1219 ktsb_descr
[1].resv
= 0;
1222 void __cpuinit
sun4v_ktsb_register(void)
1224 register unsigned long func
asm("%o5");
1225 register unsigned long arg0
asm("%o0");
1226 register unsigned long arg1
asm("%o1");
1229 pa
= kern_base
+ ((unsigned long)&ktsb_descr
[0] - KERNBASE
);
1231 func
= HV_FAST_MMU_TSB_CTX0
;
1234 __asm__
__volatile__("ta %6"
1235 : "=&r" (func
), "=&r" (arg0
), "=&r" (arg1
)
1236 : "0" (func
), "1" (arg0
), "2" (arg1
),
1237 "i" (HV_FAST_TRAP
));
1240 /* paging_init() sets up the page tables */
1242 extern void cheetah_ecache_flush_init(void);
1243 extern void sun4v_patch_tlb_handlers(void);
1245 static unsigned long last_valid_pfn
;
1246 pgd_t swapper_pg_dir
[2048];
1248 static void sun4u_pgprot_init(void);
1249 static void sun4v_pgprot_init(void);
1251 void __init
paging_init(void)
1253 unsigned long end_pfn
, pages_avail
, shift
, phys_base
;
1254 unsigned long real_end
, i
;
1256 kern_base
= (prom_boot_mapping_phys_low
>> 22UL) << 22UL;
1257 kern_size
= (unsigned long)&_end
- (unsigned long)KERNBASE
;
1259 /* Invalidate both kernel TSBs. */
1260 memset(swapper_tsb
, 0x40, sizeof(swapper_tsb
));
1261 memset(swapper_4m_tsb
, 0x40, sizeof(swapper_4m_tsb
));
1263 if (tlb_type
== hypervisor
)
1264 sun4v_pgprot_init();
1266 sun4u_pgprot_init();
1268 if (tlb_type
== cheetah_plus
||
1269 tlb_type
== hypervisor
)
1272 if (tlb_type
== hypervisor
) {
1273 sun4v_patch_tlb_handlers();
1277 /* Find available physical memory... */
1278 read_obp_memory("available", &pavail
[0], &pavail_ents
);
1280 phys_base
= 0xffffffffffffffffUL
;
1281 for (i
= 0; i
< pavail_ents
; i
++)
1282 phys_base
= min(phys_base
, pavail
[i
].phys_addr
);
1284 set_bit(0, mmu_context_bmap
);
1286 shift
= kern_base
+ PAGE_OFFSET
- ((unsigned long)KERNBASE
);
1288 real_end
= (unsigned long)_end
;
1289 if ((real_end
> ((unsigned long)KERNBASE
+ 0x400000)))
1291 if ((real_end
> ((unsigned long)KERNBASE
+ 0x800000))) {
1292 prom_printf("paging_init: Kernel > 8MB, too large.\n");
1296 /* Set kernel pgd to upper alias so physical page computations
1299 init_mm
.pgd
+= ((shift
) / (sizeof(pgd_t
)));
1301 memset(swapper_low_pmd_dir
, 0, sizeof(swapper_low_pmd_dir
));
1303 /* Now can init the kernel/bad page tables. */
1304 pud_set(pud_offset(&swapper_pg_dir
[0], 0),
1305 swapper_low_pmd_dir
+ (shift
/ sizeof(pgd_t
)));
1307 inherit_prom_mappings();
1309 /* Ok, we can use our TLB miss and window trap handlers safely. */
1314 if (tlb_type
== hypervisor
)
1315 sun4v_ktsb_register();
1317 /* Setup bootmem... */
1319 last_valid_pfn
= end_pfn
= bootmem_init(&pages_avail
, phys_base
);
1321 max_mapnr
= last_valid_pfn
;
1323 kernel_physical_mapping_init();
1326 unsigned long zones_size
[MAX_NR_ZONES
];
1327 unsigned long zholes_size
[MAX_NR_ZONES
];
1330 for (znum
= 0; znum
< MAX_NR_ZONES
; znum
++)
1331 zones_size
[znum
] = zholes_size
[znum
] = 0;
1333 zones_size
[ZONE_DMA
] = end_pfn
;
1334 zholes_size
[ZONE_DMA
] = end_pfn
- pages_avail
;
1336 free_area_init_node(0, &contig_page_data
, zones_size
,
1337 __pa(PAGE_OFFSET
) >> PAGE_SHIFT
,
1344 static void __init
taint_real_pages(void)
1348 read_obp_memory("available", &pavail_rescan
[0], &pavail_rescan_ents
);
1350 /* Find changes discovered in the physmem available rescan and
1351 * reserve the lost portions in the bootmem maps.
1353 for (i
= 0; i
< pavail_ents
; i
++) {
1354 unsigned long old_start
, old_end
;
1356 old_start
= pavail
[i
].phys_addr
;
1357 old_end
= old_start
+
1359 while (old_start
< old_end
) {
1362 for (n
= 0; pavail_rescan_ents
; n
++) {
1363 unsigned long new_start
, new_end
;
1365 new_start
= pavail_rescan
[n
].phys_addr
;
1366 new_end
= new_start
+
1367 pavail_rescan
[n
].reg_size
;
1369 if (new_start
<= old_start
&&
1370 new_end
>= (old_start
+ PAGE_SIZE
)) {
1371 set_bit(old_start
>> 22,
1372 sparc64_valid_addr_bitmap
);
1376 reserve_bootmem(old_start
, PAGE_SIZE
);
1379 old_start
+= PAGE_SIZE
;
1384 void __init
mem_init(void)
1386 unsigned long codepages
, datapages
, initpages
;
1387 unsigned long addr
, last
;
1390 i
= last_valid_pfn
>> ((22 - PAGE_SHIFT
) + 6);
1392 sparc64_valid_addr_bitmap
= (unsigned long *) alloc_bootmem(i
<< 3);
1393 if (sparc64_valid_addr_bitmap
== NULL
) {
1394 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1397 memset(sparc64_valid_addr_bitmap
, 0, i
<< 3);
1399 addr
= PAGE_OFFSET
+ kern_base
;
1400 last
= PAGE_ALIGN(kern_size
) + addr
;
1401 while (addr
< last
) {
1402 set_bit(__pa(addr
) >> 22, sparc64_valid_addr_bitmap
);
1408 high_memory
= __va(last_valid_pfn
<< PAGE_SHIFT
);
1410 #ifdef CONFIG_DEBUG_BOOTMEM
1411 prom_printf("mem_init: Calling free_all_bootmem().\n");
1413 totalram_pages
= num_physpages
= free_all_bootmem() - 1;
1416 * Set up the zero page, mark it reserved, so that page count
1417 * is not manipulated when freeing the page from user ptes.
1419 mem_map_zero
= alloc_pages(GFP_KERNEL
|__GFP_ZERO
, 0);
1420 if (mem_map_zero
== NULL
) {
1421 prom_printf("paging_init: Cannot alloc zero page.\n");
1424 SetPageReserved(mem_map_zero
);
1426 codepages
= (((unsigned long) _etext
) - ((unsigned long) _start
));
1427 codepages
= PAGE_ALIGN(codepages
) >> PAGE_SHIFT
;
1428 datapages
= (((unsigned long) _edata
) - ((unsigned long) _etext
));
1429 datapages
= PAGE_ALIGN(datapages
) >> PAGE_SHIFT
;
1430 initpages
= (((unsigned long) __init_end
) - ((unsigned long) __init_begin
));
1431 initpages
= PAGE_ALIGN(initpages
) >> PAGE_SHIFT
;
1433 printk("Memory: %uk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1434 nr_free_pages() << (PAGE_SHIFT
-10),
1435 codepages
<< (PAGE_SHIFT
-10),
1436 datapages
<< (PAGE_SHIFT
-10),
1437 initpages
<< (PAGE_SHIFT
-10),
1438 PAGE_OFFSET
, (last_valid_pfn
<< PAGE_SHIFT
));
1440 if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
)
1441 cheetah_ecache_flush_init();
1444 void free_initmem(void)
1446 unsigned long addr
, initend
;
1449 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1451 addr
= PAGE_ALIGN((unsigned long)(__init_begin
));
1452 initend
= (unsigned long)(__init_end
) & PAGE_MASK
;
1453 for (; addr
< initend
; addr
+= PAGE_SIZE
) {
1458 ((unsigned long) __va(kern_base
)) -
1459 ((unsigned long) KERNBASE
));
1460 memset((void *)addr
, 0xcc, PAGE_SIZE
);
1461 p
= virt_to_page(page
);
1463 ClearPageReserved(p
);
1464 set_page_count(p
, 1);
1471 #ifdef CONFIG_BLK_DEV_INITRD
1472 void free_initrd_mem(unsigned long start
, unsigned long end
)
1475 printk ("Freeing initrd memory: %ldk freed\n", (end
- start
) >> 10);
1476 for (; start
< end
; start
+= PAGE_SIZE
) {
1477 struct page
*p
= virt_to_page(start
);
1479 ClearPageReserved(p
);
1480 set_page_count(p
, 1);
1488 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
1489 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
1490 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
1491 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
1492 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
1493 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
1495 pgprot_t PAGE_KERNEL __read_mostly
;
1496 EXPORT_SYMBOL(PAGE_KERNEL
);
1498 pgprot_t PAGE_KERNEL_LOCKED __read_mostly
;
1499 pgprot_t PAGE_COPY __read_mostly
;
1501 pgprot_t PAGE_SHARED __read_mostly
;
1502 EXPORT_SYMBOL(PAGE_SHARED
);
1504 pgprot_t PAGE_EXEC __read_mostly
;
1505 unsigned long pg_iobits __read_mostly
;
1507 unsigned long _PAGE_IE __read_mostly
;
1509 unsigned long _PAGE_E __read_mostly
;
1510 EXPORT_SYMBOL(_PAGE_E
);
1512 unsigned long _PAGE_CACHE __read_mostly
;
1513 EXPORT_SYMBOL(_PAGE_CACHE
);
1515 static void prot_init_common(unsigned long page_none
,
1516 unsigned long page_shared
,
1517 unsigned long page_copy
,
1518 unsigned long page_readonly
,
1519 unsigned long page_exec_bit
)
1521 PAGE_COPY
= __pgprot(page_copy
);
1522 PAGE_SHARED
= __pgprot(page_shared
);
1524 protection_map
[0x0] = __pgprot(page_none
);
1525 protection_map
[0x1] = __pgprot(page_readonly
& ~page_exec_bit
);
1526 protection_map
[0x2] = __pgprot(page_copy
& ~page_exec_bit
);
1527 protection_map
[0x3] = __pgprot(page_copy
& ~page_exec_bit
);
1528 protection_map
[0x4] = __pgprot(page_readonly
);
1529 protection_map
[0x5] = __pgprot(page_readonly
);
1530 protection_map
[0x6] = __pgprot(page_copy
);
1531 protection_map
[0x7] = __pgprot(page_copy
);
1532 protection_map
[0x8] = __pgprot(page_none
);
1533 protection_map
[0x9] = __pgprot(page_readonly
& ~page_exec_bit
);
1534 protection_map
[0xa] = __pgprot(page_shared
& ~page_exec_bit
);
1535 protection_map
[0xb] = __pgprot(page_shared
& ~page_exec_bit
);
1536 protection_map
[0xc] = __pgprot(page_readonly
);
1537 protection_map
[0xd] = __pgprot(page_readonly
);
1538 protection_map
[0xe] = __pgprot(page_shared
);
1539 protection_map
[0xf] = __pgprot(page_shared
);
1542 static void __init
sun4u_pgprot_init(void)
1544 unsigned long page_none
, page_shared
, page_copy
, page_readonly
;
1545 unsigned long page_exec_bit
;
1547 PAGE_KERNEL
= __pgprot (_PAGE_PRESENT_4U
| _PAGE_VALID
|
1548 _PAGE_CACHE_4U
| _PAGE_P_4U
|
1549 __ACCESS_BITS_4U
| __DIRTY_BITS_4U
|
1551 PAGE_KERNEL_LOCKED
= __pgprot (_PAGE_PRESENT_4U
| _PAGE_VALID
|
1552 _PAGE_CACHE_4U
| _PAGE_P_4U
|
1553 __ACCESS_BITS_4U
| __DIRTY_BITS_4U
|
1554 _PAGE_EXEC_4U
| _PAGE_L_4U
);
1555 PAGE_EXEC
= __pgprot(_PAGE_EXEC_4U
);
1557 _PAGE_IE
= _PAGE_IE_4U
;
1558 _PAGE_E
= _PAGE_E_4U
;
1559 _PAGE_CACHE
= _PAGE_CACHE_4U
;
1561 pg_iobits
= (_PAGE_VALID
| _PAGE_PRESENT_4U
| __DIRTY_BITS_4U
|
1562 __ACCESS_BITS_4U
| _PAGE_E_4U
);
1564 kern_linear_pte_xor
[0] = (_PAGE_VALID
| _PAGE_SZ4MB_4U
) ^
1566 kern_linear_pte_xor
[0] |= (_PAGE_CP_4U
| _PAGE_CV_4U
|
1567 _PAGE_P_4U
| _PAGE_W_4U
);
1569 /* XXX Should use 256MB on Panther. XXX */
1570 kern_linear_pte_xor
[1] = kern_linear_pte_xor
[0];
1572 _PAGE_SZBITS
= _PAGE_SZBITS_4U
;
1573 _PAGE_ALL_SZ_BITS
= (_PAGE_SZ4MB_4U
| _PAGE_SZ512K_4U
|
1574 _PAGE_SZ64K_4U
| _PAGE_SZ8K_4U
|
1575 _PAGE_SZ32MB_4U
| _PAGE_SZ256MB_4U
);
1578 page_none
= _PAGE_PRESENT_4U
| _PAGE_ACCESSED_4U
| _PAGE_CACHE_4U
;
1579 page_shared
= (_PAGE_VALID
| _PAGE_PRESENT_4U
| _PAGE_CACHE_4U
|
1580 __ACCESS_BITS_4U
| _PAGE_WRITE_4U
| _PAGE_EXEC_4U
);
1581 page_copy
= (_PAGE_VALID
| _PAGE_PRESENT_4U
| _PAGE_CACHE_4U
|
1582 __ACCESS_BITS_4U
| _PAGE_EXEC_4U
);
1583 page_readonly
= (_PAGE_VALID
| _PAGE_PRESENT_4U
| _PAGE_CACHE_4U
|
1584 __ACCESS_BITS_4U
| _PAGE_EXEC_4U
);
1586 page_exec_bit
= _PAGE_EXEC_4U
;
1588 prot_init_common(page_none
, page_shared
, page_copy
, page_readonly
,
1592 static void __init
sun4v_pgprot_init(void)
1594 unsigned long page_none
, page_shared
, page_copy
, page_readonly
;
1595 unsigned long page_exec_bit
;
1597 PAGE_KERNEL
= __pgprot (_PAGE_PRESENT_4V
| _PAGE_VALID
|
1598 _PAGE_CACHE_4V
| _PAGE_P_4V
|
1599 __ACCESS_BITS_4V
| __DIRTY_BITS_4V
|
1601 PAGE_KERNEL_LOCKED
= PAGE_KERNEL
;
1602 PAGE_EXEC
= __pgprot(_PAGE_EXEC_4V
);
1604 _PAGE_IE
= _PAGE_IE_4V
;
1605 _PAGE_E
= _PAGE_E_4V
;
1606 _PAGE_CACHE
= _PAGE_CACHE_4V
;
1608 kern_linear_pte_xor
[0] = (_PAGE_VALID
| _PAGE_SZ4MB_4V
) ^
1610 kern_linear_pte_xor
[0] |= (_PAGE_CP_4V
| _PAGE_CV_4V
|
1611 _PAGE_P_4V
| _PAGE_W_4V
);
1613 kern_linear_pte_xor
[1] = (_PAGE_VALID
| _PAGE_SZ256MB_4V
) ^
1615 kern_linear_pte_xor
[1] |= (_PAGE_CP_4V
| _PAGE_CV_4V
|
1616 _PAGE_P_4V
| _PAGE_W_4V
);
1618 pg_iobits
= (_PAGE_VALID
| _PAGE_PRESENT_4V
| __DIRTY_BITS_4V
|
1619 __ACCESS_BITS_4V
| _PAGE_E_4V
);
1621 _PAGE_SZBITS
= _PAGE_SZBITS_4V
;
1622 _PAGE_ALL_SZ_BITS
= (_PAGE_SZ16GB_4V
| _PAGE_SZ2GB_4V
|
1623 _PAGE_SZ256MB_4V
| _PAGE_SZ32MB_4V
|
1624 _PAGE_SZ4MB_4V
| _PAGE_SZ512K_4V
|
1625 _PAGE_SZ64K_4V
| _PAGE_SZ8K_4V
);
1627 page_none
= _PAGE_PRESENT_4V
| _PAGE_ACCESSED_4V
| _PAGE_CACHE_4V
;
1628 page_shared
= (_PAGE_VALID
| _PAGE_PRESENT_4V
| _PAGE_CACHE_4V
|
1629 __ACCESS_BITS_4V
| _PAGE_WRITE_4V
| _PAGE_EXEC_4V
);
1630 page_copy
= (_PAGE_VALID
| _PAGE_PRESENT_4V
| _PAGE_CACHE_4V
|
1631 __ACCESS_BITS_4V
| _PAGE_EXEC_4V
);
1632 page_readonly
= (_PAGE_VALID
| _PAGE_PRESENT_4V
| _PAGE_CACHE_4V
|
1633 __ACCESS_BITS_4V
| _PAGE_EXEC_4V
);
1635 page_exec_bit
= _PAGE_EXEC_4V
;
1637 prot_init_common(page_none
, page_shared
, page_copy
, page_readonly
,
1641 unsigned long pte_sz_bits(unsigned long sz
)
1643 if (tlb_type
== hypervisor
) {
1647 return _PAGE_SZ8K_4V
;
1649 return _PAGE_SZ64K_4V
;
1651 return _PAGE_SZ512K_4V
;
1652 case 4 * 1024 * 1024:
1653 return _PAGE_SZ4MB_4V
;
1659 return _PAGE_SZ8K_4U
;
1661 return _PAGE_SZ64K_4U
;
1663 return _PAGE_SZ512K_4U
;
1664 case 4 * 1024 * 1024:
1665 return _PAGE_SZ4MB_4U
;
1670 pte_t
mk_pte_io(unsigned long page
, pgprot_t prot
, int space
, unsigned long page_size
)
1674 pte_val(pte
) = page
| pgprot_val(pgprot_noncached(prot
));
1675 pte_val(pte
) |= (((unsigned long)space
) << 32);
1676 pte_val(pte
) |= pte_sz_bits(page_size
);
1681 static unsigned long kern_large_tte(unsigned long paddr
)
1685 val
= (_PAGE_VALID
| _PAGE_SZ4MB_4U
|
1686 _PAGE_CP_4U
| _PAGE_CV_4U
| _PAGE_P_4U
|
1687 _PAGE_EXEC_4U
| _PAGE_L_4U
| _PAGE_W_4U
);
1688 if (tlb_type
== hypervisor
)
1689 val
= (_PAGE_VALID
| _PAGE_SZ4MB_4V
|
1690 _PAGE_CP_4V
| _PAGE_CV_4V
| _PAGE_P_4V
|
1691 _PAGE_EXEC_4V
| _PAGE_W_4V
);
1697 * Translate PROM's mapping we capture at boot time into physical address.
1698 * The second parameter is only set from prom_callback() invocations.
1700 unsigned long prom_virt_to_phys(unsigned long promva
, int *error
)
1705 mask
= _PAGE_PADDR_4U
;
1706 if (tlb_type
== hypervisor
)
1707 mask
= _PAGE_PADDR_4V
;
1709 for (i
= 0; i
< prom_trans_ents
; i
++) {
1710 struct linux_prom_translation
*p
= &prom_trans
[i
];
1712 if (promva
>= p
->virt
&&
1713 promva
< (p
->virt
+ p
->size
)) {
1714 unsigned long base
= p
->data
& mask
;
1718 return base
+ (promva
& (8192 - 1));
1726 /* XXX We should kill off this ugly thing at so me point. XXX */
1727 unsigned long sun4u_get_pte(unsigned long addr
)
1733 unsigned long mask
= _PAGE_PADDR_4U
;
1735 if (tlb_type
== hypervisor
)
1736 mask
= _PAGE_PADDR_4V
;
1738 if (addr
>= PAGE_OFFSET
)
1741 if ((addr
>= LOW_OBP_ADDRESS
) && (addr
< HI_OBP_ADDRESS
))
1742 return prom_virt_to_phys(addr
, NULL
);
1744 pgdp
= pgd_offset_k(addr
);
1745 pudp
= pud_offset(pgdp
, addr
);
1746 pmdp
= pmd_offset(pudp
, addr
);
1747 ptep
= pte_offset_kernel(pmdp
, addr
);
1749 return pte_val(*ptep
) & mask
;
1752 /* If not locked, zap it. */
1753 void __flush_tlb_all(void)
1755 unsigned long pstate
;
1758 __asm__
__volatile__("flushw\n\t"
1759 "rdpr %%pstate, %0\n\t"
1760 "wrpr %0, %1, %%pstate"
1763 if (tlb_type
== spitfire
) {
1764 for (i
= 0; i
< 64; i
++) {
1765 /* Spitfire Errata #32 workaround */
1766 /* NOTE: Always runs on spitfire, so no
1767 * cheetah+ page size encodings.
1769 __asm__
__volatile__("stxa %0, [%1] %2\n\t"
1773 "r" (PRIMARY_CONTEXT
), "i" (ASI_DMMU
));
1775 if (!(spitfire_get_dtlb_data(i
) & _PAGE_L_4U
)) {
1776 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
1779 : "r" (TLB_TAG_ACCESS
), "i" (ASI_DMMU
));
1780 spitfire_put_dtlb_data(i
, 0x0UL
);
1783 /* Spitfire Errata #32 workaround */
1784 /* NOTE: Always runs on spitfire, so no
1785 * cheetah+ page size encodings.
1787 __asm__
__volatile__("stxa %0, [%1] %2\n\t"
1791 "r" (PRIMARY_CONTEXT
), "i" (ASI_DMMU
));
1793 if (!(spitfire_get_itlb_data(i
) & _PAGE_L_4U
)) {
1794 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
1797 : "r" (TLB_TAG_ACCESS
), "i" (ASI_IMMU
));
1798 spitfire_put_itlb_data(i
, 0x0UL
);
1801 } else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
1802 cheetah_flush_dtlb_all();
1803 cheetah_flush_itlb_all();
1805 __asm__
__volatile__("wrpr %0, 0, %%pstate"
1809 #ifdef CONFIG_MEMORY_HOTPLUG
1811 void online_page(struct page
*page
)
1813 ClearPageReserved(page
);
1814 set_page_count(page
, 0);
1815 free_cold_page(page
);
1820 int remove_memory(u64 start
, u64 size
)
1825 #endif /* CONFIG_MEMORY_HOTPLUG */