1 /* $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
2 * arch/sparc64/mm/init.c
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 #include <linux/module.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/string.h>
12 #include <linux/init.h>
13 #include <linux/bootmem.h>
15 #include <linux/hugetlb.h>
16 #include <linux/slab.h>
17 #include <linux/initrd.h>
18 #include <linux/swap.h>
19 #include <linux/pagemap.h>
20 #include <linux/poison.h>
22 #include <linux/seq_file.h>
23 #include <linux/kprobes.h>
24 #include <linux/cache.h>
25 #include <linux/sort.h>
26 #include <linux/percpu.h>
29 #include <asm/system.h>
31 #include <asm/pgalloc.h>
32 #include <asm/pgtable.h>
33 #include <asm/oplib.h>
34 #include <asm/iommu.h>
36 #include <asm/uaccess.h>
37 #include <asm/mmu_context.h>
38 #include <asm/tlbflush.h>
40 #include <asm/starfire.h>
42 #include <asm/spitfire.h>
43 #include <asm/sections.h>
45 #include <asm/hypervisor.h>
47 #include <asm/sstate.h>
48 #include <asm/mdesc.h>
50 #define MAX_PHYS_ADDRESS (1UL << 42UL)
51 #define KPTE_BITMAP_CHUNK_SZ (256UL * 1024UL * 1024UL)
52 #define KPTE_BITMAP_BYTES \
53 ((MAX_PHYS_ADDRESS / KPTE_BITMAP_CHUNK_SZ) / 8)
55 unsigned long kern_linear_pte_xor
[2] __read_mostly
;
57 /* A bitmap, one bit for every 256MB of physical memory. If the bit
58 * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
59 * if set we should use a 256MB page (via kern_linear_pte_xor[1]).
61 unsigned long kpte_linear_bitmap
[KPTE_BITMAP_BYTES
/ sizeof(unsigned long)];
63 #ifndef CONFIG_DEBUG_PAGEALLOC
64 /* A special kernel TSB for 4MB and 256MB linear mappings.
65 * Space is allocated for this right after the trap table
66 * in arch/sparc64/kernel/head.S
68 extern struct tsb swapper_4m_tsb
[KERNEL_TSB4M_NENTRIES
];
73 static struct linux_prom64_registers pavail
[MAX_BANKS
] __initdata
;
74 static struct linux_prom64_registers pavail_rescan
[MAX_BANKS
] __initdata
;
75 static int pavail_ents __initdata
;
76 static int pavail_rescan_ents __initdata
;
78 static int cmp_p64(const void *a
, const void *b
)
80 const struct linux_prom64_registers
*x
= a
, *y
= b
;
82 if (x
->phys_addr
> y
->phys_addr
)
84 if (x
->phys_addr
< y
->phys_addr
)
89 static void __init
read_obp_memory(const char *property
,
90 struct linux_prom64_registers
*regs
,
93 int node
= prom_finddevice("/memory");
94 int prop_size
= prom_getproplen(node
, property
);
97 ents
= prop_size
/ sizeof(struct linux_prom64_registers
);
98 if (ents
> MAX_BANKS
) {
99 prom_printf("The machine has more %s property entries than "
100 "this kernel can support (%d).\n",
101 property
, MAX_BANKS
);
105 ret
= prom_getproperty(node
, property
, (char *) regs
, prop_size
);
107 prom_printf("Couldn't get %s property from /memory.\n");
111 /* Sanitize what we got from the firmware, by page aligning
114 for (i
= 0; i
< ents
; i
++) {
115 unsigned long base
, size
;
117 base
= regs
[i
].phys_addr
;
118 size
= regs
[i
].reg_size
;
121 if (base
& ~PAGE_MASK
) {
122 unsigned long new_base
= PAGE_ALIGN(base
);
124 size
-= new_base
- base
;
125 if ((long) size
< 0L)
130 /* If it is empty, simply get rid of it.
131 * This simplifies the logic of the other
132 * functions that process these arrays.
134 memmove(®s
[i
], ®s
[i
+ 1],
135 (ents
- i
- 1) * sizeof(regs
[0]));
140 regs
[i
].phys_addr
= base
;
141 regs
[i
].reg_size
= size
;
146 sort(regs
, ents
, sizeof(struct linux_prom64_registers
),
150 unsigned long *sparc64_valid_addr_bitmap __read_mostly
;
152 /* Kernel physical address base and size in bytes. */
153 unsigned long kern_base __read_mostly
;
154 unsigned long kern_size __read_mostly
;
156 /* Initial ramdisk setup */
157 extern unsigned long sparc_ramdisk_image64
;
158 extern unsigned int sparc_ramdisk_image
;
159 extern unsigned int sparc_ramdisk_size
;
161 struct page
*mem_map_zero __read_mostly
;
163 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly
;
165 unsigned long sparc64_kern_pri_context __read_mostly
;
166 unsigned long sparc64_kern_pri_nuc_bits __read_mostly
;
167 unsigned long sparc64_kern_sec_context __read_mostly
;
169 int num_kernel_image_mappings
;
171 #ifdef CONFIG_DEBUG_DCFLUSH
172 atomic_t dcpage_flushes
= ATOMIC_INIT(0);
174 atomic_t dcpage_flushes_xcall
= ATOMIC_INIT(0);
178 inline void flush_dcache_page_impl(struct page
*page
)
180 BUG_ON(tlb_type
== hypervisor
);
181 #ifdef CONFIG_DEBUG_DCFLUSH
182 atomic_inc(&dcpage_flushes
);
185 #ifdef DCACHE_ALIASING_POSSIBLE
186 __flush_dcache_page(page_address(page
),
187 ((tlb_type
== spitfire
) &&
188 page_mapping(page
) != NULL
));
190 if (page_mapping(page
) != NULL
&&
191 tlb_type
== spitfire
)
192 __flush_icache_page(__pa(page_address(page
)));
196 #define PG_dcache_dirty PG_arch_1
197 #define PG_dcache_cpu_shift 32UL
198 #define PG_dcache_cpu_mask \
199 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
201 #define dcache_dirty_cpu(page) \
202 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
204 static inline void set_dcache_dirty(struct page
*page
, int this_cpu
)
206 unsigned long mask
= this_cpu
;
207 unsigned long non_cpu_bits
;
209 non_cpu_bits
= ~(PG_dcache_cpu_mask
<< PG_dcache_cpu_shift
);
210 mask
= (mask
<< PG_dcache_cpu_shift
) | (1UL << PG_dcache_dirty
);
212 __asm__
__volatile__("1:\n\t"
214 "and %%g7, %1, %%g1\n\t"
215 "or %%g1, %0, %%g1\n\t"
216 "casx [%2], %%g7, %%g1\n\t"
218 "membar #StoreLoad | #StoreStore\n\t"
219 "bne,pn %%xcc, 1b\n\t"
222 : "r" (mask
), "r" (non_cpu_bits
), "r" (&page
->flags
)
226 static inline void clear_dcache_dirty_cpu(struct page
*page
, unsigned long cpu
)
228 unsigned long mask
= (1UL << PG_dcache_dirty
);
230 __asm__
__volatile__("! test_and_clear_dcache_dirty\n"
233 "srlx %%g7, %4, %%g1\n\t"
234 "and %%g1, %3, %%g1\n\t"
236 "bne,pn %%icc, 2f\n\t"
237 " andn %%g7, %1, %%g1\n\t"
238 "casx [%2], %%g7, %%g1\n\t"
240 "membar #StoreLoad | #StoreStore\n\t"
241 "bne,pn %%xcc, 1b\n\t"
245 : "r" (cpu
), "r" (mask
), "r" (&page
->flags
),
246 "i" (PG_dcache_cpu_mask
),
247 "i" (PG_dcache_cpu_shift
)
251 static inline void tsb_insert(struct tsb
*ent
, unsigned long tag
, unsigned long pte
)
253 unsigned long tsb_addr
= (unsigned long) ent
;
255 if (tlb_type
== cheetah_plus
|| tlb_type
== hypervisor
)
256 tsb_addr
= __pa(tsb_addr
);
258 __tsb_insert(tsb_addr
, tag
, pte
);
261 unsigned long _PAGE_ALL_SZ_BITS __read_mostly
;
262 unsigned long _PAGE_SZBITS __read_mostly
;
264 void update_mmu_cache(struct vm_area_struct
*vma
, unsigned long address
, pte_t pte
)
266 struct mm_struct
*mm
;
268 unsigned long tag
, flags
;
269 unsigned long tsb_index
, tsb_hash_shift
;
271 if (tlb_type
!= hypervisor
) {
272 unsigned long pfn
= pte_pfn(pte
);
273 unsigned long pg_flags
;
276 if (pfn_valid(pfn
) &&
277 (page
= pfn_to_page(pfn
), page_mapping(page
)) &&
278 ((pg_flags
= page
->flags
) & (1UL << PG_dcache_dirty
))) {
279 int cpu
= ((pg_flags
>> PG_dcache_cpu_shift
) &
281 int this_cpu
= get_cpu();
283 /* This is just to optimize away some function calls
287 flush_dcache_page_impl(page
);
289 smp_flush_dcache_page_impl(page
, cpu
);
291 clear_dcache_dirty_cpu(page
, cpu
);
299 tsb_index
= MM_TSB_BASE
;
300 tsb_hash_shift
= PAGE_SHIFT
;
302 spin_lock_irqsave(&mm
->context
.lock
, flags
);
304 #ifdef CONFIG_HUGETLB_PAGE
305 if (mm
->context
.tsb_block
[MM_TSB_HUGE
].tsb
!= NULL
) {
306 if ((tlb_type
== hypervisor
&&
307 (pte_val(pte
) & _PAGE_SZALL_4V
) == _PAGE_SZHUGE_4V
) ||
308 (tlb_type
!= hypervisor
&&
309 (pte_val(pte
) & _PAGE_SZALL_4U
) == _PAGE_SZHUGE_4U
)) {
310 tsb_index
= MM_TSB_HUGE
;
311 tsb_hash_shift
= HPAGE_SHIFT
;
316 tsb
= mm
->context
.tsb_block
[tsb_index
].tsb
;
317 tsb
+= ((address
>> tsb_hash_shift
) &
318 (mm
->context
.tsb_block
[tsb_index
].tsb_nentries
- 1UL));
319 tag
= (address
>> 22UL);
320 tsb_insert(tsb
, tag
, pte_val(pte
));
322 spin_unlock_irqrestore(&mm
->context
.lock
, flags
);
325 void flush_dcache_page(struct page
*page
)
327 struct address_space
*mapping
;
330 if (tlb_type
== hypervisor
)
333 /* Do not bother with the expensive D-cache flush if it
334 * is merely the zero page. The 'bigcore' testcase in GDB
335 * causes this case to run millions of times.
337 if (page
== ZERO_PAGE(0))
340 this_cpu
= get_cpu();
342 mapping
= page_mapping(page
);
343 if (mapping
&& !mapping_mapped(mapping
)) {
344 int dirty
= test_bit(PG_dcache_dirty
, &page
->flags
);
346 int dirty_cpu
= dcache_dirty_cpu(page
);
348 if (dirty_cpu
== this_cpu
)
350 smp_flush_dcache_page_impl(page
, dirty_cpu
);
352 set_dcache_dirty(page
, this_cpu
);
354 /* We could delay the flush for the !page_mapping
355 * case too. But that case is for exec env/arg
356 * pages and those are %99 certainly going to get
357 * faulted into the tlb (and thus flushed) anyways.
359 flush_dcache_page_impl(page
);
366 void __kprobes
flush_icache_range(unsigned long start
, unsigned long end
)
368 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
369 if (tlb_type
== spitfire
) {
372 /* This code only runs on Spitfire cpus so this is
373 * why we can assume _PAGE_PADDR_4U.
375 for (kaddr
= start
; kaddr
< end
; kaddr
+= PAGE_SIZE
) {
376 unsigned long paddr
, mask
= _PAGE_PADDR_4U
;
378 if (kaddr
>= PAGE_OFFSET
)
379 paddr
= kaddr
& mask
;
381 pgd_t
*pgdp
= pgd_offset_k(kaddr
);
382 pud_t
*pudp
= pud_offset(pgdp
, kaddr
);
383 pmd_t
*pmdp
= pmd_offset(pudp
, kaddr
);
384 pte_t
*ptep
= pte_offset_kernel(pmdp
, kaddr
);
386 paddr
= pte_val(*ptep
) & mask
;
388 __flush_icache_page(paddr
);
395 unsigned long total
= 0, reserved
= 0;
396 unsigned long shared
= 0, cached
= 0;
399 printk(KERN_INFO
"Mem-info:\n");
401 printk(KERN_INFO
"Free swap: %6ldkB\n",
402 nr_swap_pages
<< (PAGE_SHIFT
-10));
403 for_each_online_pgdat(pgdat
) {
404 unsigned long i
, flags
;
406 pgdat_resize_lock(pgdat
, &flags
);
407 for (i
= 0; i
< pgdat
->node_spanned_pages
; i
++) {
408 struct page
*page
= pgdat_page_nr(pgdat
, i
);
410 if (PageReserved(page
))
412 else if (PageSwapCache(page
))
414 else if (page_count(page
))
415 shared
+= page_count(page
) - 1;
417 pgdat_resize_unlock(pgdat
, &flags
);
420 printk(KERN_INFO
"%lu pages of RAM\n", total
);
421 printk(KERN_INFO
"%lu reserved pages\n", reserved
);
422 printk(KERN_INFO
"%lu pages shared\n", shared
);
423 printk(KERN_INFO
"%lu pages swap cached\n", cached
);
425 printk(KERN_INFO
"%lu pages dirty\n",
426 global_page_state(NR_FILE_DIRTY
));
427 printk(KERN_INFO
"%lu pages writeback\n",
428 global_page_state(NR_WRITEBACK
));
429 printk(KERN_INFO
"%lu pages mapped\n",
430 global_page_state(NR_FILE_MAPPED
));
431 printk(KERN_INFO
"%lu pages slab\n",
432 global_page_state(NR_SLAB_RECLAIMABLE
) +
433 global_page_state(NR_SLAB_UNRECLAIMABLE
));
434 printk(KERN_INFO
"%lu pages pagetables\n",
435 global_page_state(NR_PAGETABLE
));
438 void mmu_info(struct seq_file
*m
)
440 if (tlb_type
== cheetah
)
441 seq_printf(m
, "MMU Type\t: Cheetah\n");
442 else if (tlb_type
== cheetah_plus
)
443 seq_printf(m
, "MMU Type\t: Cheetah+\n");
444 else if (tlb_type
== spitfire
)
445 seq_printf(m
, "MMU Type\t: Spitfire\n");
446 else if (tlb_type
== hypervisor
)
447 seq_printf(m
, "MMU Type\t: Hypervisor (sun4v)\n");
449 seq_printf(m
, "MMU Type\t: ???\n");
451 #ifdef CONFIG_DEBUG_DCFLUSH
452 seq_printf(m
, "DCPageFlushes\t: %d\n",
453 atomic_read(&dcpage_flushes
));
455 seq_printf(m
, "DCPageFlushesXC\t: %d\n",
456 atomic_read(&dcpage_flushes_xcall
));
457 #endif /* CONFIG_SMP */
458 #endif /* CONFIG_DEBUG_DCFLUSH */
461 struct linux_prom_translation
{
467 /* Exported for kernel TLB miss handling in ktlb.S */
468 struct linux_prom_translation prom_trans
[512] __read_mostly
;
469 unsigned int prom_trans_ents __read_mostly
;
471 /* Exported for SMP bootup purposes. */
472 unsigned long kern_locked_tte_data
;
474 /* The obp translations are saved based on 8k pagesize, since obp can
475 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
476 * HI_OBP_ADDRESS range are handled in ktlb.S.
478 static inline int in_obp_range(unsigned long vaddr
)
480 return (vaddr
>= LOW_OBP_ADDRESS
&&
481 vaddr
< HI_OBP_ADDRESS
);
484 static int cmp_ptrans(const void *a
, const void *b
)
486 const struct linux_prom_translation
*x
= a
, *y
= b
;
488 if (x
->virt
> y
->virt
)
490 if (x
->virt
< y
->virt
)
495 /* Read OBP translations property into 'prom_trans[]'. */
496 static void __init
read_obp_translations(void)
498 int n
, node
, ents
, first
, last
, i
;
500 node
= prom_finddevice("/virtual-memory");
501 n
= prom_getproplen(node
, "translations");
502 if (unlikely(n
== 0 || n
== -1)) {
503 prom_printf("prom_mappings: Couldn't get size.\n");
506 if (unlikely(n
> sizeof(prom_trans
))) {
507 prom_printf("prom_mappings: Size %Zd is too big.\n", n
);
511 if ((n
= prom_getproperty(node
, "translations",
512 (char *)&prom_trans
[0],
513 sizeof(prom_trans
))) == -1) {
514 prom_printf("prom_mappings: Couldn't get property.\n");
518 n
= n
/ sizeof(struct linux_prom_translation
);
522 sort(prom_trans
, ents
, sizeof(struct linux_prom_translation
),
525 /* Now kick out all the non-OBP entries. */
526 for (i
= 0; i
< ents
; i
++) {
527 if (in_obp_range(prom_trans
[i
].virt
))
531 for (; i
< ents
; i
++) {
532 if (!in_obp_range(prom_trans
[i
].virt
))
537 for (i
= 0; i
< (last
- first
); i
++) {
538 struct linux_prom_translation
*src
= &prom_trans
[i
+ first
];
539 struct linux_prom_translation
*dest
= &prom_trans
[i
];
543 for (; i
< ents
; i
++) {
544 struct linux_prom_translation
*dest
= &prom_trans
[i
];
545 dest
->virt
= dest
->size
= dest
->data
= 0x0UL
;
548 prom_trans_ents
= last
- first
;
550 if (tlb_type
== spitfire
) {
551 /* Clear diag TTE bits. */
552 for (i
= 0; i
< prom_trans_ents
; i
++)
553 prom_trans
[i
].data
&= ~0x0003fe0000000000UL
;
557 static void __init
hypervisor_tlb_lock(unsigned long vaddr
,
561 unsigned long ret
= sun4v_mmu_map_perm_addr(vaddr
, 0, pte
, mmu
);
564 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
565 "errors with %lx\n", vaddr
, 0, pte
, mmu
, ret
);
570 static unsigned long kern_large_tte(unsigned long paddr
);
572 static void __init
remap_kernel(void)
574 unsigned long phys_page
, tte_vaddr
, tte_data
;
575 int i
, tlb_ent
= sparc64_highest_locked_tlbent();
577 tte_vaddr
= (unsigned long) KERNBASE
;
578 phys_page
= (prom_boot_mapping_phys_low
>> 22UL) << 22UL;
579 tte_data
= kern_large_tte(phys_page
);
581 kern_locked_tte_data
= tte_data
;
583 /* Now lock us into the TLBs via Hypervisor or OBP. */
584 if (tlb_type
== hypervisor
) {
585 for (i
= 0; i
< num_kernel_image_mappings
; i
++) {
586 hypervisor_tlb_lock(tte_vaddr
, tte_data
, HV_MMU_DMMU
);
587 hypervisor_tlb_lock(tte_vaddr
, tte_data
, HV_MMU_IMMU
);
588 tte_vaddr
+= 0x400000;
589 tte_data
+= 0x400000;
592 for (i
= 0; i
< num_kernel_image_mappings
; i
++) {
593 prom_dtlb_load(tlb_ent
- i
, tte_data
, tte_vaddr
);
594 prom_itlb_load(tlb_ent
- i
, tte_data
, tte_vaddr
);
595 tte_vaddr
+= 0x400000;
596 tte_data
+= 0x400000;
598 sparc64_highest_unlocked_tlb_ent
= tlb_ent
- i
;
600 if (tlb_type
== cheetah_plus
) {
601 sparc64_kern_pri_context
= (CTX_CHEETAH_PLUS_CTX0
|
602 CTX_CHEETAH_PLUS_NUC
);
603 sparc64_kern_pri_nuc_bits
= CTX_CHEETAH_PLUS_NUC
;
604 sparc64_kern_sec_context
= CTX_CHEETAH_PLUS_CTX0
;
609 static void __init
inherit_prom_mappings(void)
611 read_obp_translations();
613 /* Now fixup OBP's idea about where we really are mapped. */
614 printk("Remapping the kernel... ");
619 void prom_world(int enter
)
622 set_fs((mm_segment_t
) { get_thread_current_ds() });
624 __asm__
__volatile__("flushw");
627 void __flush_dcache_range(unsigned long start
, unsigned long end
)
631 if (tlb_type
== spitfire
) {
634 for (va
= start
; va
< end
; va
+= 32) {
635 spitfire_put_dcache_tag(va
& 0x3fe0, 0x0);
639 } else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
642 for (va
= start
; va
< end
; va
+= 32)
643 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
647 "i" (ASI_DCACHE_INVALIDATE
));
651 /* get_new_mmu_context() uses "cache + 1". */
652 DEFINE_SPINLOCK(ctx_alloc_lock
);
653 unsigned long tlb_context_cache
= CTX_FIRST_VERSION
- 1;
654 #define MAX_CTX_NR (1UL << CTX_NR_BITS)
655 #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
656 DECLARE_BITMAP(mmu_context_bmap
, MAX_CTX_NR
);
658 /* Caller does TLB context flushing on local CPU if necessary.
659 * The caller also ensures that CTX_VALID(mm->context) is false.
661 * We must be careful about boundary cases so that we never
662 * let the user have CTX 0 (nucleus) or we ever use a CTX
663 * version of zero (and thus NO_CONTEXT would not be caught
664 * by version mis-match tests in mmu_context.h).
666 * Always invoked with interrupts disabled.
668 void get_new_mmu_context(struct mm_struct
*mm
)
670 unsigned long ctx
, new_ctx
;
671 unsigned long orig_pgsz_bits
;
675 spin_lock_irqsave(&ctx_alloc_lock
, flags
);
676 orig_pgsz_bits
= (mm
->context
.sparc64_ctx_val
& CTX_PGSZ_MASK
);
677 ctx
= (tlb_context_cache
+ 1) & CTX_NR_MASK
;
678 new_ctx
= find_next_zero_bit(mmu_context_bmap
, 1 << CTX_NR_BITS
, ctx
);
680 if (new_ctx
>= (1 << CTX_NR_BITS
)) {
681 new_ctx
= find_next_zero_bit(mmu_context_bmap
, ctx
, 1);
682 if (new_ctx
>= ctx
) {
684 new_ctx
= (tlb_context_cache
& CTX_VERSION_MASK
) +
687 new_ctx
= CTX_FIRST_VERSION
;
689 /* Don't call memset, for 16 entries that's just
692 mmu_context_bmap
[0] = 3;
693 mmu_context_bmap
[1] = 0;
694 mmu_context_bmap
[2] = 0;
695 mmu_context_bmap
[3] = 0;
696 for (i
= 4; i
< CTX_BMAP_SLOTS
; i
+= 4) {
697 mmu_context_bmap
[i
+ 0] = 0;
698 mmu_context_bmap
[i
+ 1] = 0;
699 mmu_context_bmap
[i
+ 2] = 0;
700 mmu_context_bmap
[i
+ 3] = 0;
706 mmu_context_bmap
[new_ctx
>>6] |= (1UL << (new_ctx
& 63));
707 new_ctx
|= (tlb_context_cache
& CTX_VERSION_MASK
);
709 tlb_context_cache
= new_ctx
;
710 mm
->context
.sparc64_ctx_val
= new_ctx
| orig_pgsz_bits
;
711 spin_unlock_irqrestore(&ctx_alloc_lock
, flags
);
713 if (unlikely(new_version
))
714 smp_new_mmu_context_version();
717 /* Find a free area for the bootmem map, avoiding the kernel image
718 * and the initial ramdisk.
720 static unsigned long __init
choose_bootmap_pfn(unsigned long start_pfn
,
721 unsigned long end_pfn
)
723 unsigned long avoid_start
, avoid_end
, bootmap_size
;
726 bootmap_size
= bootmem_bootmap_pages(end_pfn
- start_pfn
);
727 bootmap_size
<<= PAGE_SHIFT
;
729 avoid_start
= avoid_end
= 0;
730 #ifdef CONFIG_BLK_DEV_INITRD
731 avoid_start
= initrd_start
;
732 avoid_end
= PAGE_ALIGN(initrd_end
);
735 for (i
= 0; i
< pavail_ents
; i
++) {
736 unsigned long start
, end
;
738 start
= pavail
[i
].phys_addr
;
739 end
= start
+ pavail
[i
].reg_size
;
741 while (start
< end
) {
742 if (start
>= kern_base
&&
743 start
< PAGE_ALIGN(kern_base
+ kern_size
)) {
744 start
= PAGE_ALIGN(kern_base
+ kern_size
);
747 if (start
>= avoid_start
&& start
< avoid_end
) {
752 if ((end
- start
) < bootmap_size
)
755 if (start
< kern_base
&&
756 (start
+ bootmap_size
) > kern_base
) {
757 start
= PAGE_ALIGN(kern_base
+ kern_size
);
761 if (start
< avoid_start
&&
762 (start
+ bootmap_size
) > avoid_start
) {
767 /* OK, it doesn't overlap anything, use it. */
768 return start
>> PAGE_SHIFT
;
772 prom_printf("Cannot find free area for bootmap, aborting.\n");
776 static void __init
trim_pavail(unsigned long *cur_size_p
,
777 unsigned long *end_of_phys_p
)
779 unsigned long to_trim
= *cur_size_p
- cmdline_memory_size
;
780 unsigned long avoid_start
, avoid_end
;
783 to_trim
= PAGE_ALIGN(to_trim
);
785 avoid_start
= avoid_end
= 0;
786 #ifdef CONFIG_BLK_DEV_INITRD
787 avoid_start
= initrd_start
;
788 avoid_end
= PAGE_ALIGN(initrd_end
);
791 /* Trim some pavail[] entries in order to satisfy the
792 * requested "mem=xxx" kernel command line specification.
794 * We must not trim off the kernel image area nor the
795 * initial ramdisk range (if any). Also, we must not trim
796 * any pavail[] entry down to zero in order to preserve
797 * the invariant that all pavail[] entries have a non-zero
798 * size which is assumed by all of the code in here.
800 for (i
= 0; i
< pavail_ents
; i
++) {
801 unsigned long start
, end
, kern_end
;
802 unsigned long trim_low
, trim_high
, n
;
804 kern_end
= PAGE_ALIGN(kern_base
+ kern_size
);
806 trim_low
= start
= pavail
[i
].phys_addr
;
807 trim_high
= end
= start
+ pavail
[i
].reg_size
;
809 if (kern_base
>= start
&&
811 trim_low
= kern_base
;
815 if (kern_end
>= start
&&
817 trim_high
= kern_end
;
820 avoid_start
>= start
&&
822 if (trim_low
> avoid_start
)
823 trim_low
= avoid_start
;
824 if (avoid_end
>= end
)
828 avoid_end
>= start
&&
830 if (trim_high
< avoid_end
)
831 trim_high
= avoid_end
;
834 if (trim_high
<= trim_low
)
837 if (trim_low
== start
&& trim_high
== end
) {
838 /* Whole chunk is available for trimming.
839 * Trim all except one page, in order to keep
842 n
= (end
- start
) - PAGE_SIZE
;
847 pavail
[i
].phys_addr
+= n
;
848 pavail
[i
].reg_size
-= n
;
852 n
= (trim_low
- start
);
857 pavail
[i
].phys_addr
+= n
;
858 pavail
[i
].reg_size
-= n
;
866 pavail
[i
].reg_size
-= n
;
878 for (i
= 0; i
< pavail_ents
; i
++) {
879 *end_of_phys_p
= pavail
[i
].phys_addr
+
881 *cur_size_p
+= pavail
[i
].reg_size
;
885 /* About pages_avail, this is the value we will use to calculate
886 * the zholes_size[] argument given to free_area_init_node(). The
887 * page allocator uses this to calculate nr_kernel_pages,
888 * nr_all_pages and zone->present_pages. On NUMA it is used
889 * to calculate zone->min_unmapped_pages and zone->min_slab_pages.
891 * So this number should really be set to what the page allocator
892 * actually ends up with. This means:
893 * 1) It should include bootmem map pages, we'll release those.
894 * 2) It should not include the kernel image, except for the
895 * __init sections which we will also release.
896 * 3) It should include the initrd image, since we'll release
899 static unsigned long __init
bootmem_init(unsigned long *pages_avail
,
900 unsigned long phys_base
)
902 unsigned long bootmap_size
, end_pfn
;
903 unsigned long end_of_phys_memory
= 0UL;
904 unsigned long bootmap_pfn
, bytes_avail
, size
;
908 for (i
= 0; i
< pavail_ents
; i
++) {
909 end_of_phys_memory
= pavail
[i
].phys_addr
+
911 bytes_avail
+= pavail
[i
].reg_size
;
914 /* Determine the location of the initial ramdisk before trying
915 * to honor the "mem=xxx" command line argument. We must know
916 * where the kernel image and the ramdisk image are so that we
917 * do not trim those two areas from the physical memory map.
920 #ifdef CONFIG_BLK_DEV_INITRD
921 /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
922 if (sparc_ramdisk_image
|| sparc_ramdisk_image64
) {
923 unsigned long ramdisk_image
= sparc_ramdisk_image
?
924 sparc_ramdisk_image
: sparc_ramdisk_image64
;
925 ramdisk_image
-= KERNBASE
;
926 initrd_start
= ramdisk_image
+ phys_base
;
927 initrd_end
= initrd_start
+ sparc_ramdisk_size
;
928 if (initrd_end
> end_of_phys_memory
) {
929 printk(KERN_CRIT
"initrd extends beyond end of memory "
930 "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
931 initrd_end
, end_of_phys_memory
);
938 if (cmdline_memory_size
&&
939 bytes_avail
> cmdline_memory_size
)
940 trim_pavail(&bytes_avail
,
941 &end_of_phys_memory
);
943 *pages_avail
= bytes_avail
>> PAGE_SHIFT
;
945 end_pfn
= end_of_phys_memory
>> PAGE_SHIFT
;
947 /* Initialize the boot-time allocator. */
948 max_pfn
= max_low_pfn
= end_pfn
;
949 min_low_pfn
= (phys_base
>> PAGE_SHIFT
);
951 bootmap_pfn
= choose_bootmap_pfn(min_low_pfn
, end_pfn
);
953 bootmap_size
= init_bootmem_node(NODE_DATA(0), bootmap_pfn
,
954 min_low_pfn
, end_pfn
);
956 /* Now register the available physical memory with the
959 for (i
= 0; i
< pavail_ents
; i
++)
960 free_bootmem(pavail
[i
].phys_addr
, pavail
[i
].reg_size
);
962 #ifdef CONFIG_BLK_DEV_INITRD
964 size
= initrd_end
- initrd_start
;
966 /* Reserve the initrd image area. */
967 reserve_bootmem(initrd_start
, size
, BOOTMEM_DEFAULT
);
969 initrd_start
+= PAGE_OFFSET
;
970 initrd_end
+= PAGE_OFFSET
;
973 /* Reserve the kernel text/data/bss. */
974 reserve_bootmem(kern_base
, kern_size
, BOOTMEM_DEFAULT
);
975 *pages_avail
-= PAGE_ALIGN(kern_size
) >> PAGE_SHIFT
;
977 /* Add back in the initmem pages. */
978 size
= ((unsigned long)(__init_end
) & PAGE_MASK
) -
979 PAGE_ALIGN((unsigned long)__init_begin
);
980 *pages_avail
+= size
>> PAGE_SHIFT
;
982 /* Reserve the bootmem map. We do not account for it
983 * in pages_avail because we will release that memory
984 * in free_all_bootmem.
987 reserve_bootmem((bootmap_pfn
<< PAGE_SHIFT
), size
, BOOTMEM_DEFAULT
);
989 for (i
= 0; i
< pavail_ents
; i
++) {
990 unsigned long start_pfn
, end_pfn
;
992 start_pfn
= pavail
[i
].phys_addr
>> PAGE_SHIFT
;
993 end_pfn
= (start_pfn
+ (pavail
[i
].reg_size
>> PAGE_SHIFT
));
994 memory_present(0, start_pfn
, end_pfn
);
1002 static struct linux_prom64_registers pall
[MAX_BANKS
] __initdata
;
1003 static int pall_ents __initdata
;
1005 #ifdef CONFIG_DEBUG_PAGEALLOC
1006 static unsigned long __ref
kernel_map_range(unsigned long pstart
,
1007 unsigned long pend
, pgprot_t prot
)
1009 unsigned long vstart
= PAGE_OFFSET
+ pstart
;
1010 unsigned long vend
= PAGE_OFFSET
+ pend
;
1011 unsigned long alloc_bytes
= 0UL;
1013 if ((vstart
& ~PAGE_MASK
) || (vend
& ~PAGE_MASK
)) {
1014 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1019 while (vstart
< vend
) {
1020 unsigned long this_end
, paddr
= __pa(vstart
);
1021 pgd_t
*pgd
= pgd_offset_k(vstart
);
1026 pud
= pud_offset(pgd
, vstart
);
1027 if (pud_none(*pud
)) {
1030 new = __alloc_bootmem(PAGE_SIZE
, PAGE_SIZE
, PAGE_SIZE
);
1031 alloc_bytes
+= PAGE_SIZE
;
1032 pud_populate(&init_mm
, pud
, new);
1035 pmd
= pmd_offset(pud
, vstart
);
1036 if (!pmd_present(*pmd
)) {
1039 new = __alloc_bootmem(PAGE_SIZE
, PAGE_SIZE
, PAGE_SIZE
);
1040 alloc_bytes
+= PAGE_SIZE
;
1041 pmd_populate_kernel(&init_mm
, pmd
, new);
1044 pte
= pte_offset_kernel(pmd
, vstart
);
1045 this_end
= (vstart
+ PMD_SIZE
) & PMD_MASK
;
1046 if (this_end
> vend
)
1049 while (vstart
< this_end
) {
1050 pte_val(*pte
) = (paddr
| pgprot_val(prot
));
1052 vstart
+= PAGE_SIZE
;
1061 extern unsigned int kvmap_linear_patch
[1];
1062 #endif /* CONFIG_DEBUG_PAGEALLOC */
1064 static void __init
mark_kpte_bitmap(unsigned long start
, unsigned long end
)
1066 const unsigned long shift_256MB
= 28;
1067 const unsigned long mask_256MB
= ((1UL << shift_256MB
) - 1UL);
1068 const unsigned long size_256MB
= (1UL << shift_256MB
);
1070 while (start
< end
) {
1073 remains
= end
- start
;
1074 if (remains
< size_256MB
)
1077 if (start
& mask_256MB
) {
1078 start
= (start
+ size_256MB
) & ~mask_256MB
;
1082 while (remains
>= size_256MB
) {
1083 unsigned long index
= start
>> shift_256MB
;
1085 __set_bit(index
, kpte_linear_bitmap
);
1087 start
+= size_256MB
;
1088 remains
-= size_256MB
;
1093 static void __init
init_kpte_bitmap(void)
1097 for (i
= 0; i
< pall_ents
; i
++) {
1098 unsigned long phys_start
, phys_end
;
1100 phys_start
= pall
[i
].phys_addr
;
1101 phys_end
= phys_start
+ pall
[i
].reg_size
;
1103 mark_kpte_bitmap(phys_start
, phys_end
);
1107 static void __init
kernel_physical_mapping_init(void)
1109 #ifdef CONFIG_DEBUG_PAGEALLOC
1110 unsigned long i
, mem_alloced
= 0UL;
1112 for (i
= 0; i
< pall_ents
; i
++) {
1113 unsigned long phys_start
, phys_end
;
1115 phys_start
= pall
[i
].phys_addr
;
1116 phys_end
= phys_start
+ pall
[i
].reg_size
;
1118 mem_alloced
+= kernel_map_range(phys_start
, phys_end
,
1122 printk("Allocated %ld bytes for kernel page tables.\n",
1125 kvmap_linear_patch
[0] = 0x01000000; /* nop */
1126 flushi(&kvmap_linear_patch
[0]);
1132 #ifdef CONFIG_DEBUG_PAGEALLOC
1133 void kernel_map_pages(struct page
*page
, int numpages
, int enable
)
1135 unsigned long phys_start
= page_to_pfn(page
) << PAGE_SHIFT
;
1136 unsigned long phys_end
= phys_start
+ (numpages
* PAGE_SIZE
);
1138 kernel_map_range(phys_start
, phys_end
,
1139 (enable
? PAGE_KERNEL
: __pgprot(0)));
1141 flush_tsb_kernel_range(PAGE_OFFSET
+ phys_start
,
1142 PAGE_OFFSET
+ phys_end
);
1144 /* we should perform an IPI and flush all tlbs,
1145 * but that can deadlock->flush only current cpu.
1147 __flush_tlb_kernel_range(PAGE_OFFSET
+ phys_start
,
1148 PAGE_OFFSET
+ phys_end
);
1152 unsigned long __init
find_ecache_flush_span(unsigned long size
)
1156 for (i
= 0; i
< pavail_ents
; i
++) {
1157 if (pavail
[i
].reg_size
>= size
)
1158 return pavail
[i
].phys_addr
;
1164 static void __init
tsb_phys_patch(void)
1166 struct tsb_ldquad_phys_patch_entry
*pquad
;
1167 struct tsb_phys_patch_entry
*p
;
1169 pquad
= &__tsb_ldquad_phys_patch
;
1170 while (pquad
< &__tsb_ldquad_phys_patch_end
) {
1171 unsigned long addr
= pquad
->addr
;
1173 if (tlb_type
== hypervisor
)
1174 *(unsigned int *) addr
= pquad
->sun4v_insn
;
1176 *(unsigned int *) addr
= pquad
->sun4u_insn
;
1178 __asm__
__volatile__("flush %0"
1185 p
= &__tsb_phys_patch
;
1186 while (p
< &__tsb_phys_patch_end
) {
1187 unsigned long addr
= p
->addr
;
1189 *(unsigned int *) addr
= p
->insn
;
1191 __asm__
__volatile__("flush %0"
1199 /* Don't mark as init, we give this to the Hypervisor. */
1200 #ifndef CONFIG_DEBUG_PAGEALLOC
1201 #define NUM_KTSB_DESCR 2
1203 #define NUM_KTSB_DESCR 1
1205 static struct hv_tsb_descr ktsb_descr
[NUM_KTSB_DESCR
];
1206 extern struct tsb swapper_tsb
[KERNEL_TSB_NENTRIES
];
1208 static void __init
sun4v_ktsb_init(void)
1210 unsigned long ktsb_pa
;
1212 /* First KTSB for PAGE_SIZE mappings. */
1213 ktsb_pa
= kern_base
+ ((unsigned long)&swapper_tsb
[0] - KERNBASE
);
1215 switch (PAGE_SIZE
) {
1218 ktsb_descr
[0].pgsz_idx
= HV_PGSZ_IDX_8K
;
1219 ktsb_descr
[0].pgsz_mask
= HV_PGSZ_MASK_8K
;
1223 ktsb_descr
[0].pgsz_idx
= HV_PGSZ_IDX_64K
;
1224 ktsb_descr
[0].pgsz_mask
= HV_PGSZ_MASK_64K
;
1228 ktsb_descr
[0].pgsz_idx
= HV_PGSZ_IDX_512K
;
1229 ktsb_descr
[0].pgsz_mask
= HV_PGSZ_MASK_512K
;
1232 case 4 * 1024 * 1024:
1233 ktsb_descr
[0].pgsz_idx
= HV_PGSZ_IDX_4MB
;
1234 ktsb_descr
[0].pgsz_mask
= HV_PGSZ_MASK_4MB
;
1238 ktsb_descr
[0].assoc
= 1;
1239 ktsb_descr
[0].num_ttes
= KERNEL_TSB_NENTRIES
;
1240 ktsb_descr
[0].ctx_idx
= 0;
1241 ktsb_descr
[0].tsb_base
= ktsb_pa
;
1242 ktsb_descr
[0].resv
= 0;
1244 #ifndef CONFIG_DEBUG_PAGEALLOC
1245 /* Second KTSB for 4MB/256MB mappings. */
1246 ktsb_pa
= (kern_base
+
1247 ((unsigned long)&swapper_4m_tsb
[0] - KERNBASE
));
1249 ktsb_descr
[1].pgsz_idx
= HV_PGSZ_IDX_4MB
;
1250 ktsb_descr
[1].pgsz_mask
= (HV_PGSZ_MASK_4MB
|
1251 HV_PGSZ_MASK_256MB
);
1252 ktsb_descr
[1].assoc
= 1;
1253 ktsb_descr
[1].num_ttes
= KERNEL_TSB4M_NENTRIES
;
1254 ktsb_descr
[1].ctx_idx
= 0;
1255 ktsb_descr
[1].tsb_base
= ktsb_pa
;
1256 ktsb_descr
[1].resv
= 0;
1260 void __cpuinit
sun4v_ktsb_register(void)
1262 unsigned long pa
, ret
;
1264 pa
= kern_base
+ ((unsigned long)&ktsb_descr
[0] - KERNBASE
);
1266 ret
= sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR
, pa
);
1268 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1269 "errors with %lx\n", pa
, ret
);
1274 /* paging_init() sets up the page tables */
1276 extern void cheetah_ecache_flush_init(void);
1277 extern void sun4v_patch_tlb_handlers(void);
1279 extern void cpu_probe(void);
1280 extern void central_probe(void);
1282 static unsigned long last_valid_pfn
;
1283 pgd_t swapper_pg_dir
[2048];
1285 static void sun4u_pgprot_init(void);
1286 static void sun4v_pgprot_init(void);
1288 /* Dummy function */
1289 void __init
setup_per_cpu_areas(void)
1293 void __init
paging_init(void)
1295 unsigned long end_pfn
, pages_avail
, shift
, phys_base
;
1296 unsigned long real_end
, i
;
1298 /* These build time checkes make sure that the dcache_dirty_cpu()
1299 * page->flags usage will work.
1301 * When a page gets marked as dcache-dirty, we store the
1302 * cpu number starting at bit 32 in the page->flags. Also,
1303 * functions like clear_dcache_dirty_cpu use the cpu mask
1304 * in 13-bit signed-immediate instruction fields.
1306 BUILD_BUG_ON(FLAGS_RESERVED
!= 32);
1307 BUILD_BUG_ON(SECTIONS_WIDTH
+ NODES_WIDTH
+ ZONES_WIDTH
+
1308 ilog2(roundup_pow_of_two(NR_CPUS
)) > FLAGS_RESERVED
);
1309 BUILD_BUG_ON(NR_CPUS
> 4096);
1311 kern_base
= (prom_boot_mapping_phys_low
>> 22UL) << 22UL;
1312 kern_size
= (unsigned long)&_end
- (unsigned long)KERNBASE
;
1316 /* Invalidate both kernel TSBs. */
1317 memset(swapper_tsb
, 0x40, sizeof(swapper_tsb
));
1318 #ifndef CONFIG_DEBUG_PAGEALLOC
1319 memset(swapper_4m_tsb
, 0x40, sizeof(swapper_4m_tsb
));
1322 if (tlb_type
== hypervisor
)
1323 sun4v_pgprot_init();
1325 sun4u_pgprot_init();
1327 if (tlb_type
== cheetah_plus
||
1328 tlb_type
== hypervisor
)
1331 if (tlb_type
== hypervisor
) {
1332 sun4v_patch_tlb_handlers();
1336 /* Find available physical memory... */
1337 read_obp_memory("available", &pavail
[0], &pavail_ents
);
1339 phys_base
= 0xffffffffffffffffUL
;
1340 for (i
= 0; i
< pavail_ents
; i
++)
1341 phys_base
= min(phys_base
, pavail
[i
].phys_addr
);
1343 set_bit(0, mmu_context_bmap
);
1345 shift
= kern_base
+ PAGE_OFFSET
- ((unsigned long)KERNBASE
);
1347 real_end
= (unsigned long)_end
;
1348 num_kernel_image_mappings
= DIV_ROUND_UP(real_end
- KERNBASE
, 1 << 22);
1349 printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
1350 num_kernel_image_mappings
);
1352 /* Set kernel pgd to upper alias so physical page computations
1355 init_mm
.pgd
+= ((shift
) / (sizeof(pgd_t
)));
1357 memset(swapper_low_pmd_dir
, 0, sizeof(swapper_low_pmd_dir
));
1359 /* Now can init the kernel/bad page tables. */
1360 pud_set(pud_offset(&swapper_pg_dir
[0], 0),
1361 swapper_low_pmd_dir
+ (shift
/ sizeof(pgd_t
)));
1363 inherit_prom_mappings();
1365 read_obp_memory("reg", &pall
[0], &pall_ents
);
1369 /* Ok, we can use our TLB miss and window trap handlers safely. */
1374 if (tlb_type
== hypervisor
)
1375 sun4v_ktsb_register();
1377 /* Setup bootmem... */
1379 last_valid_pfn
= end_pfn
= bootmem_init(&pages_avail
, phys_base
);
1381 max_mapnr
= last_valid_pfn
;
1383 kernel_physical_mapping_init();
1385 real_setup_per_cpu_areas();
1387 prom_build_devicetree();
1389 if (tlb_type
== hypervisor
)
1393 unsigned long zones_size
[MAX_NR_ZONES
];
1394 unsigned long zholes_size
[MAX_NR_ZONES
];
1397 for (znum
= 0; znum
< MAX_NR_ZONES
; znum
++)
1398 zones_size
[znum
] = zholes_size
[znum
] = 0;
1400 zones_size
[ZONE_NORMAL
] = end_pfn
;
1401 zholes_size
[ZONE_NORMAL
] = end_pfn
- pages_avail
;
1403 free_area_init_node(0, &contig_page_data
, zones_size
,
1404 __pa(PAGE_OFFSET
) >> PAGE_SHIFT
,
1408 printk("Booting Linux...\n");
1414 static void __init
taint_real_pages(void)
1418 read_obp_memory("available", &pavail_rescan
[0], &pavail_rescan_ents
);
1420 /* Find changes discovered in the physmem available rescan and
1421 * reserve the lost portions in the bootmem maps.
1423 for (i
= 0; i
< pavail_ents
; i
++) {
1424 unsigned long old_start
, old_end
;
1426 old_start
= pavail
[i
].phys_addr
;
1427 old_end
= old_start
+
1429 while (old_start
< old_end
) {
1432 for (n
= 0; n
< pavail_rescan_ents
; n
++) {
1433 unsigned long new_start
, new_end
;
1435 new_start
= pavail_rescan
[n
].phys_addr
;
1436 new_end
= new_start
+
1437 pavail_rescan
[n
].reg_size
;
1439 if (new_start
<= old_start
&&
1440 new_end
>= (old_start
+ PAGE_SIZE
)) {
1441 set_bit(old_start
>> 22,
1442 sparc64_valid_addr_bitmap
);
1446 reserve_bootmem(old_start
, PAGE_SIZE
, BOOTMEM_DEFAULT
);
1449 old_start
+= PAGE_SIZE
;
1454 int __init
page_in_phys_avail(unsigned long paddr
)
1460 for (i
= 0; i
< pavail_rescan_ents
; i
++) {
1461 unsigned long start
, end
;
1463 start
= pavail_rescan
[i
].phys_addr
;
1464 end
= start
+ pavail_rescan
[i
].reg_size
;
1466 if (paddr
>= start
&& paddr
< end
)
1469 if (paddr
>= kern_base
&& paddr
< (kern_base
+ kern_size
))
1471 #ifdef CONFIG_BLK_DEV_INITRD
1472 if (paddr
>= __pa(initrd_start
) &&
1473 paddr
< __pa(PAGE_ALIGN(initrd_end
)))
1480 void __init
mem_init(void)
1482 unsigned long codepages
, datapages
, initpages
;
1483 unsigned long addr
, last
;
1486 i
= last_valid_pfn
>> ((22 - PAGE_SHIFT
) + 6);
1488 sparc64_valid_addr_bitmap
= (unsigned long *) alloc_bootmem(i
<< 3);
1489 if (sparc64_valid_addr_bitmap
== NULL
) {
1490 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1493 memset(sparc64_valid_addr_bitmap
, 0, i
<< 3);
1495 addr
= PAGE_OFFSET
+ kern_base
;
1496 last
= PAGE_ALIGN(kern_size
) + addr
;
1497 while (addr
< last
) {
1498 set_bit(__pa(addr
) >> 22, sparc64_valid_addr_bitmap
);
1504 high_memory
= __va(last_valid_pfn
<< PAGE_SHIFT
);
1506 /* We subtract one to account for the mem_map_zero page
1509 totalram_pages
= num_physpages
= free_all_bootmem() - 1;
1512 * Set up the zero page, mark it reserved, so that page count
1513 * is not manipulated when freeing the page from user ptes.
1515 mem_map_zero
= alloc_pages(GFP_KERNEL
|__GFP_ZERO
, 0);
1516 if (mem_map_zero
== NULL
) {
1517 prom_printf("paging_init: Cannot alloc zero page.\n");
1520 SetPageReserved(mem_map_zero
);
1522 codepages
= (((unsigned long) _etext
) - ((unsigned long) _start
));
1523 codepages
= PAGE_ALIGN(codepages
) >> PAGE_SHIFT
;
1524 datapages
= (((unsigned long) _edata
) - ((unsigned long) _etext
));
1525 datapages
= PAGE_ALIGN(datapages
) >> PAGE_SHIFT
;
1526 initpages
= (((unsigned long) __init_end
) - ((unsigned long) __init_begin
));
1527 initpages
= PAGE_ALIGN(initpages
) >> PAGE_SHIFT
;
1529 printk("Memory: %luk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1530 nr_free_pages() << (PAGE_SHIFT
-10),
1531 codepages
<< (PAGE_SHIFT
-10),
1532 datapages
<< (PAGE_SHIFT
-10),
1533 initpages
<< (PAGE_SHIFT
-10),
1534 PAGE_OFFSET
, (last_valid_pfn
<< PAGE_SHIFT
));
1536 if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
)
1537 cheetah_ecache_flush_init();
1540 void free_initmem(void)
1542 unsigned long addr
, initend
;
1545 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1547 addr
= PAGE_ALIGN((unsigned long)(__init_begin
));
1548 initend
= (unsigned long)(__init_end
) & PAGE_MASK
;
1549 for (; addr
< initend
; addr
+= PAGE_SIZE
) {
1554 ((unsigned long) __va(kern_base
)) -
1555 ((unsigned long) KERNBASE
));
1556 memset((void *)addr
, POISON_FREE_INITMEM
, PAGE_SIZE
);
1557 p
= virt_to_page(page
);
1559 ClearPageReserved(p
);
1567 #ifdef CONFIG_BLK_DEV_INITRD
1568 void free_initrd_mem(unsigned long start
, unsigned long end
)
1571 printk ("Freeing initrd memory: %ldk freed\n", (end
- start
) >> 10);
1572 for (; start
< end
; start
+= PAGE_SIZE
) {
1573 struct page
*p
= virt_to_page(start
);
1575 ClearPageReserved(p
);
1584 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
1585 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
1586 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
1587 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
1588 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
1589 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
1591 pgprot_t PAGE_KERNEL __read_mostly
;
1592 EXPORT_SYMBOL(PAGE_KERNEL
);
1594 pgprot_t PAGE_KERNEL_LOCKED __read_mostly
;
1595 pgprot_t PAGE_COPY __read_mostly
;
1597 pgprot_t PAGE_SHARED __read_mostly
;
1598 EXPORT_SYMBOL(PAGE_SHARED
);
1600 pgprot_t PAGE_EXEC __read_mostly
;
1601 unsigned long pg_iobits __read_mostly
;
1603 unsigned long _PAGE_IE __read_mostly
;
1604 EXPORT_SYMBOL(_PAGE_IE
);
1606 unsigned long _PAGE_E __read_mostly
;
1607 EXPORT_SYMBOL(_PAGE_E
);
1609 unsigned long _PAGE_CACHE __read_mostly
;
1610 EXPORT_SYMBOL(_PAGE_CACHE
);
1612 #ifdef CONFIG_SPARSEMEM_VMEMMAP
1614 #define VMEMMAP_CHUNK_SHIFT 22
1615 #define VMEMMAP_CHUNK (1UL << VMEMMAP_CHUNK_SHIFT)
1616 #define VMEMMAP_CHUNK_MASK ~(VMEMMAP_CHUNK - 1UL)
1617 #define VMEMMAP_ALIGN(x) (((x)+VMEMMAP_CHUNK-1UL)&VMEMMAP_CHUNK_MASK)
1619 #define VMEMMAP_SIZE ((((1UL << MAX_PHYSADDR_BITS) >> PAGE_SHIFT) * \
1620 sizeof(struct page *)) >> VMEMMAP_CHUNK_SHIFT)
1621 unsigned long vmemmap_table
[VMEMMAP_SIZE
];
1623 int __meminit
vmemmap_populate(struct page
*start
, unsigned long nr
, int node
)
1625 unsigned long vstart
= (unsigned long) start
;
1626 unsigned long vend
= (unsigned long) (start
+ nr
);
1627 unsigned long phys_start
= (vstart
- VMEMMAP_BASE
);
1628 unsigned long phys_end
= (vend
- VMEMMAP_BASE
);
1629 unsigned long addr
= phys_start
& VMEMMAP_CHUNK_MASK
;
1630 unsigned long end
= VMEMMAP_ALIGN(phys_end
);
1631 unsigned long pte_base
;
1633 pte_base
= (_PAGE_VALID
| _PAGE_SZ4MB_4U
|
1634 _PAGE_CP_4U
| _PAGE_CV_4U
|
1635 _PAGE_P_4U
| _PAGE_W_4U
);
1636 if (tlb_type
== hypervisor
)
1637 pte_base
= (_PAGE_VALID
| _PAGE_SZ4MB_4V
|
1638 _PAGE_CP_4V
| _PAGE_CV_4V
|
1639 _PAGE_P_4V
| _PAGE_W_4V
);
1641 for (; addr
< end
; addr
+= VMEMMAP_CHUNK
) {
1642 unsigned long *vmem_pp
=
1643 vmemmap_table
+ (addr
>> VMEMMAP_CHUNK_SHIFT
);
1646 if (!(*vmem_pp
& _PAGE_VALID
)) {
1647 block
= vmemmap_alloc_block(1UL << 22, node
);
1651 *vmem_pp
= pte_base
| __pa(block
);
1653 printk(KERN_INFO
"[%p-%p] page_structs=%lu "
1654 "node=%d entry=%lu/%lu\n", start
, block
, nr
,
1656 addr
>> VMEMMAP_CHUNK_SHIFT
,
1657 VMEMMAP_SIZE
>> VMEMMAP_CHUNK_SHIFT
);
1662 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
1664 static void prot_init_common(unsigned long page_none
,
1665 unsigned long page_shared
,
1666 unsigned long page_copy
,
1667 unsigned long page_readonly
,
1668 unsigned long page_exec_bit
)
1670 PAGE_COPY
= __pgprot(page_copy
);
1671 PAGE_SHARED
= __pgprot(page_shared
);
1673 protection_map
[0x0] = __pgprot(page_none
);
1674 protection_map
[0x1] = __pgprot(page_readonly
& ~page_exec_bit
);
1675 protection_map
[0x2] = __pgprot(page_copy
& ~page_exec_bit
);
1676 protection_map
[0x3] = __pgprot(page_copy
& ~page_exec_bit
);
1677 protection_map
[0x4] = __pgprot(page_readonly
);
1678 protection_map
[0x5] = __pgprot(page_readonly
);
1679 protection_map
[0x6] = __pgprot(page_copy
);
1680 protection_map
[0x7] = __pgprot(page_copy
);
1681 protection_map
[0x8] = __pgprot(page_none
);
1682 protection_map
[0x9] = __pgprot(page_readonly
& ~page_exec_bit
);
1683 protection_map
[0xa] = __pgprot(page_shared
& ~page_exec_bit
);
1684 protection_map
[0xb] = __pgprot(page_shared
& ~page_exec_bit
);
1685 protection_map
[0xc] = __pgprot(page_readonly
);
1686 protection_map
[0xd] = __pgprot(page_readonly
);
1687 protection_map
[0xe] = __pgprot(page_shared
);
1688 protection_map
[0xf] = __pgprot(page_shared
);
1691 static void __init
sun4u_pgprot_init(void)
1693 unsigned long page_none
, page_shared
, page_copy
, page_readonly
;
1694 unsigned long page_exec_bit
;
1696 PAGE_KERNEL
= __pgprot (_PAGE_PRESENT_4U
| _PAGE_VALID
|
1697 _PAGE_CACHE_4U
| _PAGE_P_4U
|
1698 __ACCESS_BITS_4U
| __DIRTY_BITS_4U
|
1700 PAGE_KERNEL_LOCKED
= __pgprot (_PAGE_PRESENT_4U
| _PAGE_VALID
|
1701 _PAGE_CACHE_4U
| _PAGE_P_4U
|
1702 __ACCESS_BITS_4U
| __DIRTY_BITS_4U
|
1703 _PAGE_EXEC_4U
| _PAGE_L_4U
);
1704 PAGE_EXEC
= __pgprot(_PAGE_EXEC_4U
);
1706 _PAGE_IE
= _PAGE_IE_4U
;
1707 _PAGE_E
= _PAGE_E_4U
;
1708 _PAGE_CACHE
= _PAGE_CACHE_4U
;
1710 pg_iobits
= (_PAGE_VALID
| _PAGE_PRESENT_4U
| __DIRTY_BITS_4U
|
1711 __ACCESS_BITS_4U
| _PAGE_E_4U
);
1713 #ifdef CONFIG_DEBUG_PAGEALLOC
1714 kern_linear_pte_xor
[0] = (_PAGE_VALID
| _PAGE_SZBITS_4U
) ^
1717 kern_linear_pte_xor
[0] = (_PAGE_VALID
| _PAGE_SZ4MB_4U
) ^
1720 kern_linear_pte_xor
[0] |= (_PAGE_CP_4U
| _PAGE_CV_4U
|
1721 _PAGE_P_4U
| _PAGE_W_4U
);
1723 /* XXX Should use 256MB on Panther. XXX */
1724 kern_linear_pte_xor
[1] = kern_linear_pte_xor
[0];
1726 _PAGE_SZBITS
= _PAGE_SZBITS_4U
;
1727 _PAGE_ALL_SZ_BITS
= (_PAGE_SZ4MB_4U
| _PAGE_SZ512K_4U
|
1728 _PAGE_SZ64K_4U
| _PAGE_SZ8K_4U
|
1729 _PAGE_SZ32MB_4U
| _PAGE_SZ256MB_4U
);
1732 page_none
= _PAGE_PRESENT_4U
| _PAGE_ACCESSED_4U
| _PAGE_CACHE_4U
;
1733 page_shared
= (_PAGE_VALID
| _PAGE_PRESENT_4U
| _PAGE_CACHE_4U
|
1734 __ACCESS_BITS_4U
| _PAGE_WRITE_4U
| _PAGE_EXEC_4U
);
1735 page_copy
= (_PAGE_VALID
| _PAGE_PRESENT_4U
| _PAGE_CACHE_4U
|
1736 __ACCESS_BITS_4U
| _PAGE_EXEC_4U
);
1737 page_readonly
= (_PAGE_VALID
| _PAGE_PRESENT_4U
| _PAGE_CACHE_4U
|
1738 __ACCESS_BITS_4U
| _PAGE_EXEC_4U
);
1740 page_exec_bit
= _PAGE_EXEC_4U
;
1742 prot_init_common(page_none
, page_shared
, page_copy
, page_readonly
,
1746 static void __init
sun4v_pgprot_init(void)
1748 unsigned long page_none
, page_shared
, page_copy
, page_readonly
;
1749 unsigned long page_exec_bit
;
1751 PAGE_KERNEL
= __pgprot (_PAGE_PRESENT_4V
| _PAGE_VALID
|
1752 _PAGE_CACHE_4V
| _PAGE_P_4V
|
1753 __ACCESS_BITS_4V
| __DIRTY_BITS_4V
|
1755 PAGE_KERNEL_LOCKED
= PAGE_KERNEL
;
1756 PAGE_EXEC
= __pgprot(_PAGE_EXEC_4V
);
1758 _PAGE_IE
= _PAGE_IE_4V
;
1759 _PAGE_E
= _PAGE_E_4V
;
1760 _PAGE_CACHE
= _PAGE_CACHE_4V
;
1762 #ifdef CONFIG_DEBUG_PAGEALLOC
1763 kern_linear_pte_xor
[0] = (_PAGE_VALID
| _PAGE_SZBITS_4V
) ^
1766 kern_linear_pte_xor
[0] = (_PAGE_VALID
| _PAGE_SZ4MB_4V
) ^
1769 kern_linear_pte_xor
[0] |= (_PAGE_CP_4V
| _PAGE_CV_4V
|
1770 _PAGE_P_4V
| _PAGE_W_4V
);
1772 #ifdef CONFIG_DEBUG_PAGEALLOC
1773 kern_linear_pte_xor
[1] = (_PAGE_VALID
| _PAGE_SZBITS_4V
) ^
1776 kern_linear_pte_xor
[1] = (_PAGE_VALID
| _PAGE_SZ256MB_4V
) ^
1779 kern_linear_pte_xor
[1] |= (_PAGE_CP_4V
| _PAGE_CV_4V
|
1780 _PAGE_P_4V
| _PAGE_W_4V
);
1782 pg_iobits
= (_PAGE_VALID
| _PAGE_PRESENT_4V
| __DIRTY_BITS_4V
|
1783 __ACCESS_BITS_4V
| _PAGE_E_4V
);
1785 _PAGE_SZBITS
= _PAGE_SZBITS_4V
;
1786 _PAGE_ALL_SZ_BITS
= (_PAGE_SZ16GB_4V
| _PAGE_SZ2GB_4V
|
1787 _PAGE_SZ256MB_4V
| _PAGE_SZ32MB_4V
|
1788 _PAGE_SZ4MB_4V
| _PAGE_SZ512K_4V
|
1789 _PAGE_SZ64K_4V
| _PAGE_SZ8K_4V
);
1791 page_none
= _PAGE_PRESENT_4V
| _PAGE_ACCESSED_4V
| _PAGE_CACHE_4V
;
1792 page_shared
= (_PAGE_VALID
| _PAGE_PRESENT_4V
| _PAGE_CACHE_4V
|
1793 __ACCESS_BITS_4V
| _PAGE_WRITE_4V
| _PAGE_EXEC_4V
);
1794 page_copy
= (_PAGE_VALID
| _PAGE_PRESENT_4V
| _PAGE_CACHE_4V
|
1795 __ACCESS_BITS_4V
| _PAGE_EXEC_4V
);
1796 page_readonly
= (_PAGE_VALID
| _PAGE_PRESENT_4V
| _PAGE_CACHE_4V
|
1797 __ACCESS_BITS_4V
| _PAGE_EXEC_4V
);
1799 page_exec_bit
= _PAGE_EXEC_4V
;
1801 prot_init_common(page_none
, page_shared
, page_copy
, page_readonly
,
1805 unsigned long pte_sz_bits(unsigned long sz
)
1807 if (tlb_type
== hypervisor
) {
1811 return _PAGE_SZ8K_4V
;
1813 return _PAGE_SZ64K_4V
;
1815 return _PAGE_SZ512K_4V
;
1816 case 4 * 1024 * 1024:
1817 return _PAGE_SZ4MB_4V
;
1823 return _PAGE_SZ8K_4U
;
1825 return _PAGE_SZ64K_4U
;
1827 return _PAGE_SZ512K_4U
;
1828 case 4 * 1024 * 1024:
1829 return _PAGE_SZ4MB_4U
;
1834 pte_t
mk_pte_io(unsigned long page
, pgprot_t prot
, int space
, unsigned long page_size
)
1838 pte_val(pte
) = page
| pgprot_val(pgprot_noncached(prot
));
1839 pte_val(pte
) |= (((unsigned long)space
) << 32);
1840 pte_val(pte
) |= pte_sz_bits(page_size
);
1845 static unsigned long kern_large_tte(unsigned long paddr
)
1849 val
= (_PAGE_VALID
| _PAGE_SZ4MB_4U
|
1850 _PAGE_CP_4U
| _PAGE_CV_4U
| _PAGE_P_4U
|
1851 _PAGE_EXEC_4U
| _PAGE_L_4U
| _PAGE_W_4U
);
1852 if (tlb_type
== hypervisor
)
1853 val
= (_PAGE_VALID
| _PAGE_SZ4MB_4V
|
1854 _PAGE_CP_4V
| _PAGE_CV_4V
| _PAGE_P_4V
|
1855 _PAGE_EXEC_4V
| _PAGE_W_4V
);
1860 /* If not locked, zap it. */
1861 void __flush_tlb_all(void)
1863 unsigned long pstate
;
1866 __asm__
__volatile__("flushw\n\t"
1867 "rdpr %%pstate, %0\n\t"
1868 "wrpr %0, %1, %%pstate"
1871 if (tlb_type
== hypervisor
) {
1872 sun4v_mmu_demap_all();
1873 } else if (tlb_type
== spitfire
) {
1874 for (i
= 0; i
< 64; i
++) {
1875 /* Spitfire Errata #32 workaround */
1876 /* NOTE: Always runs on spitfire, so no
1877 * cheetah+ page size encodings.
1879 __asm__
__volatile__("stxa %0, [%1] %2\n\t"
1883 "r" (PRIMARY_CONTEXT
), "i" (ASI_DMMU
));
1885 if (!(spitfire_get_dtlb_data(i
) & _PAGE_L_4U
)) {
1886 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
1889 : "r" (TLB_TAG_ACCESS
), "i" (ASI_DMMU
));
1890 spitfire_put_dtlb_data(i
, 0x0UL
);
1893 /* Spitfire Errata #32 workaround */
1894 /* NOTE: Always runs on spitfire, so no
1895 * cheetah+ page size encodings.
1897 __asm__
__volatile__("stxa %0, [%1] %2\n\t"
1901 "r" (PRIMARY_CONTEXT
), "i" (ASI_DMMU
));
1903 if (!(spitfire_get_itlb_data(i
) & _PAGE_L_4U
)) {
1904 __asm__
__volatile__("stxa %%g0, [%0] %1\n\t"
1907 : "r" (TLB_TAG_ACCESS
), "i" (ASI_IMMU
));
1908 spitfire_put_itlb_data(i
, 0x0UL
);
1911 } else if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
1912 cheetah_flush_dtlb_all();
1913 cheetah_flush_itlb_all();
1915 __asm__
__volatile__("wrpr %0, 0, %%pstate"
1919 #ifdef CONFIG_MEMORY_HOTPLUG
1921 void online_page(struct page
*page
)
1923 ClearPageReserved(page
);
1924 init_page_count(page
);
1930 #endif /* CONFIG_MEMORY_HOTPLUG */