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Merge branch 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mfashe...
[mirror_ubuntu-kernels.git] / arch / sparc64 / mm / init.c
1 /* $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
2 * arch/sparc64/mm/init.c
3 *
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
8 #include <linux/module.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/string.h>
12 #include <linux/init.h>
13 #include <linux/bootmem.h>
14 #include <linux/mm.h>
15 #include <linux/hugetlb.h>
16 #include <linux/slab.h>
17 #include <linux/initrd.h>
18 #include <linux/swap.h>
19 #include <linux/pagemap.h>
20 #include <linux/poison.h>
21 #include <linux/fs.h>
22 #include <linux/seq_file.h>
23 #include <linux/kprobes.h>
24 #include <linux/cache.h>
25 #include <linux/sort.h>
26 #include <linux/percpu.h>
27
28 #include <asm/head.h>
29 #include <asm/system.h>
30 #include <asm/page.h>
31 #include <asm/pgalloc.h>
32 #include <asm/pgtable.h>
33 #include <asm/oplib.h>
34 #include <asm/iommu.h>
35 #include <asm/io.h>
36 #include <asm/uaccess.h>
37 #include <asm/mmu_context.h>
38 #include <asm/tlbflush.h>
39 #include <asm/dma.h>
40 #include <asm/starfire.h>
41 #include <asm/tlb.h>
42 #include <asm/spitfire.h>
43 #include <asm/sections.h>
44 #include <asm/tsb.h>
45 #include <asm/hypervisor.h>
46 #include <asm/prom.h>
47 #include <asm/sstate.h>
48 #include <asm/mdesc.h>
49
50 #define MAX_PHYS_ADDRESS (1UL << 42UL)
51 #define KPTE_BITMAP_CHUNK_SZ (256UL * 1024UL * 1024UL)
52 #define KPTE_BITMAP_BYTES \
53 ((MAX_PHYS_ADDRESS / KPTE_BITMAP_CHUNK_SZ) / 8)
54
55 unsigned long kern_linear_pte_xor[2] __read_mostly;
56
57 /* A bitmap, one bit for every 256MB of physical memory. If the bit
58 * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
59 * if set we should use a 256MB page (via kern_linear_pte_xor[1]).
60 */
61 unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
62
63 #ifndef CONFIG_DEBUG_PAGEALLOC
64 /* A special kernel TSB for 4MB and 256MB linear mappings.
65 * Space is allocated for this right after the trap table
66 * in arch/sparc64/kernel/head.S
67 */
68 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
69 #endif
70
71 #define MAX_BANKS 32
72
73 static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
74 static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
75 static int pavail_ents __initdata;
76 static int pavail_rescan_ents __initdata;
77
78 static int cmp_p64(const void *a, const void *b)
79 {
80 const struct linux_prom64_registers *x = a, *y = b;
81
82 if (x->phys_addr > y->phys_addr)
83 return 1;
84 if (x->phys_addr < y->phys_addr)
85 return -1;
86 return 0;
87 }
88
89 static void __init read_obp_memory(const char *property,
90 struct linux_prom64_registers *regs,
91 int *num_ents)
92 {
93 int node = prom_finddevice("/memory");
94 int prop_size = prom_getproplen(node, property);
95 int ents, ret, i;
96
97 ents = prop_size / sizeof(struct linux_prom64_registers);
98 if (ents > MAX_BANKS) {
99 prom_printf("The machine has more %s property entries than "
100 "this kernel can support (%d).\n",
101 property, MAX_BANKS);
102 prom_halt();
103 }
104
105 ret = prom_getproperty(node, property, (char *) regs, prop_size);
106 if (ret == -1) {
107 prom_printf("Couldn't get %s property from /memory.\n");
108 prom_halt();
109 }
110
111 /* Sanitize what we got from the firmware, by page aligning
112 * everything.
113 */
114 for (i = 0; i < ents; i++) {
115 unsigned long base, size;
116
117 base = regs[i].phys_addr;
118 size = regs[i].reg_size;
119
120 size &= PAGE_MASK;
121 if (base & ~PAGE_MASK) {
122 unsigned long new_base = PAGE_ALIGN(base);
123
124 size -= new_base - base;
125 if ((long) size < 0L)
126 size = 0UL;
127 base = new_base;
128 }
129 if (size == 0UL) {
130 /* If it is empty, simply get rid of it.
131 * This simplifies the logic of the other
132 * functions that process these arrays.
133 */
134 memmove(&regs[i], &regs[i + 1],
135 (ents - i - 1) * sizeof(regs[0]));
136 i--;
137 ents--;
138 continue;
139 }
140 regs[i].phys_addr = base;
141 regs[i].reg_size = size;
142 }
143
144 *num_ents = ents;
145
146 sort(regs, ents, sizeof(struct linux_prom64_registers),
147 cmp_p64, NULL);
148 }
149
150 unsigned long *sparc64_valid_addr_bitmap __read_mostly;
151
152 /* Kernel physical address base and size in bytes. */
153 unsigned long kern_base __read_mostly;
154 unsigned long kern_size __read_mostly;
155
156 /* Initial ramdisk setup */
157 extern unsigned long sparc_ramdisk_image64;
158 extern unsigned int sparc_ramdisk_image;
159 extern unsigned int sparc_ramdisk_size;
160
161 struct page *mem_map_zero __read_mostly;
162
163 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
164
165 unsigned long sparc64_kern_pri_context __read_mostly;
166 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
167 unsigned long sparc64_kern_sec_context __read_mostly;
168
169 int bigkernel = 0;
170
171 #ifdef CONFIG_DEBUG_DCFLUSH
172 atomic_t dcpage_flushes = ATOMIC_INIT(0);
173 #ifdef CONFIG_SMP
174 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
175 #endif
176 #endif
177
178 inline void flush_dcache_page_impl(struct page *page)
179 {
180 BUG_ON(tlb_type == hypervisor);
181 #ifdef CONFIG_DEBUG_DCFLUSH
182 atomic_inc(&dcpage_flushes);
183 #endif
184
185 #ifdef DCACHE_ALIASING_POSSIBLE
186 __flush_dcache_page(page_address(page),
187 ((tlb_type == spitfire) &&
188 page_mapping(page) != NULL));
189 #else
190 if (page_mapping(page) != NULL &&
191 tlb_type == spitfire)
192 __flush_icache_page(__pa(page_address(page)));
193 #endif
194 }
195
196 #define PG_dcache_dirty PG_arch_1
197 #define PG_dcache_cpu_shift 32UL
198 #define PG_dcache_cpu_mask \
199 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
200
201 #define dcache_dirty_cpu(page) \
202 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
203
204 static inline void set_dcache_dirty(struct page *page, int this_cpu)
205 {
206 unsigned long mask = this_cpu;
207 unsigned long non_cpu_bits;
208
209 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
210 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
211
212 __asm__ __volatile__("1:\n\t"
213 "ldx [%2], %%g7\n\t"
214 "and %%g7, %1, %%g1\n\t"
215 "or %%g1, %0, %%g1\n\t"
216 "casx [%2], %%g7, %%g1\n\t"
217 "cmp %%g7, %%g1\n\t"
218 "membar #StoreLoad | #StoreStore\n\t"
219 "bne,pn %%xcc, 1b\n\t"
220 " nop"
221 : /* no outputs */
222 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
223 : "g1", "g7");
224 }
225
226 static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
227 {
228 unsigned long mask = (1UL << PG_dcache_dirty);
229
230 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
231 "1:\n\t"
232 "ldx [%2], %%g7\n\t"
233 "srlx %%g7, %4, %%g1\n\t"
234 "and %%g1, %3, %%g1\n\t"
235 "cmp %%g1, %0\n\t"
236 "bne,pn %%icc, 2f\n\t"
237 " andn %%g7, %1, %%g1\n\t"
238 "casx [%2], %%g7, %%g1\n\t"
239 "cmp %%g7, %%g1\n\t"
240 "membar #StoreLoad | #StoreStore\n\t"
241 "bne,pn %%xcc, 1b\n\t"
242 " nop\n"
243 "2:"
244 : /* no outputs */
245 : "r" (cpu), "r" (mask), "r" (&page->flags),
246 "i" (PG_dcache_cpu_mask),
247 "i" (PG_dcache_cpu_shift)
248 : "g1", "g7");
249 }
250
251 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
252 {
253 unsigned long tsb_addr = (unsigned long) ent;
254
255 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
256 tsb_addr = __pa(tsb_addr);
257
258 __tsb_insert(tsb_addr, tag, pte);
259 }
260
261 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
262 unsigned long _PAGE_SZBITS __read_mostly;
263
264 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
265 {
266 struct mm_struct *mm;
267 struct tsb *tsb;
268 unsigned long tag, flags;
269 unsigned long tsb_index, tsb_hash_shift;
270
271 if (tlb_type != hypervisor) {
272 unsigned long pfn = pte_pfn(pte);
273 unsigned long pg_flags;
274 struct page *page;
275
276 if (pfn_valid(pfn) &&
277 (page = pfn_to_page(pfn), page_mapping(page)) &&
278 ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
279 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
280 PG_dcache_cpu_mask);
281 int this_cpu = get_cpu();
282
283 /* This is just to optimize away some function calls
284 * in the SMP case.
285 */
286 if (cpu == this_cpu)
287 flush_dcache_page_impl(page);
288 else
289 smp_flush_dcache_page_impl(page, cpu);
290
291 clear_dcache_dirty_cpu(page, cpu);
292
293 put_cpu();
294 }
295 }
296
297 mm = vma->vm_mm;
298
299 tsb_index = MM_TSB_BASE;
300 tsb_hash_shift = PAGE_SHIFT;
301
302 spin_lock_irqsave(&mm->context.lock, flags);
303
304 #ifdef CONFIG_HUGETLB_PAGE
305 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) {
306 if ((tlb_type == hypervisor &&
307 (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
308 (tlb_type != hypervisor &&
309 (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U)) {
310 tsb_index = MM_TSB_HUGE;
311 tsb_hash_shift = HPAGE_SHIFT;
312 }
313 }
314 #endif
315
316 tsb = mm->context.tsb_block[tsb_index].tsb;
317 tsb += ((address >> tsb_hash_shift) &
318 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
319 tag = (address >> 22UL);
320 tsb_insert(tsb, tag, pte_val(pte));
321
322 spin_unlock_irqrestore(&mm->context.lock, flags);
323 }
324
325 void flush_dcache_page(struct page *page)
326 {
327 struct address_space *mapping;
328 int this_cpu;
329
330 if (tlb_type == hypervisor)
331 return;
332
333 /* Do not bother with the expensive D-cache flush if it
334 * is merely the zero page. The 'bigcore' testcase in GDB
335 * causes this case to run millions of times.
336 */
337 if (page == ZERO_PAGE(0))
338 return;
339
340 this_cpu = get_cpu();
341
342 mapping = page_mapping(page);
343 if (mapping && !mapping_mapped(mapping)) {
344 int dirty = test_bit(PG_dcache_dirty, &page->flags);
345 if (dirty) {
346 int dirty_cpu = dcache_dirty_cpu(page);
347
348 if (dirty_cpu == this_cpu)
349 goto out;
350 smp_flush_dcache_page_impl(page, dirty_cpu);
351 }
352 set_dcache_dirty(page, this_cpu);
353 } else {
354 /* We could delay the flush for the !page_mapping
355 * case too. But that case is for exec env/arg
356 * pages and those are %99 certainly going to get
357 * faulted into the tlb (and thus flushed) anyways.
358 */
359 flush_dcache_page_impl(page);
360 }
361
362 out:
363 put_cpu();
364 }
365
366 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
367 {
368 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
369 if (tlb_type == spitfire) {
370 unsigned long kaddr;
371
372 /* This code only runs on Spitfire cpus so this is
373 * why we can assume _PAGE_PADDR_4U.
374 */
375 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
376 unsigned long paddr, mask = _PAGE_PADDR_4U;
377
378 if (kaddr >= PAGE_OFFSET)
379 paddr = kaddr & mask;
380 else {
381 pgd_t *pgdp = pgd_offset_k(kaddr);
382 pud_t *pudp = pud_offset(pgdp, kaddr);
383 pmd_t *pmdp = pmd_offset(pudp, kaddr);
384 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
385
386 paddr = pte_val(*ptep) & mask;
387 }
388 __flush_icache_page(paddr);
389 }
390 }
391 }
392
393 void show_mem(void)
394 {
395 unsigned long total = 0, reserved = 0;
396 unsigned long shared = 0, cached = 0;
397 pg_data_t *pgdat;
398
399 printk(KERN_INFO "Mem-info:\n");
400 show_free_areas();
401 printk(KERN_INFO "Free swap: %6ldkB\n",
402 nr_swap_pages << (PAGE_SHIFT-10));
403 for_each_online_pgdat(pgdat) {
404 unsigned long i, flags;
405
406 pgdat_resize_lock(pgdat, &flags);
407 for (i = 0; i < pgdat->node_spanned_pages; i++) {
408 struct page *page = pgdat_page_nr(pgdat, i);
409 total++;
410 if (PageReserved(page))
411 reserved++;
412 else if (PageSwapCache(page))
413 cached++;
414 else if (page_count(page))
415 shared += page_count(page) - 1;
416 }
417 pgdat_resize_unlock(pgdat, &flags);
418 }
419
420 printk(KERN_INFO "%lu pages of RAM\n", total);
421 printk(KERN_INFO "%lu reserved pages\n", reserved);
422 printk(KERN_INFO "%lu pages shared\n", shared);
423 printk(KERN_INFO "%lu pages swap cached\n", cached);
424
425 printk(KERN_INFO "%lu pages dirty\n",
426 global_page_state(NR_FILE_DIRTY));
427 printk(KERN_INFO "%lu pages writeback\n",
428 global_page_state(NR_WRITEBACK));
429 printk(KERN_INFO "%lu pages mapped\n",
430 global_page_state(NR_FILE_MAPPED));
431 printk(KERN_INFO "%lu pages slab\n",
432 global_page_state(NR_SLAB_RECLAIMABLE) +
433 global_page_state(NR_SLAB_UNRECLAIMABLE));
434 printk(KERN_INFO "%lu pages pagetables\n",
435 global_page_state(NR_PAGETABLE));
436 }
437
438 void mmu_info(struct seq_file *m)
439 {
440 if (tlb_type == cheetah)
441 seq_printf(m, "MMU Type\t: Cheetah\n");
442 else if (tlb_type == cheetah_plus)
443 seq_printf(m, "MMU Type\t: Cheetah+\n");
444 else if (tlb_type == spitfire)
445 seq_printf(m, "MMU Type\t: Spitfire\n");
446 else if (tlb_type == hypervisor)
447 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
448 else
449 seq_printf(m, "MMU Type\t: ???\n");
450
451 #ifdef CONFIG_DEBUG_DCFLUSH
452 seq_printf(m, "DCPageFlushes\t: %d\n",
453 atomic_read(&dcpage_flushes));
454 #ifdef CONFIG_SMP
455 seq_printf(m, "DCPageFlushesXC\t: %d\n",
456 atomic_read(&dcpage_flushes_xcall));
457 #endif /* CONFIG_SMP */
458 #endif /* CONFIG_DEBUG_DCFLUSH */
459 }
460
461 struct linux_prom_translation {
462 unsigned long virt;
463 unsigned long size;
464 unsigned long data;
465 };
466
467 /* Exported for kernel TLB miss handling in ktlb.S */
468 struct linux_prom_translation prom_trans[512] __read_mostly;
469 unsigned int prom_trans_ents __read_mostly;
470
471 /* Exported for SMP bootup purposes. */
472 unsigned long kern_locked_tte_data;
473
474 /* The obp translations are saved based on 8k pagesize, since obp can
475 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
476 * HI_OBP_ADDRESS range are handled in ktlb.S.
477 */
478 static inline int in_obp_range(unsigned long vaddr)
479 {
480 return (vaddr >= LOW_OBP_ADDRESS &&
481 vaddr < HI_OBP_ADDRESS);
482 }
483
484 static int cmp_ptrans(const void *a, const void *b)
485 {
486 const struct linux_prom_translation *x = a, *y = b;
487
488 if (x->virt > y->virt)
489 return 1;
490 if (x->virt < y->virt)
491 return -1;
492 return 0;
493 }
494
495 /* Read OBP translations property into 'prom_trans[]'. */
496 static void __init read_obp_translations(void)
497 {
498 int n, node, ents, first, last, i;
499
500 node = prom_finddevice("/virtual-memory");
501 n = prom_getproplen(node, "translations");
502 if (unlikely(n == 0 || n == -1)) {
503 prom_printf("prom_mappings: Couldn't get size.\n");
504 prom_halt();
505 }
506 if (unlikely(n > sizeof(prom_trans))) {
507 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
508 prom_halt();
509 }
510
511 if ((n = prom_getproperty(node, "translations",
512 (char *)&prom_trans[0],
513 sizeof(prom_trans))) == -1) {
514 prom_printf("prom_mappings: Couldn't get property.\n");
515 prom_halt();
516 }
517
518 n = n / sizeof(struct linux_prom_translation);
519
520 ents = n;
521
522 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
523 cmp_ptrans, NULL);
524
525 /* Now kick out all the non-OBP entries. */
526 for (i = 0; i < ents; i++) {
527 if (in_obp_range(prom_trans[i].virt))
528 break;
529 }
530 first = i;
531 for (; i < ents; i++) {
532 if (!in_obp_range(prom_trans[i].virt))
533 break;
534 }
535 last = i;
536
537 for (i = 0; i < (last - first); i++) {
538 struct linux_prom_translation *src = &prom_trans[i + first];
539 struct linux_prom_translation *dest = &prom_trans[i];
540
541 *dest = *src;
542 }
543 for (; i < ents; i++) {
544 struct linux_prom_translation *dest = &prom_trans[i];
545 dest->virt = dest->size = dest->data = 0x0UL;
546 }
547
548 prom_trans_ents = last - first;
549
550 if (tlb_type == spitfire) {
551 /* Clear diag TTE bits. */
552 for (i = 0; i < prom_trans_ents; i++)
553 prom_trans[i].data &= ~0x0003fe0000000000UL;
554 }
555 }
556
557 static void __init hypervisor_tlb_lock(unsigned long vaddr,
558 unsigned long pte,
559 unsigned long mmu)
560 {
561 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
562
563 if (ret != 0) {
564 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
565 "errors with %lx\n", vaddr, 0, pte, mmu, ret);
566 prom_halt();
567 }
568 }
569
570 static unsigned long kern_large_tte(unsigned long paddr);
571
572 static void __init remap_kernel(void)
573 {
574 unsigned long phys_page, tte_vaddr, tte_data;
575 int tlb_ent = sparc64_highest_locked_tlbent();
576
577 tte_vaddr = (unsigned long) KERNBASE;
578 phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
579 tte_data = kern_large_tte(phys_page);
580
581 kern_locked_tte_data = tte_data;
582
583 /* Now lock us into the TLBs via Hypervisor or OBP. */
584 if (tlb_type == hypervisor) {
585 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
586 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
587 if (bigkernel) {
588 tte_vaddr += 0x400000;
589 tte_data += 0x400000;
590 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
591 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
592 }
593 } else {
594 prom_dtlb_load(tlb_ent, tte_data, tte_vaddr);
595 prom_itlb_load(tlb_ent, tte_data, tte_vaddr);
596 if (bigkernel) {
597 tlb_ent -= 1;
598 prom_dtlb_load(tlb_ent,
599 tte_data + 0x400000,
600 tte_vaddr + 0x400000);
601 prom_itlb_load(tlb_ent,
602 tte_data + 0x400000,
603 tte_vaddr + 0x400000);
604 }
605 sparc64_highest_unlocked_tlb_ent = tlb_ent - 1;
606 }
607 if (tlb_type == cheetah_plus) {
608 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
609 CTX_CHEETAH_PLUS_NUC);
610 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
611 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
612 }
613 }
614
615
616 static void __init inherit_prom_mappings(void)
617 {
618 read_obp_translations();
619
620 /* Now fixup OBP's idea about where we really are mapped. */
621 prom_printf("Remapping the kernel... ");
622 remap_kernel();
623 prom_printf("done.\n");
624 }
625
626 void prom_world(int enter)
627 {
628 if (!enter)
629 set_fs((mm_segment_t) { get_thread_current_ds() });
630
631 __asm__ __volatile__("flushw");
632 }
633
634 void __flush_dcache_range(unsigned long start, unsigned long end)
635 {
636 unsigned long va;
637
638 if (tlb_type == spitfire) {
639 int n = 0;
640
641 for (va = start; va < end; va += 32) {
642 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
643 if (++n >= 512)
644 break;
645 }
646 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
647 start = __pa(start);
648 end = __pa(end);
649 for (va = start; va < end; va += 32)
650 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
651 "membar #Sync"
652 : /* no outputs */
653 : "r" (va),
654 "i" (ASI_DCACHE_INVALIDATE));
655 }
656 }
657
658 /* get_new_mmu_context() uses "cache + 1". */
659 DEFINE_SPINLOCK(ctx_alloc_lock);
660 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
661 #define MAX_CTX_NR (1UL << CTX_NR_BITS)
662 #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
663 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
664
665 /* Caller does TLB context flushing on local CPU if necessary.
666 * The caller also ensures that CTX_VALID(mm->context) is false.
667 *
668 * We must be careful about boundary cases so that we never
669 * let the user have CTX 0 (nucleus) or we ever use a CTX
670 * version of zero (and thus NO_CONTEXT would not be caught
671 * by version mis-match tests in mmu_context.h).
672 *
673 * Always invoked with interrupts disabled.
674 */
675 void get_new_mmu_context(struct mm_struct *mm)
676 {
677 unsigned long ctx, new_ctx;
678 unsigned long orig_pgsz_bits;
679 unsigned long flags;
680 int new_version;
681
682 spin_lock_irqsave(&ctx_alloc_lock, flags);
683 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
684 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
685 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
686 new_version = 0;
687 if (new_ctx >= (1 << CTX_NR_BITS)) {
688 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
689 if (new_ctx >= ctx) {
690 int i;
691 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
692 CTX_FIRST_VERSION;
693 if (new_ctx == 1)
694 new_ctx = CTX_FIRST_VERSION;
695
696 /* Don't call memset, for 16 entries that's just
697 * plain silly...
698 */
699 mmu_context_bmap[0] = 3;
700 mmu_context_bmap[1] = 0;
701 mmu_context_bmap[2] = 0;
702 mmu_context_bmap[3] = 0;
703 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
704 mmu_context_bmap[i + 0] = 0;
705 mmu_context_bmap[i + 1] = 0;
706 mmu_context_bmap[i + 2] = 0;
707 mmu_context_bmap[i + 3] = 0;
708 }
709 new_version = 1;
710 goto out;
711 }
712 }
713 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
714 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
715 out:
716 tlb_context_cache = new_ctx;
717 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
718 spin_unlock_irqrestore(&ctx_alloc_lock, flags);
719
720 if (unlikely(new_version))
721 smp_new_mmu_context_version();
722 }
723
724 /* Find a free area for the bootmem map, avoiding the kernel image
725 * and the initial ramdisk.
726 */
727 static unsigned long __init choose_bootmap_pfn(unsigned long start_pfn,
728 unsigned long end_pfn)
729 {
730 unsigned long avoid_start, avoid_end, bootmap_size;
731 int i;
732
733 bootmap_size = bootmem_bootmap_pages(end_pfn - start_pfn);
734 bootmap_size <<= PAGE_SHIFT;
735
736 avoid_start = avoid_end = 0;
737 #ifdef CONFIG_BLK_DEV_INITRD
738 avoid_start = initrd_start;
739 avoid_end = PAGE_ALIGN(initrd_end);
740 #endif
741
742 #ifdef CONFIG_DEBUG_BOOTMEM
743 prom_printf("choose_bootmap_pfn: kern[%lx:%lx] avoid[%lx:%lx]\n",
744 kern_base, PAGE_ALIGN(kern_base + kern_size),
745 avoid_start, avoid_end);
746 #endif
747 for (i = 0; i < pavail_ents; i++) {
748 unsigned long start, end;
749
750 start = pavail[i].phys_addr;
751 end = start + pavail[i].reg_size;
752
753 while (start < end) {
754 if (start >= kern_base &&
755 start < PAGE_ALIGN(kern_base + kern_size)) {
756 start = PAGE_ALIGN(kern_base + kern_size);
757 continue;
758 }
759 if (start >= avoid_start && start < avoid_end) {
760 start = avoid_end;
761 continue;
762 }
763
764 if ((end - start) < bootmap_size)
765 break;
766
767 if (start < kern_base &&
768 (start + bootmap_size) > kern_base) {
769 start = PAGE_ALIGN(kern_base + kern_size);
770 continue;
771 }
772
773 if (start < avoid_start &&
774 (start + bootmap_size) > avoid_start) {
775 start = avoid_end;
776 continue;
777 }
778
779 /* OK, it doesn't overlap anything, use it. */
780 #ifdef CONFIG_DEBUG_BOOTMEM
781 prom_printf("choose_bootmap_pfn: Using %lx [%lx]\n",
782 start >> PAGE_SHIFT, start);
783 #endif
784 return start >> PAGE_SHIFT;
785 }
786 }
787
788 prom_printf("Cannot find free area for bootmap, aborting.\n");
789 prom_halt();
790 }
791
792 static void __init trim_pavail(unsigned long *cur_size_p,
793 unsigned long *end_of_phys_p)
794 {
795 unsigned long to_trim = *cur_size_p - cmdline_memory_size;
796 unsigned long avoid_start, avoid_end;
797 int i;
798
799 to_trim = PAGE_ALIGN(to_trim);
800
801 avoid_start = avoid_end = 0;
802 #ifdef CONFIG_BLK_DEV_INITRD
803 avoid_start = initrd_start;
804 avoid_end = PAGE_ALIGN(initrd_end);
805 #endif
806
807 /* Trim some pavail[] entries in order to satisfy the
808 * requested "mem=xxx" kernel command line specification.
809 *
810 * We must not trim off the kernel image area nor the
811 * initial ramdisk range (if any). Also, we must not trim
812 * any pavail[] entry down to zero in order to preserve
813 * the invariant that all pavail[] entries have a non-zero
814 * size which is assumed by all of the code in here.
815 */
816 for (i = 0; i < pavail_ents; i++) {
817 unsigned long start, end, kern_end;
818 unsigned long trim_low, trim_high, n;
819
820 kern_end = PAGE_ALIGN(kern_base + kern_size);
821
822 trim_low = start = pavail[i].phys_addr;
823 trim_high = end = start + pavail[i].reg_size;
824
825 if (kern_base >= start &&
826 kern_base < end) {
827 trim_low = kern_base;
828 if (kern_end >= end)
829 continue;
830 }
831 if (kern_end >= start &&
832 kern_end < end) {
833 trim_high = kern_end;
834 }
835 if (avoid_start &&
836 avoid_start >= start &&
837 avoid_start < end) {
838 if (trim_low > avoid_start)
839 trim_low = avoid_start;
840 if (avoid_end >= end)
841 continue;
842 }
843 if (avoid_end &&
844 avoid_end >= start &&
845 avoid_end < end) {
846 if (trim_high < avoid_end)
847 trim_high = avoid_end;
848 }
849
850 if (trim_high <= trim_low)
851 continue;
852
853 if (trim_low == start && trim_high == end) {
854 /* Whole chunk is available for trimming.
855 * Trim all except one page, in order to keep
856 * entry non-empty.
857 */
858 n = (end - start) - PAGE_SIZE;
859 if (n > to_trim)
860 n = to_trim;
861
862 if (n) {
863 pavail[i].phys_addr += n;
864 pavail[i].reg_size -= n;
865 to_trim -= n;
866 }
867 } else {
868 n = (trim_low - start);
869 if (n > to_trim)
870 n = to_trim;
871
872 if (n) {
873 pavail[i].phys_addr += n;
874 pavail[i].reg_size -= n;
875 to_trim -= n;
876 }
877 if (to_trim) {
878 n = end - trim_high;
879 if (n > to_trim)
880 n = to_trim;
881 if (n) {
882 pavail[i].reg_size -= n;
883 to_trim -= n;
884 }
885 }
886 }
887
888 if (!to_trim)
889 break;
890 }
891
892 /* Recalculate. */
893 *cur_size_p = 0UL;
894 for (i = 0; i < pavail_ents; i++) {
895 *end_of_phys_p = pavail[i].phys_addr +
896 pavail[i].reg_size;
897 *cur_size_p += pavail[i].reg_size;
898 }
899 }
900
901 /* About pages_avail, this is the value we will use to calculate
902 * the zholes_size[] argument given to free_area_init_node(). The
903 * page allocator uses this to calculate nr_kernel_pages,
904 * nr_all_pages and zone->present_pages. On NUMA it is used
905 * to calculate zone->min_unmapped_pages and zone->min_slab_pages.
906 *
907 * So this number should really be set to what the page allocator
908 * actually ends up with. This means:
909 * 1) It should include bootmem map pages, we'll release those.
910 * 2) It should not include the kernel image, except for the
911 * __init sections which we will also release.
912 * 3) It should include the initrd image, since we'll release
913 * that too.
914 */
915 static unsigned long __init bootmem_init(unsigned long *pages_avail,
916 unsigned long phys_base)
917 {
918 unsigned long bootmap_size, end_pfn;
919 unsigned long end_of_phys_memory = 0UL;
920 unsigned long bootmap_pfn, bytes_avail, size;
921 int i;
922
923 #ifdef CONFIG_DEBUG_BOOTMEM
924 prom_printf("bootmem_init: Scan pavail, ");
925 #endif
926
927 bytes_avail = 0UL;
928 for (i = 0; i < pavail_ents; i++) {
929 end_of_phys_memory = pavail[i].phys_addr +
930 pavail[i].reg_size;
931 bytes_avail += pavail[i].reg_size;
932 }
933
934 /* Determine the location of the initial ramdisk before trying
935 * to honor the "mem=xxx" command line argument. We must know
936 * where the kernel image and the ramdisk image are so that we
937 * do not trim those two areas from the physical memory map.
938 */
939
940 #ifdef CONFIG_BLK_DEV_INITRD
941 /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
942 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
943 unsigned long ramdisk_image = sparc_ramdisk_image ?
944 sparc_ramdisk_image : sparc_ramdisk_image64;
945 ramdisk_image -= KERNBASE;
946 initrd_start = ramdisk_image + phys_base;
947 initrd_end = initrd_start + sparc_ramdisk_size;
948 if (initrd_end > end_of_phys_memory) {
949 printk(KERN_CRIT "initrd extends beyond end of memory "
950 "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
951 initrd_end, end_of_phys_memory);
952 initrd_start = 0;
953 initrd_end = 0;
954 }
955 }
956 #endif
957
958 if (cmdline_memory_size &&
959 bytes_avail > cmdline_memory_size)
960 trim_pavail(&bytes_avail,
961 &end_of_phys_memory);
962
963 *pages_avail = bytes_avail >> PAGE_SHIFT;
964
965 end_pfn = end_of_phys_memory >> PAGE_SHIFT;
966
967 /* Initialize the boot-time allocator. */
968 max_pfn = max_low_pfn = end_pfn;
969 min_low_pfn = (phys_base >> PAGE_SHIFT);
970
971 bootmap_pfn = choose_bootmap_pfn(min_low_pfn, end_pfn);
972
973 #ifdef CONFIG_DEBUG_BOOTMEM
974 prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
975 min_low_pfn, bootmap_pfn, max_low_pfn);
976 #endif
977 bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn,
978 min_low_pfn, end_pfn);
979
980 /* Now register the available physical memory with the
981 * allocator.
982 */
983 for (i = 0; i < pavail_ents; i++) {
984 #ifdef CONFIG_DEBUG_BOOTMEM
985 prom_printf("free_bootmem(pavail:%d): base[%lx] size[%lx]\n",
986 i, pavail[i].phys_addr, pavail[i].reg_size);
987 #endif
988 free_bootmem(pavail[i].phys_addr, pavail[i].reg_size);
989 }
990
991 #ifdef CONFIG_BLK_DEV_INITRD
992 if (initrd_start) {
993 size = initrd_end - initrd_start;
994
995 /* Reserve the initrd image area. */
996 #ifdef CONFIG_DEBUG_BOOTMEM
997 prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
998 initrd_start, initrd_end);
999 #endif
1000 reserve_bootmem(initrd_start, size, BOOTMEM_DEFAULT);
1001
1002 initrd_start += PAGE_OFFSET;
1003 initrd_end += PAGE_OFFSET;
1004 }
1005 #endif
1006 /* Reserve the kernel text/data/bss. */
1007 #ifdef CONFIG_DEBUG_BOOTMEM
1008 prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
1009 #endif
1010 reserve_bootmem(kern_base, kern_size, BOOTMEM_DEFAULT);
1011 *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
1012
1013 /* Add back in the initmem pages. */
1014 size = ((unsigned long)(__init_end) & PAGE_MASK) -
1015 PAGE_ALIGN((unsigned long)__init_begin);
1016 *pages_avail += size >> PAGE_SHIFT;
1017
1018 /* Reserve the bootmem map. We do not account for it
1019 * in pages_avail because we will release that memory
1020 * in free_all_bootmem.
1021 */
1022 size = bootmap_size;
1023 #ifdef CONFIG_DEBUG_BOOTMEM
1024 prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
1025 (bootmap_pfn << PAGE_SHIFT), size);
1026 #endif
1027 reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size, BOOTMEM_DEFAULT);
1028
1029 for (i = 0; i < pavail_ents; i++) {
1030 unsigned long start_pfn, end_pfn;
1031
1032 start_pfn = pavail[i].phys_addr >> PAGE_SHIFT;
1033 end_pfn = (start_pfn + (pavail[i].reg_size >> PAGE_SHIFT));
1034 #ifdef CONFIG_DEBUG_BOOTMEM
1035 prom_printf("memory_present(0, %lx, %lx)\n",
1036 start_pfn, end_pfn);
1037 #endif
1038 memory_present(0, start_pfn, end_pfn);
1039 }
1040
1041 sparse_init();
1042
1043 return end_pfn;
1044 }
1045
1046 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1047 static int pall_ents __initdata;
1048
1049 #ifdef CONFIG_DEBUG_PAGEALLOC
1050 static unsigned long kernel_map_range(unsigned long pstart, unsigned long pend, pgprot_t prot)
1051 {
1052 unsigned long vstart = PAGE_OFFSET + pstart;
1053 unsigned long vend = PAGE_OFFSET + pend;
1054 unsigned long alloc_bytes = 0UL;
1055
1056 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1057 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1058 vstart, vend);
1059 prom_halt();
1060 }
1061
1062 while (vstart < vend) {
1063 unsigned long this_end, paddr = __pa(vstart);
1064 pgd_t *pgd = pgd_offset_k(vstart);
1065 pud_t *pud;
1066 pmd_t *pmd;
1067 pte_t *pte;
1068
1069 pud = pud_offset(pgd, vstart);
1070 if (pud_none(*pud)) {
1071 pmd_t *new;
1072
1073 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1074 alloc_bytes += PAGE_SIZE;
1075 pud_populate(&init_mm, pud, new);
1076 }
1077
1078 pmd = pmd_offset(pud, vstart);
1079 if (!pmd_present(*pmd)) {
1080 pte_t *new;
1081
1082 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1083 alloc_bytes += PAGE_SIZE;
1084 pmd_populate_kernel(&init_mm, pmd, new);
1085 }
1086
1087 pte = pte_offset_kernel(pmd, vstart);
1088 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1089 if (this_end > vend)
1090 this_end = vend;
1091
1092 while (vstart < this_end) {
1093 pte_val(*pte) = (paddr | pgprot_val(prot));
1094
1095 vstart += PAGE_SIZE;
1096 paddr += PAGE_SIZE;
1097 pte++;
1098 }
1099 }
1100
1101 return alloc_bytes;
1102 }
1103
1104 extern unsigned int kvmap_linear_patch[1];
1105 #endif /* CONFIG_DEBUG_PAGEALLOC */
1106
1107 static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
1108 {
1109 const unsigned long shift_256MB = 28;
1110 const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL);
1111 const unsigned long size_256MB = (1UL << shift_256MB);
1112
1113 while (start < end) {
1114 long remains;
1115
1116 remains = end - start;
1117 if (remains < size_256MB)
1118 break;
1119
1120 if (start & mask_256MB) {
1121 start = (start + size_256MB) & ~mask_256MB;
1122 continue;
1123 }
1124
1125 while (remains >= size_256MB) {
1126 unsigned long index = start >> shift_256MB;
1127
1128 __set_bit(index, kpte_linear_bitmap);
1129
1130 start += size_256MB;
1131 remains -= size_256MB;
1132 }
1133 }
1134 }
1135
1136 static void __init init_kpte_bitmap(void)
1137 {
1138 unsigned long i;
1139
1140 for (i = 0; i < pall_ents; i++) {
1141 unsigned long phys_start, phys_end;
1142
1143 phys_start = pall[i].phys_addr;
1144 phys_end = phys_start + pall[i].reg_size;
1145
1146 mark_kpte_bitmap(phys_start, phys_end);
1147 }
1148 }
1149
1150 static void __init kernel_physical_mapping_init(void)
1151 {
1152 #ifdef CONFIG_DEBUG_PAGEALLOC
1153 unsigned long i, mem_alloced = 0UL;
1154
1155 for (i = 0; i < pall_ents; i++) {
1156 unsigned long phys_start, phys_end;
1157
1158 phys_start = pall[i].phys_addr;
1159 phys_end = phys_start + pall[i].reg_size;
1160
1161 mem_alloced += kernel_map_range(phys_start, phys_end,
1162 PAGE_KERNEL);
1163 }
1164
1165 printk("Allocated %ld bytes for kernel page tables.\n",
1166 mem_alloced);
1167
1168 kvmap_linear_patch[0] = 0x01000000; /* nop */
1169 flushi(&kvmap_linear_patch[0]);
1170
1171 __flush_tlb_all();
1172 #endif
1173 }
1174
1175 #ifdef CONFIG_DEBUG_PAGEALLOC
1176 void kernel_map_pages(struct page *page, int numpages, int enable)
1177 {
1178 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1179 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1180
1181 kernel_map_range(phys_start, phys_end,
1182 (enable ? PAGE_KERNEL : __pgprot(0)));
1183
1184 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1185 PAGE_OFFSET + phys_end);
1186
1187 /* we should perform an IPI and flush all tlbs,
1188 * but that can deadlock->flush only current cpu.
1189 */
1190 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1191 PAGE_OFFSET + phys_end);
1192 }
1193 #endif
1194
1195 unsigned long __init find_ecache_flush_span(unsigned long size)
1196 {
1197 int i;
1198
1199 for (i = 0; i < pavail_ents; i++) {
1200 if (pavail[i].reg_size >= size)
1201 return pavail[i].phys_addr;
1202 }
1203
1204 return ~0UL;
1205 }
1206
1207 static void __init tsb_phys_patch(void)
1208 {
1209 struct tsb_ldquad_phys_patch_entry *pquad;
1210 struct tsb_phys_patch_entry *p;
1211
1212 pquad = &__tsb_ldquad_phys_patch;
1213 while (pquad < &__tsb_ldquad_phys_patch_end) {
1214 unsigned long addr = pquad->addr;
1215
1216 if (tlb_type == hypervisor)
1217 *(unsigned int *) addr = pquad->sun4v_insn;
1218 else
1219 *(unsigned int *) addr = pquad->sun4u_insn;
1220 wmb();
1221 __asm__ __volatile__("flush %0"
1222 : /* no outputs */
1223 : "r" (addr));
1224
1225 pquad++;
1226 }
1227
1228 p = &__tsb_phys_patch;
1229 while (p < &__tsb_phys_patch_end) {
1230 unsigned long addr = p->addr;
1231
1232 *(unsigned int *) addr = p->insn;
1233 wmb();
1234 __asm__ __volatile__("flush %0"
1235 : /* no outputs */
1236 : "r" (addr));
1237
1238 p++;
1239 }
1240 }
1241
1242 /* Don't mark as init, we give this to the Hypervisor. */
1243 #ifndef CONFIG_DEBUG_PAGEALLOC
1244 #define NUM_KTSB_DESCR 2
1245 #else
1246 #define NUM_KTSB_DESCR 1
1247 #endif
1248 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
1249 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1250
1251 static void __init sun4v_ktsb_init(void)
1252 {
1253 unsigned long ktsb_pa;
1254
1255 /* First KTSB for PAGE_SIZE mappings. */
1256 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1257
1258 switch (PAGE_SIZE) {
1259 case 8 * 1024:
1260 default:
1261 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1262 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1263 break;
1264
1265 case 64 * 1024:
1266 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1267 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1268 break;
1269
1270 case 512 * 1024:
1271 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1272 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1273 break;
1274
1275 case 4 * 1024 * 1024:
1276 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1277 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1278 break;
1279 };
1280
1281 ktsb_descr[0].assoc = 1;
1282 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1283 ktsb_descr[0].ctx_idx = 0;
1284 ktsb_descr[0].tsb_base = ktsb_pa;
1285 ktsb_descr[0].resv = 0;
1286
1287 #ifndef CONFIG_DEBUG_PAGEALLOC
1288 /* Second KTSB for 4MB/256MB mappings. */
1289 ktsb_pa = (kern_base +
1290 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1291
1292 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1293 ktsb_descr[1].pgsz_mask = (HV_PGSZ_MASK_4MB |
1294 HV_PGSZ_MASK_256MB);
1295 ktsb_descr[1].assoc = 1;
1296 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1297 ktsb_descr[1].ctx_idx = 0;
1298 ktsb_descr[1].tsb_base = ktsb_pa;
1299 ktsb_descr[1].resv = 0;
1300 #endif
1301 }
1302
1303 void __cpuinit sun4v_ktsb_register(void)
1304 {
1305 unsigned long pa, ret;
1306
1307 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1308
1309 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
1310 if (ret != 0) {
1311 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1312 "errors with %lx\n", pa, ret);
1313 prom_halt();
1314 }
1315 }
1316
1317 /* paging_init() sets up the page tables */
1318
1319 extern void cheetah_ecache_flush_init(void);
1320 extern void sun4v_patch_tlb_handlers(void);
1321
1322 extern void cpu_probe(void);
1323 extern void central_probe(void);
1324
1325 static unsigned long last_valid_pfn;
1326 pgd_t swapper_pg_dir[2048];
1327
1328 static void sun4u_pgprot_init(void);
1329 static void sun4v_pgprot_init(void);
1330
1331 /* Dummy function */
1332 void __init setup_per_cpu_areas(void)
1333 {
1334 }
1335
1336 void __init paging_init(void)
1337 {
1338 unsigned long end_pfn, pages_avail, shift, phys_base;
1339 unsigned long real_end, i;
1340
1341 /* These build time checkes make sure that the dcache_dirty_cpu()
1342 * page->flags usage will work.
1343 *
1344 * When a page gets marked as dcache-dirty, we store the
1345 * cpu number starting at bit 32 in the page->flags. Also,
1346 * functions like clear_dcache_dirty_cpu use the cpu mask
1347 * in 13-bit signed-immediate instruction fields.
1348 */
1349 BUILD_BUG_ON(FLAGS_RESERVED != 32);
1350 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
1351 ilog2(roundup_pow_of_two(NR_CPUS)) > FLAGS_RESERVED);
1352 BUILD_BUG_ON(NR_CPUS > 4096);
1353
1354 kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1355 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1356
1357 sstate_booting();
1358
1359 /* Invalidate both kernel TSBs. */
1360 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
1361 #ifndef CONFIG_DEBUG_PAGEALLOC
1362 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
1363 #endif
1364
1365 if (tlb_type == hypervisor)
1366 sun4v_pgprot_init();
1367 else
1368 sun4u_pgprot_init();
1369
1370 if (tlb_type == cheetah_plus ||
1371 tlb_type == hypervisor)
1372 tsb_phys_patch();
1373
1374 if (tlb_type == hypervisor) {
1375 sun4v_patch_tlb_handlers();
1376 sun4v_ktsb_init();
1377 }
1378
1379 /* Find available physical memory... */
1380 read_obp_memory("available", &pavail[0], &pavail_ents);
1381
1382 phys_base = 0xffffffffffffffffUL;
1383 for (i = 0; i < pavail_ents; i++)
1384 phys_base = min(phys_base, pavail[i].phys_addr);
1385
1386 set_bit(0, mmu_context_bmap);
1387
1388 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1389
1390 real_end = (unsigned long)_end;
1391 if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1392 bigkernel = 1;
1393 if ((real_end > ((unsigned long)KERNBASE + 0x800000))) {
1394 prom_printf("paging_init: Kernel > 8MB, too large.\n");
1395 prom_halt();
1396 }
1397
1398 /* Set kernel pgd to upper alias so physical page computations
1399 * work.
1400 */
1401 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1402
1403 memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1404
1405 /* Now can init the kernel/bad page tables. */
1406 pud_set(pud_offset(&swapper_pg_dir[0], 0),
1407 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1408
1409 inherit_prom_mappings();
1410
1411 read_obp_memory("reg", &pall[0], &pall_ents);
1412
1413 init_kpte_bitmap();
1414
1415 /* Ok, we can use our TLB miss and window trap handlers safely. */
1416 setup_tba();
1417
1418 __flush_tlb_all();
1419
1420 if (tlb_type == hypervisor)
1421 sun4v_ktsb_register();
1422
1423 /* Setup bootmem... */
1424 pages_avail = 0;
1425 last_valid_pfn = end_pfn = bootmem_init(&pages_avail, phys_base);
1426
1427 max_mapnr = last_valid_pfn;
1428
1429 kernel_physical_mapping_init();
1430
1431 real_setup_per_cpu_areas();
1432
1433 prom_build_devicetree();
1434
1435 if (tlb_type == hypervisor)
1436 sun4v_mdesc_init();
1437
1438 {
1439 unsigned long zones_size[MAX_NR_ZONES];
1440 unsigned long zholes_size[MAX_NR_ZONES];
1441 int znum;
1442
1443 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1444 zones_size[znum] = zholes_size[znum] = 0;
1445
1446 zones_size[ZONE_NORMAL] = end_pfn;
1447 zholes_size[ZONE_NORMAL] = end_pfn - pages_avail;
1448
1449 free_area_init_node(0, &contig_page_data, zones_size,
1450 __pa(PAGE_OFFSET) >> PAGE_SHIFT,
1451 zholes_size);
1452 }
1453
1454 prom_printf("Booting Linux...\n");
1455
1456 central_probe();
1457 cpu_probe();
1458 }
1459
1460 static void __init taint_real_pages(void)
1461 {
1462 int i;
1463
1464 read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1465
1466 /* Find changes discovered in the physmem available rescan and
1467 * reserve the lost portions in the bootmem maps.
1468 */
1469 for (i = 0; i < pavail_ents; i++) {
1470 unsigned long old_start, old_end;
1471
1472 old_start = pavail[i].phys_addr;
1473 old_end = old_start +
1474 pavail[i].reg_size;
1475 while (old_start < old_end) {
1476 int n;
1477
1478 for (n = 0; n < pavail_rescan_ents; n++) {
1479 unsigned long new_start, new_end;
1480
1481 new_start = pavail_rescan[n].phys_addr;
1482 new_end = new_start +
1483 pavail_rescan[n].reg_size;
1484
1485 if (new_start <= old_start &&
1486 new_end >= (old_start + PAGE_SIZE)) {
1487 set_bit(old_start >> 22,
1488 sparc64_valid_addr_bitmap);
1489 goto do_next_page;
1490 }
1491 }
1492 reserve_bootmem(old_start, PAGE_SIZE, BOOTMEM_DEFAULT);
1493
1494 do_next_page:
1495 old_start += PAGE_SIZE;
1496 }
1497 }
1498 }
1499
1500 int __init page_in_phys_avail(unsigned long paddr)
1501 {
1502 int i;
1503
1504 paddr &= PAGE_MASK;
1505
1506 for (i = 0; i < pavail_rescan_ents; i++) {
1507 unsigned long start, end;
1508
1509 start = pavail_rescan[i].phys_addr;
1510 end = start + pavail_rescan[i].reg_size;
1511
1512 if (paddr >= start && paddr < end)
1513 return 1;
1514 }
1515 if (paddr >= kern_base && paddr < (kern_base + kern_size))
1516 return 1;
1517 #ifdef CONFIG_BLK_DEV_INITRD
1518 if (paddr >= __pa(initrd_start) &&
1519 paddr < __pa(PAGE_ALIGN(initrd_end)))
1520 return 1;
1521 #endif
1522
1523 return 0;
1524 }
1525
1526 void __init mem_init(void)
1527 {
1528 unsigned long codepages, datapages, initpages;
1529 unsigned long addr, last;
1530 int i;
1531
1532 i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1533 i += 1;
1534 sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1535 if (sparc64_valid_addr_bitmap == NULL) {
1536 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1537 prom_halt();
1538 }
1539 memset(sparc64_valid_addr_bitmap, 0, i << 3);
1540
1541 addr = PAGE_OFFSET + kern_base;
1542 last = PAGE_ALIGN(kern_size) + addr;
1543 while (addr < last) {
1544 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1545 addr += PAGE_SIZE;
1546 }
1547
1548 taint_real_pages();
1549
1550 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1551
1552 #ifdef CONFIG_DEBUG_BOOTMEM
1553 prom_printf("mem_init: Calling free_all_bootmem().\n");
1554 #endif
1555
1556 /* We subtract one to account for the mem_map_zero page
1557 * allocated below.
1558 */
1559 totalram_pages = num_physpages = free_all_bootmem() - 1;
1560
1561 /*
1562 * Set up the zero page, mark it reserved, so that page count
1563 * is not manipulated when freeing the page from user ptes.
1564 */
1565 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1566 if (mem_map_zero == NULL) {
1567 prom_printf("paging_init: Cannot alloc zero page.\n");
1568 prom_halt();
1569 }
1570 SetPageReserved(mem_map_zero);
1571
1572 codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1573 codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1574 datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1575 datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1576 initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1577 initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1578
1579 printk("Memory: %luk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1580 nr_free_pages() << (PAGE_SHIFT-10),
1581 codepages << (PAGE_SHIFT-10),
1582 datapages << (PAGE_SHIFT-10),
1583 initpages << (PAGE_SHIFT-10),
1584 PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1585
1586 if (tlb_type == cheetah || tlb_type == cheetah_plus)
1587 cheetah_ecache_flush_init();
1588 }
1589
1590 void free_initmem(void)
1591 {
1592 unsigned long addr, initend;
1593
1594 /*
1595 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1596 */
1597 addr = PAGE_ALIGN((unsigned long)(__init_begin));
1598 initend = (unsigned long)(__init_end) & PAGE_MASK;
1599 for (; addr < initend; addr += PAGE_SIZE) {
1600 unsigned long page;
1601 struct page *p;
1602
1603 page = (addr +
1604 ((unsigned long) __va(kern_base)) -
1605 ((unsigned long) KERNBASE));
1606 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
1607 p = virt_to_page(page);
1608
1609 ClearPageReserved(p);
1610 init_page_count(p);
1611 __free_page(p);
1612 num_physpages++;
1613 totalram_pages++;
1614 }
1615 }
1616
1617 #ifdef CONFIG_BLK_DEV_INITRD
1618 void free_initrd_mem(unsigned long start, unsigned long end)
1619 {
1620 if (start < end)
1621 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1622 for (; start < end; start += PAGE_SIZE) {
1623 struct page *p = virt_to_page(start);
1624
1625 ClearPageReserved(p);
1626 init_page_count(p);
1627 __free_page(p);
1628 num_physpages++;
1629 totalram_pages++;
1630 }
1631 }
1632 #endif
1633
1634 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
1635 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
1636 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
1637 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
1638 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
1639 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
1640
1641 pgprot_t PAGE_KERNEL __read_mostly;
1642 EXPORT_SYMBOL(PAGE_KERNEL);
1643
1644 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
1645 pgprot_t PAGE_COPY __read_mostly;
1646
1647 pgprot_t PAGE_SHARED __read_mostly;
1648 EXPORT_SYMBOL(PAGE_SHARED);
1649
1650 pgprot_t PAGE_EXEC __read_mostly;
1651 unsigned long pg_iobits __read_mostly;
1652
1653 unsigned long _PAGE_IE __read_mostly;
1654 EXPORT_SYMBOL(_PAGE_IE);
1655
1656 unsigned long _PAGE_E __read_mostly;
1657 EXPORT_SYMBOL(_PAGE_E);
1658
1659 unsigned long _PAGE_CACHE __read_mostly;
1660 EXPORT_SYMBOL(_PAGE_CACHE);
1661
1662 #ifdef CONFIG_SPARSEMEM_VMEMMAP
1663
1664 #define VMEMMAP_CHUNK_SHIFT 22
1665 #define VMEMMAP_CHUNK (1UL << VMEMMAP_CHUNK_SHIFT)
1666 #define VMEMMAP_CHUNK_MASK ~(VMEMMAP_CHUNK - 1UL)
1667 #define VMEMMAP_ALIGN(x) (((x)+VMEMMAP_CHUNK-1UL)&VMEMMAP_CHUNK_MASK)
1668
1669 #define VMEMMAP_SIZE ((((1UL << MAX_PHYSADDR_BITS) >> PAGE_SHIFT) * \
1670 sizeof(struct page *)) >> VMEMMAP_CHUNK_SHIFT)
1671 unsigned long vmemmap_table[VMEMMAP_SIZE];
1672
1673 int __meminit vmemmap_populate(struct page *start, unsigned long nr, int node)
1674 {
1675 unsigned long vstart = (unsigned long) start;
1676 unsigned long vend = (unsigned long) (start + nr);
1677 unsigned long phys_start = (vstart - VMEMMAP_BASE);
1678 unsigned long phys_end = (vend - VMEMMAP_BASE);
1679 unsigned long addr = phys_start & VMEMMAP_CHUNK_MASK;
1680 unsigned long end = VMEMMAP_ALIGN(phys_end);
1681 unsigned long pte_base;
1682
1683 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
1684 _PAGE_CP_4U | _PAGE_CV_4U |
1685 _PAGE_P_4U | _PAGE_W_4U);
1686 if (tlb_type == hypervisor)
1687 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
1688 _PAGE_CP_4V | _PAGE_CV_4V |
1689 _PAGE_P_4V | _PAGE_W_4V);
1690
1691 for (; addr < end; addr += VMEMMAP_CHUNK) {
1692 unsigned long *vmem_pp =
1693 vmemmap_table + (addr >> VMEMMAP_CHUNK_SHIFT);
1694 void *block;
1695
1696 if (!(*vmem_pp & _PAGE_VALID)) {
1697 block = vmemmap_alloc_block(1UL << 22, node);
1698 if (!block)
1699 return -ENOMEM;
1700
1701 *vmem_pp = pte_base | __pa(block);
1702
1703 printk(KERN_INFO "[%p-%p] page_structs=%lu "
1704 "node=%d entry=%lu/%lu\n", start, block, nr,
1705 node,
1706 addr >> VMEMMAP_CHUNK_SHIFT,
1707 VMEMMAP_SIZE >> VMEMMAP_CHUNK_SHIFT);
1708 }
1709 }
1710 return 0;
1711 }
1712 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
1713
1714 static void prot_init_common(unsigned long page_none,
1715 unsigned long page_shared,
1716 unsigned long page_copy,
1717 unsigned long page_readonly,
1718 unsigned long page_exec_bit)
1719 {
1720 PAGE_COPY = __pgprot(page_copy);
1721 PAGE_SHARED = __pgprot(page_shared);
1722
1723 protection_map[0x0] = __pgprot(page_none);
1724 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
1725 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
1726 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
1727 protection_map[0x4] = __pgprot(page_readonly);
1728 protection_map[0x5] = __pgprot(page_readonly);
1729 protection_map[0x6] = __pgprot(page_copy);
1730 protection_map[0x7] = __pgprot(page_copy);
1731 protection_map[0x8] = __pgprot(page_none);
1732 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
1733 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
1734 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
1735 protection_map[0xc] = __pgprot(page_readonly);
1736 protection_map[0xd] = __pgprot(page_readonly);
1737 protection_map[0xe] = __pgprot(page_shared);
1738 protection_map[0xf] = __pgprot(page_shared);
1739 }
1740
1741 static void __init sun4u_pgprot_init(void)
1742 {
1743 unsigned long page_none, page_shared, page_copy, page_readonly;
1744 unsigned long page_exec_bit;
1745
1746 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1747 _PAGE_CACHE_4U | _PAGE_P_4U |
1748 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1749 _PAGE_EXEC_4U);
1750 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1751 _PAGE_CACHE_4U | _PAGE_P_4U |
1752 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1753 _PAGE_EXEC_4U | _PAGE_L_4U);
1754 PAGE_EXEC = __pgprot(_PAGE_EXEC_4U);
1755
1756 _PAGE_IE = _PAGE_IE_4U;
1757 _PAGE_E = _PAGE_E_4U;
1758 _PAGE_CACHE = _PAGE_CACHE_4U;
1759
1760 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
1761 __ACCESS_BITS_4U | _PAGE_E_4U);
1762
1763 #ifdef CONFIG_DEBUG_PAGEALLOC
1764 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4U) ^
1765 0xfffff80000000000;
1766 #else
1767 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
1768 0xfffff80000000000;
1769 #endif
1770 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
1771 _PAGE_P_4U | _PAGE_W_4U);
1772
1773 /* XXX Should use 256MB on Panther. XXX */
1774 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
1775
1776 _PAGE_SZBITS = _PAGE_SZBITS_4U;
1777 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
1778 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
1779 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
1780
1781
1782 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
1783 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1784 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
1785 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1786 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1787 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1788 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1789
1790 page_exec_bit = _PAGE_EXEC_4U;
1791
1792 prot_init_common(page_none, page_shared, page_copy, page_readonly,
1793 page_exec_bit);
1794 }
1795
1796 static void __init sun4v_pgprot_init(void)
1797 {
1798 unsigned long page_none, page_shared, page_copy, page_readonly;
1799 unsigned long page_exec_bit;
1800
1801 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
1802 _PAGE_CACHE_4V | _PAGE_P_4V |
1803 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
1804 _PAGE_EXEC_4V);
1805 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
1806 PAGE_EXEC = __pgprot(_PAGE_EXEC_4V);
1807
1808 _PAGE_IE = _PAGE_IE_4V;
1809 _PAGE_E = _PAGE_E_4V;
1810 _PAGE_CACHE = _PAGE_CACHE_4V;
1811
1812 #ifdef CONFIG_DEBUG_PAGEALLOC
1813 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
1814 0xfffff80000000000;
1815 #else
1816 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
1817 0xfffff80000000000;
1818 #endif
1819 kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1820 _PAGE_P_4V | _PAGE_W_4V);
1821
1822 #ifdef CONFIG_DEBUG_PAGEALLOC
1823 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
1824 0xfffff80000000000;
1825 #else
1826 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
1827 0xfffff80000000000;
1828 #endif
1829 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1830 _PAGE_P_4V | _PAGE_W_4V);
1831
1832 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
1833 __ACCESS_BITS_4V | _PAGE_E_4V);
1834
1835 _PAGE_SZBITS = _PAGE_SZBITS_4V;
1836 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
1837 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
1838 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
1839 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
1840
1841 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
1842 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1843 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
1844 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1845 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1846 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1847 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1848
1849 page_exec_bit = _PAGE_EXEC_4V;
1850
1851 prot_init_common(page_none, page_shared, page_copy, page_readonly,
1852 page_exec_bit);
1853 }
1854
1855 unsigned long pte_sz_bits(unsigned long sz)
1856 {
1857 if (tlb_type == hypervisor) {
1858 switch (sz) {
1859 case 8 * 1024:
1860 default:
1861 return _PAGE_SZ8K_4V;
1862 case 64 * 1024:
1863 return _PAGE_SZ64K_4V;
1864 case 512 * 1024:
1865 return _PAGE_SZ512K_4V;
1866 case 4 * 1024 * 1024:
1867 return _PAGE_SZ4MB_4V;
1868 };
1869 } else {
1870 switch (sz) {
1871 case 8 * 1024:
1872 default:
1873 return _PAGE_SZ8K_4U;
1874 case 64 * 1024:
1875 return _PAGE_SZ64K_4U;
1876 case 512 * 1024:
1877 return _PAGE_SZ512K_4U;
1878 case 4 * 1024 * 1024:
1879 return _PAGE_SZ4MB_4U;
1880 };
1881 }
1882 }
1883
1884 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
1885 {
1886 pte_t pte;
1887
1888 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
1889 pte_val(pte) |= (((unsigned long)space) << 32);
1890 pte_val(pte) |= pte_sz_bits(page_size);
1891
1892 return pte;
1893 }
1894
1895 static unsigned long kern_large_tte(unsigned long paddr)
1896 {
1897 unsigned long val;
1898
1899 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
1900 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
1901 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
1902 if (tlb_type == hypervisor)
1903 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
1904 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
1905 _PAGE_EXEC_4V | _PAGE_W_4V);
1906
1907 return val | paddr;
1908 }
1909
1910 /* If not locked, zap it. */
1911 void __flush_tlb_all(void)
1912 {
1913 unsigned long pstate;
1914 int i;
1915
1916 __asm__ __volatile__("flushw\n\t"
1917 "rdpr %%pstate, %0\n\t"
1918 "wrpr %0, %1, %%pstate"
1919 : "=r" (pstate)
1920 : "i" (PSTATE_IE));
1921 if (tlb_type == hypervisor) {
1922 sun4v_mmu_demap_all();
1923 } else if (tlb_type == spitfire) {
1924 for (i = 0; i < 64; i++) {
1925 /* Spitfire Errata #32 workaround */
1926 /* NOTE: Always runs on spitfire, so no
1927 * cheetah+ page size encodings.
1928 */
1929 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1930 "flush %%g6"
1931 : /* No outputs */
1932 : "r" (0),
1933 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1934
1935 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
1936 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1937 "membar #Sync"
1938 : /* no outputs */
1939 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
1940 spitfire_put_dtlb_data(i, 0x0UL);
1941 }
1942
1943 /* Spitfire Errata #32 workaround */
1944 /* NOTE: Always runs on spitfire, so no
1945 * cheetah+ page size encodings.
1946 */
1947 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1948 "flush %%g6"
1949 : /* No outputs */
1950 : "r" (0),
1951 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1952
1953 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
1954 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1955 "membar #Sync"
1956 : /* no outputs */
1957 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
1958 spitfire_put_itlb_data(i, 0x0UL);
1959 }
1960 }
1961 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1962 cheetah_flush_dtlb_all();
1963 cheetah_flush_itlb_all();
1964 }
1965 __asm__ __volatile__("wrpr %0, 0, %%pstate"
1966 : : "r" (pstate));
1967 }
1968
1969 #ifdef CONFIG_MEMORY_HOTPLUG
1970
1971 void online_page(struct page *page)
1972 {
1973 ClearPageReserved(page);
1974 init_page_count(page);
1975 __free_page(page);
1976 totalram_pages++;
1977 num_physpages++;
1978 }
1979
1980 #endif /* CONFIG_MEMORY_HOTPLUG */
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