arch/tile/include/uapi/arch/icache.h

   1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
   2 /*
   3  * Copyright 2010 Tilera Corporation. All Rights Reserved.
   4  *
   5  *   This program is free software; you can redistribute it and/or
   6  *   modify it under the terms of the GNU General Public License
   7  *   as published by the Free Software Foundation, version 2.
   8  *
   9  *   This program is distributed in the hope that it will be useful, but
  10  *   WITHOUT ANY WARRANTY; without even the implied warranty of
  11  *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  12  *   NON INFRINGEMENT.  See the GNU General Public License for
  13  *   more details.
  14  *
  15  */
  16
  17 /**
  18  * @file
  19  *
  20  * Support for invalidating bytes in the instruction cache.
  21  */
  22
  23 #ifndef __ARCH_ICACHE_H__
  24 #define __ARCH_ICACHE_H__
  25
  26 #include <arch/chip.h>
  27
  28
  29 /**
  30  * Invalidate the instruction cache for the given range of memory.
  31  *
  32  * @param addr The start of memory to be invalidated.
  33  * @param size The number of bytes to be invalidated.
  34  * @param page_size The system's page size, e.g. getpagesize() in userspace.
  35  * This value must be a power of two no larger than the page containing
  36  * the code to be invalidated. If the value is smaller than the actual page
  37  * size, this function will still work, but may run slower than necessary.
  38  */
  39 static __inline void
  40 invalidate_icache(const void* addr, unsigned long size,
  41                   unsigned long page_size)
  42 {
  43   const unsigned long cache_way_size =
  44     CHIP_L1I_CACHE_SIZE() / CHIP_L1I_ASSOC();
  45   unsigned long max_useful_size;
  46   const char* start, *end;
  47   long num_passes;
  48
  49   if (__builtin_expect(size == 0, 0))
  50     return;
  51
  52 #ifdef __tilegx__
  53   /* Limit the number of bytes visited to avoid redundant iterations. */
  54   max_useful_size = (page_size < cache_way_size) ? page_size : cache_way_size;
  55
  56   /* No PA aliasing is possible, so one pass always suffices. */
  57   num_passes = 1;
  58 #else
  59   /* Limit the number of bytes visited to avoid redundant iterations. */
  60   max_useful_size = cache_way_size;
  61
  62   /*
  63    * Compute how many passes we need (we'll treat 0 as if it were 1).
  64    * This works because we know the page size is a power of two.
  65    */
  66   num_passes = cache_way_size >> __builtin_ctzl(page_size);
  67 #endif
  68
  69   if (__builtin_expect(size > max_useful_size, 0))
  70     size = max_useful_size;
  71
  72   /* Locate the first and last bytes to be invalidated. */
  73   start = (const char *)((unsigned long)addr & -CHIP_L1I_LINE_SIZE());
  74   end = (const char*)addr + size - 1;
  75
  76   __insn_mf();
  77
  78   do
  79   {
  80     const char* p;
  81
  82     for (p = start; p <= end; p += CHIP_L1I_LINE_SIZE())
  83       __insn_icoh(p);
  84
  85     start += page_size;
  86     end += page_size;
  87   }
  88   while (--num_passes > 0);
  89
  90   __insn_drain();
  91 }
  92
  93
  94 #endif /* __ARCH_ICACHE_H__ */