arch/x86/crypto/sha512-avx-asm.S

   1 ########################################################################
   2 # Implement fast SHA-512 with AVX instructions. (x86_64)
   3 #
   4 # Copyright (C) 2013 Intel Corporation.
   5 #
   6 # Authors:
   7 #     James Guilford <james.guilford@intel.com>
   8 #     Kirk Yap <kirk.s.yap@intel.com>
   9 #     David Cote <david.m.cote@intel.com>
  10 #     Tim Chen <tim.c.chen@linux.intel.com>
  11 #
  12 # This software is available to you under a choice of one of two
  13 # licenses.  You may choose to be licensed under the terms of the GNU
  14 # General Public License (GPL) Version 2, available from the file
  15 # COPYING in the main directory of this source tree, or the
  16 # OpenIB.org BSD license below:
  17 #
  18 #     Redistribution and use in source and binary forms, with or
  19 #     without modification, are permitted provided that the following
  20 #     conditions are met:
  21 #
  22 #      - Redistributions of source code must retain the above
  23 #        copyright notice, this list of conditions and the following
  24 #        disclaimer.
  25 #
  26 #      - Redistributions in binary form must reproduce the above
  27 #        copyright notice, this list of conditions and the following
  28 #        disclaimer in the documentation and/or other materials
  29 #        provided with the distribution.
  30 #
  31 # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32 # EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  33 # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34 # NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  35 # BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  36 # ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  37 # CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  38 # SOFTWARE.
  39 #
  40 ########################################################################
  41 #
  42 # This code is described in an Intel White-Paper:
  43 # "Fast SHA-512 Implementations on Intel Architecture Processors"
  44 #
  45 # To find it, surf to http://www.intel.com/p/en_US/embedded
  46 # and search for that title.
  47 #
  48 ########################################################################
  49
  50 #ifdef CONFIG_AS_AVX
  51 #include <linux/linkage.h>
  52
  53 .text
  54
  55 # Virtual Registers
  56 # ARG1
  57 digest  = %rdi
  58 # ARG2
  59 msg     = %rsi
  60 # ARG3
  61 msglen  = %rdx
  62 T1      = %rcx
  63 T2      = %r8
  64 a_64    = %r9
  65 b_64    = %r10
  66 c_64    = %r11
  67 d_64    = %r12
  68 e_64    = %r13
  69 f_64    = %r14
  70 g_64    = %r15
  71 h_64    = %rbx
  72 tmp0    = %rax
  73
  74 # Local variables (stack frame)
  75
  76 # Message Schedule
  77 W_SIZE = 80*8
  78 # W[t] + K[t] | W[t+1] + K[t+1]
  79 WK_SIZE = 2*8
  80 RSPSAVE_SIZE = 1*8
  81 GPRSAVE_SIZE = 5*8
  82
  83 frame_W = 0
  84 frame_WK = frame_W + W_SIZE
  85 frame_RSPSAVE = frame_WK + WK_SIZE
  86 frame_GPRSAVE = frame_RSPSAVE + RSPSAVE_SIZE
  87 frame_size = frame_GPRSAVE + GPRSAVE_SIZE
  88
  89 # Useful QWORD "arrays" for simpler memory references
  90 # MSG, DIGEST, K_t, W_t are arrays
  91 # WK_2(t) points to 1 of 2 qwords at frame.WK depdending on t being odd/even
  92
  93 # Input message (arg1)
  94 #define MSG(i)    8*i(msg)
  95
  96 # Output Digest (arg2)
  97 #define DIGEST(i) 8*i(digest)
  98
  99 # SHA Constants (static mem)
 100 #define K_t(i)    8*i+K512(%rip)
 101
 102 # Message Schedule (stack frame)
 103 #define W_t(i)    8*i+frame_W(%rsp)
 104
 105 # W[t]+K[t] (stack frame)
 106 #define WK_2(i)   8*((i%2))+frame_WK(%rsp)
 107
 108 .macro RotateState
 109         # Rotate symbols a..h right
 110         TMP   = h_64
 111         h_64  = g_64
 112         g_64  = f_64
 113         f_64  = e_64
 114         e_64  = d_64
 115         d_64  = c_64
 116         c_64  = b_64
 117         b_64  = a_64
 118         a_64  = TMP
 119 .endm
 120
 121 .macro RORQ p1 p2
 122         # shld is faster than ror on Sandybridge
 123         shld    $(64-\p2), \p1, \p1
 124 .endm
 125
 126 .macro SHA512_Round rnd
 127         # Compute Round %%t
 128         mov     f_64, T1          # T1 = f
 129         mov     e_64, tmp0        # tmp = e
 130         xor     g_64, T1          # T1 = f ^ g
 131         RORQ    tmp0, 23   # 41    # tmp = e ror 23
 132         and     e_64, T1          # T1 = (f ^ g) & e
 133         xor     e_64, tmp0        # tmp = (e ror 23) ^ e
 134         xor     g_64, T1          # T1 = ((f ^ g) & e) ^ g = CH(e,f,g)
 135         idx = \rnd
 136         add     WK_2(idx), T1     # W[t] + K[t] from message scheduler
 137         RORQ    tmp0, 4   # 18    # tmp = ((e ror 23) ^ e) ror 4
 138         xor     e_64, tmp0        # tmp = (((e ror 23) ^ e) ror 4) ^ e
 139         mov     a_64, T2          # T2 = a
 140         add     h_64, T1          # T1 = CH(e,f,g) + W[t] + K[t] + h
 141         RORQ    tmp0, 14  # 14    # tmp = ((((e ror23)^e)ror4)^e)ror14 = S1(e)
 142         add     tmp0, T1          # T1 = CH(e,f,g) + W[t] + K[t] + S1(e)
 143         mov     a_64, tmp0        # tmp = a
 144         xor     c_64, T2          # T2 = a ^ c
 145         and     c_64, tmp0        # tmp = a & c
 146         and     b_64, T2          # T2 = (a ^ c) & b
 147         xor     tmp0, T2          # T2 = ((a ^ c) & b) ^ (a & c) = Maj(a,b,c)
 148         mov     a_64, tmp0        # tmp = a
 149         RORQ    tmp0, 5  # 39     # tmp = a ror 5
 150         xor     a_64, tmp0        # tmp = (a ror 5) ^ a
 151         add     T1, d_64          # e(next_state) = d + T1
 152         RORQ    tmp0, 6  # 34     # tmp = ((a ror 5) ^ a) ror 6
 153         xor     a_64, tmp0        # tmp = (((a ror 5) ^ a) ror 6) ^ a
 154         lea     (T1, T2), h_64    # a(next_state) = T1 + Maj(a,b,c)
 155         RORQ    tmp0, 28  # 28    # tmp = ((((a ror5)^a)ror6)^a)ror28 = S0(a)
 156         add     tmp0, h_64        # a(next_state) = T1 + Maj(a,b,c) S0(a)
 157         RotateState
 158 .endm
 159
 160 .macro SHA512_2Sched_2Round_avx rnd
 161         # Compute rounds t-2 and t-1
 162         # Compute message schedule QWORDS t and t+1
 163
 164         #   Two rounds are computed based on the values for K[t-2]+W[t-2] and
 165         # K[t-1]+W[t-1] which were previously stored at WK_2 by the message
 166         # scheduler.
 167         #   The two new schedule QWORDS are stored at [W_t(t)] and [W_t(t+1)].
 168         # They are then added to their respective SHA512 constants at
 169         # [K_t(t)] and [K_t(t+1)] and stored at dqword [WK_2(t)]
 170         #   For brievity, the comments following vectored instructions only refer to
 171         # the first of a pair of QWORDS.
 172         # Eg. XMM4=W[t-2] really means XMM4={W[t-2]|W[t-1]}
 173         #   The computation of the message schedule and the rounds are tightly
 174         # stitched to take advantage of instruction-level parallelism.
 175
 176         idx = \rnd - 2
 177         vmovdqa W_t(idx), %xmm4         # XMM4 = W[t-2]
 178         idx = \rnd - 15
 179         vmovdqu W_t(idx), %xmm5         # XMM5 = W[t-15]
 180         mov     f_64, T1
 181         vpsrlq  $61, %xmm4, %xmm0       # XMM0 = W[t-2]>>61
 182         mov     e_64, tmp0
 183         vpsrlq  $1, %xmm5, %xmm6        # XMM6 = W[t-15]>>1
 184         xor     g_64, T1
 185         RORQ    tmp0, 23 # 41
 186         vpsrlq  $19, %xmm4, %xmm1       # XMM1 = W[t-2]>>19
 187         and     e_64, T1
 188         xor     e_64, tmp0
 189         vpxor   %xmm1, %xmm0, %xmm0     # XMM0 = W[t-2]>>61 ^ W[t-2]>>19
 190         xor     g_64, T1
 191         idx = \rnd
 192         add     WK_2(idx), T1#
 193         vpsrlq  $8, %xmm5, %xmm7        # XMM7 = W[t-15]>>8
 194         RORQ    tmp0, 4 # 18
 195         vpsrlq  $6, %xmm4, %xmm2        # XMM2 = W[t-2]>>6
 196         xor     e_64, tmp0
 197         mov     a_64, T2
 198         add     h_64, T1
 199         vpxor   %xmm7, %xmm6, %xmm6     # XMM6 = W[t-15]>>1 ^ W[t-15]>>8
 200         RORQ    tmp0, 14 # 14
 201         add     tmp0, T1
 202         vpsrlq  $7, %xmm5, %xmm8        # XMM8 = W[t-15]>>7
 203         mov     a_64, tmp0
 204         xor     c_64, T2
 205         vpsllq  $(64-61), %xmm4, %xmm3  # XMM3 = W[t-2]<<3
 206         and     c_64, tmp0
 207         and     b_64, T2
 208         vpxor   %xmm3, %xmm2, %xmm2     # XMM2 = W[t-2]>>6 ^ W[t-2]<<3
 209         xor     tmp0, T2
 210         mov     a_64, tmp0
 211         vpsllq  $(64-1), %xmm5, %xmm9   # XMM9 = W[t-15]<<63
 212         RORQ    tmp0, 5 # 39
 213         vpxor   %xmm9, %xmm8, %xmm8     # XMM8 = W[t-15]>>7 ^ W[t-15]<<63
 214         xor     a_64, tmp0
 215         add     T1, d_64
 216         RORQ    tmp0, 6 # 34
 217         xor     a_64, tmp0
 218         vpxor   %xmm8, %xmm6, %xmm6     # XMM6 = W[t-15]>>1 ^ W[t-15]>>8 ^
 219                                         #  W[t-15]>>7 ^ W[t-15]<<63
 220         lea     (T1, T2), h_64
 221         RORQ    tmp0, 28 # 28
 222         vpsllq  $(64-19), %xmm4, %xmm4  # XMM4 = W[t-2]<<25
 223         add     tmp0, h_64
 224         RotateState
 225         vpxor   %xmm4, %xmm0, %xmm0     # XMM0 = W[t-2]>>61 ^ W[t-2]>>19 ^
 226                                         #        W[t-2]<<25
 227         mov     f_64, T1
 228         vpxor   %xmm2, %xmm0, %xmm0     # XMM0 = s1(W[t-2])
 229         mov     e_64, tmp0
 230         xor     g_64, T1
 231         idx = \rnd - 16
 232         vpaddq  W_t(idx), %xmm0, %xmm0  # XMM0 = s1(W[t-2]) + W[t-16]
 233         idx = \rnd - 7
 234         vmovdqu W_t(idx), %xmm1         # XMM1 = W[t-7]
 235         RORQ    tmp0, 23 # 41
 236         and     e_64, T1
 237         xor     e_64, tmp0
 238         xor     g_64, T1
 239         vpsllq  $(64-8), %xmm5, %xmm5   # XMM5 = W[t-15]<<56
 240         idx = \rnd + 1
 241         add     WK_2(idx), T1
 242         vpxor   %xmm5, %xmm6, %xmm6     # XMM6 = s0(W[t-15])
 243         RORQ    tmp0, 4 # 18
 244         vpaddq  %xmm6, %xmm0, %xmm0     # XMM0 = s1(W[t-2]) + W[t-16] + s0(W[t-15])
 245         xor     e_64, tmp0
 246         vpaddq  %xmm1, %xmm0, %xmm0     # XMM0 = W[t] = s1(W[t-2]) + W[t-7] +
 247                                         #               s0(W[t-15]) + W[t-16]
 248         mov     a_64, T2
 249         add     h_64, T1
 250         RORQ    tmp0, 14 # 14
 251         add     tmp0, T1
 252         idx = \rnd
 253         vmovdqa %xmm0, W_t(idx)         # Store W[t]
 254         vpaddq  K_t(idx), %xmm0, %xmm0  # Compute W[t]+K[t]
 255         vmovdqa %xmm0, WK_2(idx)        # Store W[t]+K[t] for next rounds
 256         mov     a_64, tmp0
 257         xor     c_64, T2
 258         and     c_64, tmp0
 259         and     b_64, T2
 260         xor     tmp0, T2
 261         mov     a_64, tmp0
 262         RORQ    tmp0, 5 # 39
 263         xor     a_64, tmp0
 264         add     T1, d_64
 265         RORQ    tmp0, 6 # 34
 266         xor     a_64, tmp0
 267         lea     (T1, T2), h_64
 268         RORQ    tmp0, 28 # 28
 269         add     tmp0, h_64
 270         RotateState
 271 .endm
 272
 273 ########################################################################
 274 # void sha512_transform_avx(void* D, const void* M, u64 L)
 275 # Purpose: Updates the SHA512 digest stored at D with the message stored in M.
 276 # The size of the message pointed to by M must be an integer multiple of SHA512
 277 # message blocks.
 278 # L is the message length in SHA512 blocks
 279 ########################################################################
 280 ENTRY(sha512_transform_avx)
 281         cmp $0, msglen
 282         je nowork
 283
 284         # Allocate Stack Space
 285         mov     %rsp, %rax
 286         sub     $frame_size, %rsp
 287         and     $~(0x20 - 1), %rsp
 288         mov     %rax, frame_RSPSAVE(%rsp)
 289
 290         # Save GPRs
 291         mov     %rbx, frame_GPRSAVE(%rsp)
 292         mov     %r12, frame_GPRSAVE +8*1(%rsp)
 293         mov     %r13, frame_GPRSAVE +8*2(%rsp)
 294         mov     %r14, frame_GPRSAVE +8*3(%rsp)
 295         mov     %r15, frame_GPRSAVE +8*4(%rsp)
 296
 297 updateblock:
 298
 299         # Load state variables
 300         mov     DIGEST(0), a_64
 301         mov     DIGEST(1), b_64
 302         mov     DIGEST(2), c_64
 303         mov     DIGEST(3), d_64
 304         mov     DIGEST(4), e_64
 305         mov     DIGEST(5), f_64
 306         mov     DIGEST(6), g_64
 307         mov     DIGEST(7), h_64
 308
 309         t = 0
 310         .rept 80/2 + 1
 311         # (80 rounds) / (2 rounds/iteration) + (1 iteration)
 312         # +1 iteration because the scheduler leads hashing by 1 iteration
 313                 .if t < 2
 314                         # BSWAP 2 QWORDS
 315                         vmovdqa  XMM_QWORD_BSWAP(%rip), %xmm1
 316                         vmovdqu  MSG(t), %xmm0
 317                         vpshufb  %xmm1, %xmm0, %xmm0    # BSWAP
 318                         vmovdqa  %xmm0, W_t(t) # Store Scheduled Pair
 319                         vpaddq   K_t(t), %xmm0, %xmm0 # Compute W[t]+K[t]
 320                         vmovdqa  %xmm0, WK_2(t) # Store into WK for rounds
 321                 .elseif t < 16
 322                         # BSWAP 2 QWORDS# Compute 2 Rounds
 323                         vmovdqu  MSG(t), %xmm0
 324                         vpshufb  %xmm1, %xmm0, %xmm0    # BSWAP
 325                         SHA512_Round t-2    # Round t-2
 326                         vmovdqa  %xmm0, W_t(t) # Store Scheduled Pair
 327                         vpaddq   K_t(t), %xmm0, %xmm0 # Compute W[t]+K[t]
 328                         SHA512_Round t-1    # Round t-1
 329                         vmovdqa  %xmm0, WK_2(t)# Store W[t]+K[t] into WK
 330                 .elseif t < 79
 331                         # Schedule 2 QWORDS# Compute 2 Rounds
 332                         SHA512_2Sched_2Round_avx t
 333                 .else
 334                         # Compute 2 Rounds
 335                         SHA512_Round t-2
 336                         SHA512_Round t-1
 337                 .endif
 338                 t = t+2
 339         .endr
 340
 341         # Update digest
 342         add     a_64, DIGEST(0)
 343         add     b_64, DIGEST(1)
 344         add     c_64, DIGEST(2)
 345         add     d_64, DIGEST(3)
 346         add     e_64, DIGEST(4)
 347         add     f_64, DIGEST(5)
 348         add     g_64, DIGEST(6)
 349         add     h_64, DIGEST(7)
 350
 351         # Advance to next message block
 352         add     $16*8, msg
 353         dec     msglen
 354         jnz     updateblock
 355
 356         # Restore GPRs
 357         mov     frame_GPRSAVE(%rsp),      %rbx
 358         mov     frame_GPRSAVE +8*1(%rsp), %r12
 359         mov     frame_GPRSAVE +8*2(%rsp), %r13
 360         mov     frame_GPRSAVE +8*3(%rsp), %r14
 361         mov     frame_GPRSAVE +8*4(%rsp), %r15
 362
 363         # Restore Stack Pointer
 364         mov     frame_RSPSAVE(%rsp), %rsp
 365
 366 nowork:
 367         ret
 368 ENDPROC(sha512_transform_avx)
 369
 370 ########################################################################
 371 ### Binary Data
 372
 373 .section        .rodata.cst16.XMM_QWORD_BSWAP, "aM", @progbits, 16
 374 .align 16
 375 # Mask for byte-swapping a couple of qwords in an XMM register using (v)pshufb.
 376 XMM_QWORD_BSWAP:
 377         .octa 0x08090a0b0c0d0e0f0001020304050607
 378
 379 # Mergeable 640-byte rodata section. This allows linker to merge the table
 380 # with other, exactly the same 640-byte fragment of another rodata section
 381 # (if such section exists).
 382 .section        .rodata.cst640.K512, "aM", @progbits, 640
 383 .align 64
 384 # K[t] used in SHA512 hashing
 385 K512:
 386         .quad 0x428a2f98d728ae22,0x7137449123ef65cd
 387         .quad 0xb5c0fbcfec4d3b2f,0xe9b5dba58189dbbc
 388         .quad 0x3956c25bf348b538,0x59f111f1b605d019
 389         .quad 0x923f82a4af194f9b,0xab1c5ed5da6d8118
 390         .quad 0xd807aa98a3030242,0x12835b0145706fbe
 391         .quad 0x243185be4ee4b28c,0x550c7dc3d5ffb4e2
 392         .quad 0x72be5d74f27b896f,0x80deb1fe3b1696b1
 393         .quad 0x9bdc06a725c71235,0xc19bf174cf692694
 394         .quad 0xe49b69c19ef14ad2,0xefbe4786384f25e3
 395         .quad 0x0fc19dc68b8cd5b5,0x240ca1cc77ac9c65
 396         .quad 0x2de92c6f592b0275,0x4a7484aa6ea6e483
 397         .quad 0x5cb0a9dcbd41fbd4,0x76f988da831153b5
 398         .quad 0x983e5152ee66dfab,0xa831c66d2db43210
 399         .quad 0xb00327c898fb213f,0xbf597fc7beef0ee4
 400         .quad 0xc6e00bf33da88fc2,0xd5a79147930aa725
 401         .quad 0x06ca6351e003826f,0x142929670a0e6e70
 402         .quad 0x27b70a8546d22ffc,0x2e1b21385c26c926
 403         .quad 0x4d2c6dfc5ac42aed,0x53380d139d95b3df
 404         .quad 0x650a73548baf63de,0x766a0abb3c77b2a8
 405         .quad 0x81c2c92e47edaee6,0x92722c851482353b
 406         .quad 0xa2bfe8a14cf10364,0xa81a664bbc423001
 407         .quad 0xc24b8b70d0f89791,0xc76c51a30654be30
 408         .quad 0xd192e819d6ef5218,0xd69906245565a910
 409         .quad 0xf40e35855771202a,0x106aa07032bbd1b8
 410         .quad 0x19a4c116b8d2d0c8,0x1e376c085141ab53
 411         .quad 0x2748774cdf8eeb99,0x34b0bcb5e19b48a8
 412         .quad 0x391c0cb3c5c95a63,0x4ed8aa4ae3418acb
 413         .quad 0x5b9cca4f7763e373,0x682e6ff3d6b2b8a3
 414         .quad 0x748f82ee5defb2fc,0x78a5636f43172f60
 415         .quad 0x84c87814a1f0ab72,0x8cc702081a6439ec
 416         .quad 0x90befffa23631e28,0xa4506cebde82bde9
 417         .quad 0xbef9a3f7b2c67915,0xc67178f2e372532b
 418         .quad 0xca273eceea26619c,0xd186b8c721c0c207
 419         .quad 0xeada7dd6cde0eb1e,0xf57d4f7fee6ed178
 420         .quad 0x06f067aa72176fba,0x0a637dc5a2c898a6
 421         .quad 0x113f9804bef90dae,0x1b710b35131c471b
 422         .quad 0x28db77f523047d84,0x32caab7b40c72493
 423         .quad 0x3c9ebe0a15c9bebc,0x431d67c49c100d4c
 424         .quad 0x4cc5d4becb3e42b6,0x597f299cfc657e2a
 425         .quad 0x5fcb6fab3ad6faec,0x6c44198c4a475817
 426 #endif