1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 1991,1992 Linus Torvalds
5 * entry_32.S contains the system-call and low-level fault and trap handling routines.
7 * Stack layout while running C code:
8 * ptrace needs to have all registers on the stack.
9 * If the order here is changed, it needs to be
10 * updated in fork.c:copy_process(), signal.c:do_signal(),
11 * ptrace.c and ptrace.h
23 * 28(%esp) - %gs saved iff !CONFIG_X86_32_LAZY_GS
32 #include <linux/linkage.h>
33 #include <linux/err.h>
34 #include <asm/thread_info.h>
35 #include <asm/irqflags.h>
36 #include <asm/errno.h>
37 #include <asm/segment.h>
39 #include <asm/percpu.h>
40 #include <asm/processor-flags.h>
41 #include <asm/irq_vectors.h>
42 #include <asm/cpufeatures.h>
43 #include <asm/alternative-asm.h>
46 #include <asm/frame.h>
47 #include <asm/trapnr.h>
48 #include <asm/nospec-branch.h>
52 .section .entry.text, "ax"
55 * We use macros for low-level operations which need to be overridden
56 * for paravirtualization. The following will never clobber any registers:
57 * INTERRUPT_RETURN (aka. "iret")
58 * GET_CR0_INTO_EAX (aka. "movl %cr0, %eax")
59 * ENABLE_INTERRUPTS_SYSEXIT (aka "sti; sysexit").
61 * For DISABLE_INTERRUPTS/ENABLE_INTERRUPTS (aka "cli"/"sti"), you must
62 * specify what registers can be overwritten (CLBR_NONE, CLBR_EAX/EDX/ECX/ANY).
63 * Allowing a register to be clobbered can shrink the paravirt replacement
64 * enough to patch inline, increasing performance.
67 #ifdef CONFIG_PREEMPTION
68 # define preempt_stop(clobbers) DISABLE_INTERRUPTS(clobbers); TRACE_IRQS_OFF
70 # define preempt_stop(clobbers)
73 .macro TRACE_IRQS_IRET
74 #ifdef CONFIG_TRACE_IRQFLAGS
75 testl $X86_EFLAGS_IF, PT_EFLAGS(%esp) # interrupts off?
82 #define PTI_SWITCH_MASK (1 << PAGE_SHIFT)
85 * User gs save/restore
87 * %gs is used for userland TLS and kernel only uses it for stack
88 * canary which is required to be at %gs:20 by gcc. Read the comment
89 * at the top of stackprotector.h for more info.
91 * Local labels 98 and 99 are used.
93 #ifdef CONFIG_X86_32_LAZY_GS
95 /* unfortunately push/pop can't be no-op */
100 addl $(4 + \pop), %esp
105 /* all the rest are no-op */
112 .macro REG_TO_PTGS reg
114 .macro SET_KERNEL_GS reg
117 #else /* CONFIG_X86_32_LAZY_GS */
130 .pushsection .fixup, "ax"
134 _ASM_EXTABLE(98b, 99b)
138 98: mov PT_GS(%esp), %gs
141 .pushsection .fixup, "ax"
142 99: movl $0, PT_GS(%esp)
145 _ASM_EXTABLE(98b, 99b)
151 .macro REG_TO_PTGS reg
152 movl \reg, PT_GS(%esp)
154 .macro SET_KERNEL_GS reg
155 movl $(__KERNEL_STACK_CANARY), \reg
159 #endif /* CONFIG_X86_32_LAZY_GS */
161 /* Unconditionally switch to user cr3 */
162 .macro SWITCH_TO_USER_CR3 scratch_reg:req
163 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
165 movl %cr3, \scratch_reg
166 orl $PTI_SWITCH_MASK, \scratch_reg
167 movl \scratch_reg, %cr3
171 .macro BUG_IF_WRONG_CR3 no_user_check=0
172 #ifdef CONFIG_DEBUG_ENTRY
173 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
174 .if \no_user_check == 0
175 /* coming from usermode? */
176 testl $USER_SEGMENT_RPL_MASK, PT_CS(%esp)
181 testl $PTI_SWITCH_MASK, %eax
183 /* From userspace with kernel cr3 - BUG */
190 * Switch to kernel cr3 if not already loaded and return current cr3 in
193 .macro SWITCH_TO_KERNEL_CR3 scratch_reg:req
194 ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI
195 movl %cr3, \scratch_reg
196 /* Test if we are already on kernel CR3 */
197 testl $PTI_SWITCH_MASK, \scratch_reg
199 andl $(~PTI_SWITCH_MASK), \scratch_reg
200 movl \scratch_reg, %cr3
201 /* Return original CR3 in \scratch_reg */
202 orl $PTI_SWITCH_MASK, \scratch_reg
206 #define CS_FROM_ENTRY_STACK (1 << 31)
207 #define CS_FROM_USER_CR3 (1 << 30)
208 #define CS_FROM_KERNEL (1 << 29)
209 #define CS_FROM_ESPFIX (1 << 28)
213 * The high bits of the CS dword (__csh) are used for CS_FROM_*.
214 * Clear them in case hardware didn't do this for us.
216 andl $0x0000ffff, 4*4(%esp)
219 testl $X86_EFLAGS_VM, 5*4(%esp)
220 jnz .Lfrom_usermode_no_fixup_\@
222 testl $USER_SEGMENT_RPL_MASK, 4*4(%esp)
223 jnz .Lfrom_usermode_no_fixup_\@
225 orl $CS_FROM_KERNEL, 4*4(%esp)
228 * When we're here from kernel mode; the (exception) stack looks like:
230 * 6*4(%esp) - <previous context>
234 * 2*4(%esp) - orig_eax
235 * 1*4(%esp) - gs / function
238 * Lets build a 5 entry IRET frame after that, such that struct pt_regs
239 * is complete and in particular regs->sp is correct. This gives us
240 * the original 6 enties as gap:
242 * 14*4(%esp) - <previous context>
243 * 13*4(%esp) - gap / flags
244 * 12*4(%esp) - gap / cs
245 * 11*4(%esp) - gap / ip
246 * 10*4(%esp) - gap / orig_eax
247 * 9*4(%esp) - gap / gs / function
248 * 8*4(%esp) - gap / fs
254 * 2*4(%esp) - orig_eax
255 * 1*4(%esp) - gs / function
260 pushl %esp # sp (points at ss)
261 addl $7*4, (%esp) # point sp back at the previous context
262 pushl 7*4(%esp) # flags
265 pushl 7*4(%esp) # orig_eax
266 pushl 7*4(%esp) # gs / function
268 .Lfrom_usermode_no_fixup_\@:
273 * We're called with %ds, %es, %fs, and %gs from the interrupted
274 * frame, so we shouldn't use them. Also, we may be in ESPFIX
275 * mode and therefore have a nonzero SS base and an offset ESP,
276 * so any attempt to access the stack needs to use SS. (except for
277 * accesses through %esp, which automatically use SS.)
279 testl $CS_FROM_KERNEL, 1*4(%esp)
280 jz .Lfinished_frame_\@
283 * Reconstruct the 3 entry IRET frame right after the (modified)
284 * regs->sp without lowering %esp in between, such that an NMI in the
285 * middle doesn't scribble our stack.
289 movl 5*4(%esp), %eax # (modified) regs->sp
291 movl 4*4(%esp), %ecx # flags
292 movl %ecx, %ss:-1*4(%eax)
294 movl 3*4(%esp), %ecx # cs
295 andl $0x0000ffff, %ecx
296 movl %ecx, %ss:-2*4(%eax)
298 movl 2*4(%esp), %ecx # ip
299 movl %ecx, %ss:-3*4(%eax)
301 movl 1*4(%esp), %ecx # eax
302 movl %ecx, %ss:-4*4(%eax)
310 .macro SAVE_ALL pt_regs_ax=%eax switch_stacks=0 skip_gs=0 unwind_espfix=0
318 movl $(__KERNEL_PERCPU), %eax
320 .if \unwind_espfix > 0
335 movl $(__USER_DS), %edx
341 /* Switch to kernel stack if necessary */
342 .if \switch_stacks > 0
343 SWITCH_TO_KERNEL_STACK
347 .macro SAVE_ALL_NMI cr3_reg:req unwind_espfix=0
348 SAVE_ALL unwind_espfix=\unwind_espfix
353 * Now switch the CR3 when PTI is enabled.
355 * We can enter with either user or kernel cr3, the code will
356 * store the old cr3 in \cr3_reg and switches to the kernel cr3
359 SWITCH_TO_KERNEL_CR3 scratch_reg=\cr3_reg
364 .macro RESTORE_INT_REGS
374 .macro RESTORE_REGS pop=0
381 .pushsection .fixup, "ax"
395 .macro RESTORE_ALL_NMI cr3_reg:req pop=0
397 * Now switch the CR3 when PTI is enabled.
399 * We enter with kernel cr3 and switch the cr3 to the value
400 * stored on \cr3_reg, which is either a user or a kernel cr3.
402 ALTERNATIVE "jmp .Lswitched_\@", "", X86_FEATURE_PTI
404 testl $PTI_SWITCH_MASK, \cr3_reg
407 /* User cr3 in \cr3_reg - write it to hardware cr3 */
414 RESTORE_REGS pop=\pop
417 .macro CHECK_AND_APPLY_ESPFIX
418 #ifdef CONFIG_X86_ESPFIX32
419 #define GDT_ESPFIX_OFFSET (GDT_ENTRY_ESPFIX_SS * 8)
420 #define GDT_ESPFIX_SS PER_CPU_VAR(gdt_page) + GDT_ESPFIX_OFFSET
422 ALTERNATIVE "jmp .Lend_\@", "", X86_BUG_ESPFIX
424 movl PT_EFLAGS(%esp), %eax # mix EFLAGS, SS and CS
426 * Warning: PT_OLDSS(%esp) contains the wrong/random values if we
427 * are returning to the kernel.
428 * See comments in process.c:copy_thread() for details.
430 movb PT_OLDSS(%esp), %ah
431 movb PT_CS(%esp), %al
432 andl $(X86_EFLAGS_VM | (SEGMENT_TI_MASK << 8) | SEGMENT_RPL_MASK), %eax
433 cmpl $((SEGMENT_LDT << 8) | USER_RPL), %eax
434 jne .Lend_\@ # returning to user-space with LDT SS
437 * Setup and switch to ESPFIX stack
439 * We're returning to userspace with a 16 bit stack. The CPU will not
440 * restore the high word of ESP for us on executing iret... This is an
441 * "official" bug of all the x86-compatible CPUs, which we can work
442 * around to make dosemu and wine happy. We do this by preloading the
443 * high word of ESP with the high word of the userspace ESP while
444 * compensating for the offset by changing to the ESPFIX segment with
445 * a base address that matches for the difference.
447 mov %esp, %edx /* load kernel esp */
448 mov PT_OLDESP(%esp), %eax /* load userspace esp */
449 mov %dx, %ax /* eax: new kernel esp */
450 sub %eax, %edx /* offset (low word is 0) */
452 mov %dl, GDT_ESPFIX_SS + 4 /* bits 16..23 */
453 mov %dh, GDT_ESPFIX_SS + 7 /* bits 24..31 */
455 pushl %eax /* new kernel esp */
457 * Disable interrupts, but do not irqtrace this section: we
458 * will soon execute iret and the tracer was already set to
459 * the irqstate after the IRET:
461 DISABLE_INTERRUPTS(CLBR_ANY)
462 lss (%esp), %esp /* switch to espfix segment */
464 #endif /* CONFIG_X86_ESPFIX32 */
468 * Called with pt_regs fully populated and kernel segments loaded,
469 * so we can access PER_CPU and use the integer registers.
471 * We need to be very careful here with the %esp switch, because an NMI
472 * can happen everywhere. If the NMI handler finds itself on the
473 * entry-stack, it will overwrite the task-stack and everything we
474 * copied there. So allocate the stack-frame on the task-stack and
475 * switch to it before we do any copying.
478 .macro SWITCH_TO_KERNEL_STACK
480 ALTERNATIVE "", "jmp .Lend_\@", X86_FEATURE_XENPV
484 SWITCH_TO_KERNEL_CR3 scratch_reg=%eax
487 * %eax now contains the entry cr3 and we carry it forward in
488 * that register for the time this macro runs
491 /* Are we on the entry stack? Bail out if not! */
492 movl PER_CPU_VAR(cpu_entry_area), %ecx
493 addl $CPU_ENTRY_AREA_entry_stack + SIZEOF_entry_stack, %ecx
494 subl %esp, %ecx /* ecx = (end of entry_stack) - esp */
495 cmpl $SIZEOF_entry_stack, %ecx
498 /* Load stack pointer into %esi and %edi */
502 /* Move %edi to the top of the entry stack */
503 andl $(MASK_entry_stack), %edi
504 addl $(SIZEOF_entry_stack), %edi
506 /* Load top of task-stack into %edi */
507 movl TSS_entry2task_stack(%edi), %edi
509 /* Special case - entry from kernel mode via entry stack */
511 movl PT_EFLAGS(%esp), %ecx # mix EFLAGS and CS
512 movb PT_CS(%esp), %cl
513 andl $(X86_EFLAGS_VM | SEGMENT_RPL_MASK), %ecx
515 movl PT_CS(%esp), %ecx
516 andl $SEGMENT_RPL_MASK, %ecx
519 jb .Lentry_from_kernel_\@
522 movl $PTREGS_SIZE, %ecx
525 testl $X86_EFLAGS_VM, PT_EFLAGS(%esi)
529 * Stack-frame contains 4 additional segment registers when
530 * coming from VM86 mode
537 /* Allocate frame on task-stack */
540 /* Switch to task-stack */
544 * We are now on the task-stack and can safely copy over the
553 .Lentry_from_kernel_\@:
556 * This handles the case when we enter the kernel from
557 * kernel-mode and %esp points to the entry-stack. When this
558 * happens we need to switch to the task-stack to run C code,
559 * but switch back to the entry-stack again when we approach
560 * iret and return to the interrupted code-path. This usually
561 * happens when we hit an exception while restoring user-space
562 * segment registers on the way back to user-space or when the
563 * sysenter handler runs with eflags.tf set.
565 * When we switch to the task-stack here, we can't trust the
566 * contents of the entry-stack anymore, as the exception handler
567 * might be scheduled out or moved to another CPU. Therefore we
568 * copy the complete entry-stack to the task-stack and set a
569 * marker in the iret-frame (bit 31 of the CS dword) to detect
570 * what we've done on the iret path.
572 * On the iret path we copy everything back and switch to the
573 * entry-stack, so that the interrupted kernel code-path
574 * continues on the same stack it was interrupted with.
576 * Be aware that an NMI can happen anytime in this code.
578 * %esi: Entry-Stack pointer (same as %esp)
579 * %edi: Top of the task stack
580 * %eax: CR3 on kernel entry
583 /* Calculate number of bytes on the entry stack in %ecx */
586 /* %ecx to the top of entry-stack */
587 andl $(MASK_entry_stack), %ecx
588 addl $(SIZEOF_entry_stack), %ecx
590 /* Number of bytes on the entry stack to %ecx */
593 /* Mark stackframe as coming from entry stack */
594 orl $CS_FROM_ENTRY_STACK, PT_CS(%esp)
597 * Test the cr3 used to enter the kernel and add a marker
598 * so that we can switch back to it before iret.
600 testl $PTI_SWITCH_MASK, %eax
602 orl $CS_FROM_USER_CR3, PT_CS(%esp)
605 * %esi and %edi are unchanged, %ecx contains the number of
606 * bytes to copy. The code at .Lcopy_pt_regs_\@ will allocate
607 * the stack-frame on task-stack and copy everything over
609 jmp .Lcopy_pt_regs_\@
615 * Switch back from the kernel stack to the entry stack.
617 * The %esp register must point to pt_regs on the task stack. It will
618 * first calculate the size of the stack-frame to copy, depending on
619 * whether we return to VM86 mode or not. With that it uses 'rep movsl'
620 * to copy the contents of the stack over to the entry stack.
622 * We must be very careful here, as we can't trust the contents of the
623 * task-stack once we switched to the entry-stack. When an NMI happens
624 * while on the entry-stack, the NMI handler will switch back to the top
625 * of the task stack, overwriting our stack-frame we are about to copy.
626 * Therefore we switch the stack only after everything is copied over.
628 .macro SWITCH_TO_ENTRY_STACK
630 ALTERNATIVE "", "jmp .Lend_\@", X86_FEATURE_XENPV
633 movl $PTREGS_SIZE, %ecx
636 testl $(X86_EFLAGS_VM), PT_EFLAGS(%esp)
639 /* Additional 4 registers to copy when returning to VM86 mode */
645 /* Initialize source and destination for movsl */
646 movl PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %edi
650 /* Save future stack pointer in %ebx */
653 /* Copy over the stack-frame */
659 * Switch to entry-stack - needs to happen after everything is
660 * copied because the NMI handler will overwrite the task-stack
661 * when on entry-stack
669 * This macro handles the case when we return to kernel-mode on the iret
670 * path and have to switch back to the entry stack and/or user-cr3
672 * See the comments below the .Lentry_from_kernel_\@ label in the
673 * SWITCH_TO_KERNEL_STACK macro for more details.
675 .macro PARANOID_EXIT_TO_KERNEL_MODE
678 * Test if we entered the kernel with the entry-stack. Most
679 * likely we did not, because this code only runs on the
680 * return-to-kernel path.
682 testl $CS_FROM_ENTRY_STACK, PT_CS(%esp)
685 /* Unlikely slow-path */
687 /* Clear marker from stack-frame */
688 andl $(~CS_FROM_ENTRY_STACK), PT_CS(%esp)
690 /* Copy the remaining task-stack contents to entry-stack */
692 movl PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %edi
694 /* Bytes on the task-stack to ecx */
695 movl PER_CPU_VAR(cpu_tss_rw + TSS_sp1), %ecx
698 /* Allocate stack-frame on entry-stack */
702 * Save future stack-pointer, we must not switch until the
703 * copy is done, otherwise the NMI handler could destroy the
704 * contents of the task-stack we are about to copy.
713 /* Safe to switch to entry-stack now */
717 * We came from entry-stack and need to check if we also need to
718 * switch back to user cr3.
720 testl $CS_FROM_USER_CR3, PT_CS(%esp)
723 /* Clear marker from stack-frame */
724 andl $(~CS_FROM_USER_CR3), PT_CS(%esp)
726 SWITCH_TO_USER_CR3 scratch_reg=%eax
732 * idtentry - Macro to generate entry stubs for simple IDT entries
733 * @vector: Vector number
734 * @asmsym: ASM symbol for the entry point
735 * @cfunc: C function to be called
736 * @has_error_code: Hardware pushed error code on stack
737 * @sane: Compatibility flag with 64bit
739 .macro idtentry vector asmsym cfunc has_error_code:req sane=0
740 SYM_CODE_START(\asmsym)
744 .if \has_error_code == 0
745 pushl $0 /* Clear the error code */
748 /* Push the C-function address into the GS slot */
750 /* Invoke the common exception entry */
752 SYM_CODE_END(\asmsym)
756 * Include the defines which emit the idt entries which are shared
757 * shared between 32 and 64 bit.
759 #include <asm/idtentry.h>
765 .pushsection .text, "ax"
766 SYM_CODE_START(__switch_to_asm)
768 * Save callee-saved registers
769 * This must match the order in struct inactive_task_frame
776 * Flags are saved to prevent AC leakage. This could go
777 * away if objtool would have 32bit support to verify
778 * the STAC/CLAC correctness.
783 movl %esp, TASK_threadsp(%eax)
784 movl TASK_threadsp(%edx), %esp
786 #ifdef CONFIG_STACKPROTECTOR
787 movl TASK_stack_canary(%edx), %ebx
788 movl %ebx, PER_CPU_VAR(stack_canary)+stack_canary_offset
791 #ifdef CONFIG_RETPOLINE
793 * When switching from a shallower to a deeper call stack
794 * the RSB may either underflow or use entries populated
795 * with userspace addresses. On CPUs where those concerns
796 * exist, overwrite the RSB with entries which capture
797 * speculative execution to prevent attack.
799 FILL_RETURN_BUFFER %ebx, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW
802 /* Restore flags or the incoming task to restore AC state. */
804 /* restore callee-saved registers */
811 SYM_CODE_END(__switch_to_asm)
815 * The unwinder expects the last frame on the stack to always be at the same
816 * offset from the end of the page, which allows it to validate the stack.
817 * Calling schedule_tail() directly would break that convention because its an
818 * asmlinkage function so its argument has to be pushed on the stack. This
819 * wrapper creates a proper "end of stack" frame header before the call.
821 .pushsection .text, "ax"
822 SYM_FUNC_START(schedule_tail_wrapper)
831 SYM_FUNC_END(schedule_tail_wrapper)
835 * A newly forked process directly context switches into this address.
837 * eax: prev task we switched from
838 * ebx: kernel thread func (NULL for user thread)
839 * edi: kernel thread arg
841 .pushsection .text, "ax"
842 SYM_CODE_START(ret_from_fork)
843 call schedule_tail_wrapper
846 jnz 1f /* kernel threads are uncommon */
849 /* When we fork, we trace the syscall return in the child, too. */
851 call syscall_return_slowpath
852 jmp .Lsyscall_32_done
858 * A kernel thread is allowed to return here after successfully
859 * calling do_execve(). Exit to userspace to complete the execve()
862 movl $0, PT_EAX(%esp)
864 SYM_CODE_END(ret_from_fork)
868 * Return to user mode is not as complex as all this looks,
869 * but we want the default path for a system call return to
870 * go as quickly as possible which is why some of this is
871 * less clear than it otherwise should be.
874 # userspace resumption stub bypassing syscall exit tracing
875 SYM_CODE_START_LOCAL(ret_from_exception)
876 preempt_stop(CLBR_ANY)
879 movl PT_EFLAGS(%esp), %eax # mix EFLAGS and CS
880 movb PT_CS(%esp), %al
881 andl $(X86_EFLAGS_VM | SEGMENT_RPL_MASK), %eax
884 * We can be coming here from child spawned by kernel_thread().
886 movl PT_CS(%esp), %eax
887 andl $SEGMENT_RPL_MASK, %eax
890 jb restore_all_kernel # not returning to v8086 or userspace
892 DISABLE_INTERRUPTS(CLBR_ANY)
895 call prepare_exit_to_usermode
896 jmp restore_all_switch_stack
897 SYM_CODE_END(ret_from_exception)
899 SYM_ENTRY(__begin_SYSENTER_singlestep_region, SYM_L_GLOBAL, SYM_A_NONE)
901 * All code from here through __end_SYSENTER_singlestep_region is subject
902 * to being single-stepped if a user program sets TF and executes SYSENTER.
903 * There is absolutely nothing that we can do to prevent this from happening
904 * (thanks Intel!). To keep our handling of this situation as simple as
905 * possible, we handle TF just like AC and NT, except that our #DB handler
906 * will ignore all of the single-step traps generated in this range.
911 * Xen doesn't set %esp to be precisely what the normal SYSENTER
912 * entry point expects, so fix it up before using the normal path.
914 SYM_CODE_START(xen_sysenter_target)
915 addl $5*4, %esp /* remove xen-provided frame */
916 jmp .Lsysenter_past_esp
917 SYM_CODE_END(xen_sysenter_target)
921 * 32-bit SYSENTER entry.
923 * 32-bit system calls through the vDSO's __kernel_vsyscall enter here
924 * if X86_FEATURE_SEP is available. This is the preferred system call
925 * entry on 32-bit systems.
927 * The SYSENTER instruction, in principle, should *only* occur in the
928 * vDSO. In practice, a small number of Android devices were shipped
929 * with a copy of Bionic that inlined a SYSENTER instruction. This
930 * never happened in any of Google's Bionic versions -- it only happened
931 * in a narrow range of Intel-provided versions.
933 * SYSENTER loads SS, ESP, CS, and EIP from previously programmed MSRs.
934 * IF and VM in RFLAGS are cleared (IOW: interrupts are off).
935 * SYSENTER does not save anything on the stack,
936 * and does not save old EIP (!!!), ESP, or EFLAGS.
938 * To avoid losing track of EFLAGS.VM (and thus potentially corrupting
939 * user and/or vm86 state), we explicitly disable the SYSENTER
940 * instruction in vm86 mode by reprogramming the MSRs.
943 * eax system call number
952 SYM_FUNC_START(entry_SYSENTER_32)
954 * On entry-stack with all userspace-regs live - save and
955 * restore eflags and %eax to use it as scratch-reg for the cr3
960 BUG_IF_WRONG_CR3 no_user_check=1
961 SWITCH_TO_KERNEL_CR3 scratch_reg=%eax
965 /* Stack empty again, switch to task stack */
966 movl TSS_entry2task_stack(%esp), %esp
969 pushl $__USER_DS /* pt_regs->ss */
970 pushl %ebp /* pt_regs->sp (stashed in bp) */
971 pushfl /* pt_regs->flags (except IF = 0) */
972 orl $X86_EFLAGS_IF, (%esp) /* Fix IF */
973 pushl $__USER_CS /* pt_regs->cs */
974 pushl $0 /* pt_regs->ip = 0 (placeholder) */
975 pushl %eax /* pt_regs->orig_ax */
976 SAVE_ALL pt_regs_ax=$-ENOSYS /* save rest, stack already switched */
979 * SYSENTER doesn't filter flags, so we need to clear NT, AC
980 * and TF ourselves. To save a few cycles, we can check whether
981 * either was set instead of doing an unconditional popfq.
982 * This needs to happen before enabling interrupts so that
983 * we don't get preempted with NT set.
985 * If TF is set, we will single-step all the way to here -- do_debug
986 * will ignore all the traps. (Yes, this is slow, but so is
987 * single-stepping in general. This allows us to avoid having
988 * a more complicated code to handle the case where a user program
989 * forces us to single-step through the SYSENTER entry code.)
991 * NB.: .Lsysenter_fix_flags is a label with the code under it moved
992 * out-of-line as an optimization: NT is unlikely to be set in the
993 * majority of the cases and instead of polluting the I$ unnecessarily,
994 * we're keeping that code behind a branch which will predict as
995 * not-taken and therefore its instructions won't be fetched.
997 testl $X86_EFLAGS_NT|X86_EFLAGS_AC|X86_EFLAGS_TF, PT_EFLAGS(%esp)
998 jnz .Lsysenter_fix_flags
999 .Lsysenter_flags_fixed:
1002 call do_fast_syscall_32
1003 /* XEN PV guests always use IRET path */
1004 ALTERNATIVE "testl %eax, %eax; jz .Lsyscall_32_done", \
1005 "jmp .Lsyscall_32_done", X86_FEATURE_XENPV
1009 /* Opportunistic SYSEXIT */
1012 * Setup entry stack - we keep the pointer in %eax and do the
1013 * switch after almost all user-state is restored.
1016 /* Load entry stack pointer and allocate frame for eflags/eax */
1017 movl PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %eax
1020 /* Copy eflags and eax to entry stack */
1021 movl PT_EFLAGS(%esp), %edi
1022 movl PT_EAX(%esp), %esi
1026 /* Restore user registers and segments */
1027 movl PT_EIP(%esp), %edx /* pt_regs->ip */
1028 movl PT_OLDESP(%esp), %ecx /* pt_regs->sp */
1029 1: mov PT_FS(%esp), %fs
1032 popl %ebx /* pt_regs->bx */
1033 addl $2*4, %esp /* skip pt_regs->cx and pt_regs->dx */
1034 popl %esi /* pt_regs->si */
1035 popl %edi /* pt_regs->di */
1036 popl %ebp /* pt_regs->bp */
1038 /* Switch to entry stack */
1041 /* Now ready to switch the cr3 */
1042 SWITCH_TO_USER_CR3 scratch_reg=%eax
1045 * Restore all flags except IF. (We restore IF separately because
1046 * STI gives a one-instruction window in which we won't be interrupted,
1047 * whereas POPF does not.)
1049 btrl $X86_EFLAGS_IF_BIT, (%esp)
1050 BUG_IF_WRONG_CR3 no_user_check=1
1055 * Return back to the vDSO, which will pop ecx and edx.
1056 * Don't bother with DS and ES (they already contain __USER_DS).
1061 .pushsection .fixup, "ax"
1062 2: movl $0, PT_FS(%esp)
1065 _ASM_EXTABLE(1b, 2b)
1068 .Lsysenter_fix_flags:
1069 pushl $X86_EFLAGS_FIXED
1071 jmp .Lsysenter_flags_fixed
1072 SYM_ENTRY(__end_SYSENTER_singlestep_region, SYM_L_GLOBAL, SYM_A_NONE)
1073 SYM_FUNC_END(entry_SYSENTER_32)
1076 * 32-bit legacy system call entry.
1078 * 32-bit x86 Linux system calls traditionally used the INT $0x80
1079 * instruction. INT $0x80 lands here.
1081 * This entry point can be used by any 32-bit perform system calls.
1082 * Instances of INT $0x80 can be found inline in various programs and
1083 * libraries. It is also used by the vDSO's __kernel_vsyscall
1084 * fallback for hardware that doesn't support a faster entry method.
1085 * Restarted 32-bit system calls also fall back to INT $0x80
1086 * regardless of what instruction was originally used to do the system
1087 * call. (64-bit programs can use INT $0x80 as well, but they can
1088 * only run on 64-bit kernels and therefore land in
1089 * entry_INT80_compat.)
1091 * This is considered a slow path. It is not used by most libc
1092 * implementations on modern hardware except during process startup.
1095 * eax system call number
1103 SYM_FUNC_START(entry_INT80_32)
1105 pushl %eax /* pt_regs->orig_ax */
1107 SAVE_ALL pt_regs_ax=$-ENOSYS switch_stacks=1 /* save rest */
1110 call do_int80_syscall_32
1114 restore_all_switch_stack:
1115 SWITCH_TO_ENTRY_STACK
1116 CHECK_AND_APPLY_ESPFIX
1118 /* Switch back to user CR3 */
1119 SWITCH_TO_USER_CR3 scratch_reg=%eax
1123 /* Restore user state */
1124 RESTORE_REGS pop=4 # skip orig_eax/error_code
1127 * ARCH_HAS_MEMBARRIER_SYNC_CORE rely on IRET core serialization
1128 * when returning from IPI handler and when returning from
1129 * scheduler to user-space.
1134 #ifdef CONFIG_PREEMPTION
1135 DISABLE_INTERRUPTS(CLBR_ANY)
1136 cmpl $0, PER_CPU_VAR(__preempt_count)
1138 testl $X86_EFLAGS_IF, PT_EFLAGS(%esp) # interrupts off (exception path) ?
1140 call preempt_schedule_irq
1144 PARANOID_EXIT_TO_KERNEL_MODE
1149 .section .fixup, "ax"
1150 SYM_CODE_START(iret_exc)
1151 pushl $0 # no error code
1152 pushl $do_iret_error
1154 #ifdef CONFIG_DEBUG_ENTRY
1156 * The stack-frame here is the one that iret faulted on, so its a
1157 * return-to-user frame. We are on kernel-cr3 because we come here from
1158 * the fixup code. This confuses the CR3 checker, so switch to user-cr3
1159 * as the checker expects it.
1162 SWITCH_TO_USER_CR3 scratch_reg=%eax
1166 jmp common_exception
1167 SYM_CODE_END(iret_exc)
1169 _ASM_EXTABLE(.Lirq_return, iret_exc)
1170 SYM_FUNC_END(entry_INT80_32)
1172 .macro FIXUP_ESPFIX_STACK
1174 * Switch back for ESPFIX stack to the normal zerobased stack
1176 * We can't call C functions using the ESPFIX stack. This code reads
1177 * the high word of the segment base from the GDT and swiches to the
1178 * normal stack and adjusts ESP with the matching offset.
1180 * We might be on user CR3 here, so percpu data is not mapped and we can't
1181 * access the GDT through the percpu segment. Instead, use SGDT to find
1182 * the cpu_entry_area alias of the GDT.
1184 #ifdef CONFIG_X86_ESPFIX32
1185 /* fixup the stack */
1189 movl 2(%esp), %ecx /* GDT address */
1191 * Careful: ECX is a linear pointer, so we need to force base
1192 * zero. %cs is the only known-linear segment we have right now.
1194 mov %cs:GDT_ESPFIX_OFFSET + 4(%ecx), %al /* bits 16..23 */
1195 mov %cs:GDT_ESPFIX_OFFSET + 7(%ecx), %ah /* bits 24..31 */
1199 addl %esp, %eax /* the adjusted stack pointer */
1202 lss (%esp), %esp /* switch to the normal stack segment */
1206 .macro UNWIND_ESPFIX_STACK
1207 /* It's safe to clobber %eax, all other regs need to be preserved */
1208 #ifdef CONFIG_X86_ESPFIX32
1210 /* see if on espfix stack */
1211 cmpw $__ESPFIX_SS, %ax
1213 /* switch to normal stack */
1220 * Build the entry stubs with some assembler magic.
1221 * We pack 1 stub into every 8-byte block.
1224 SYM_CODE_START(irq_entries_start)
1225 vector=FIRST_EXTERNAL_VECTOR
1226 .rept (FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR)
1227 pushl $(~vector+0x80) /* Note: always in signed byte range */
1229 jmp common_interrupt
1232 SYM_CODE_END(irq_entries_start)
1234 #ifdef CONFIG_X86_LOCAL_APIC
1236 SYM_CODE_START(spurious_entries_start)
1237 vector=FIRST_SYSTEM_VECTOR
1238 .rept (NR_VECTORS - FIRST_SYSTEM_VECTOR)
1239 pushl $(~vector+0x80) /* Note: always in signed byte range */
1244 SYM_CODE_END(spurious_entries_start)
1246 SYM_CODE_START_LOCAL(common_spurious)
1248 addl $-0x80, (%esp) /* Adjust vector into the [-256, -1] range */
1249 SAVE_ALL switch_stacks=1
1250 ENCODE_FRAME_POINTER
1253 call smp_spurious_interrupt
1255 SYM_CODE_END(common_spurious)
1259 * the CPU automatically disables interrupts when executing an IRQ vector,
1260 * so IRQ-flags tracing has to follow that:
1262 .p2align CONFIG_X86_L1_CACHE_SHIFT
1263 SYM_CODE_START_LOCAL(common_interrupt)
1265 addl $-0x80, (%esp) /* Adjust vector into the [-256, -1] range */
1267 SAVE_ALL switch_stacks=1
1268 ENCODE_FRAME_POINTER
1273 SYM_CODE_END(common_interrupt)
1275 #define BUILD_INTERRUPT3(name, nr, fn) \
1276 SYM_FUNC_START(name) \
1279 SAVE_ALL switch_stacks=1; \
1280 ENCODE_FRAME_POINTER; \
1284 jmp ret_from_intr; \
1287 #define BUILD_INTERRUPT(name, nr) \
1288 BUILD_INTERRUPT3(name, nr, smp_##name); \
1290 /* The include is where all of the SMP etc. interrupts come from */
1291 #include <asm/entry_arch.h>
1293 SYM_CODE_START(coprocessor_error)
1296 pushl $do_coprocessor_error
1297 jmp common_exception
1298 SYM_CODE_END(coprocessor_error)
1300 SYM_CODE_START(simd_coprocessor_error)
1303 #ifdef CONFIG_X86_INVD_BUG
1304 /* AMD 486 bug: invd from userspace calls exception 19 instead of #GP */
1305 ALTERNATIVE "pushl $do_general_protection", \
1306 "pushl $do_simd_coprocessor_error", \
1309 pushl $do_simd_coprocessor_error
1311 jmp common_exception
1312 SYM_CODE_END(simd_coprocessor_error)
1314 SYM_CODE_START(device_not_available)
1317 pushl $do_device_not_available
1318 jmp common_exception
1319 SYM_CODE_END(device_not_available)
1321 #ifdef CONFIG_PARAVIRT
1322 SYM_CODE_START(native_iret)
1324 _ASM_EXTABLE(native_iret, iret_exc)
1325 SYM_CODE_END(native_iret)
1328 SYM_CODE_START(invalid_op)
1331 pushl $do_invalid_op
1332 jmp common_exception
1333 SYM_CODE_END(invalid_op)
1335 SYM_CODE_START(coprocessor_segment_overrun)
1338 pushl $do_coprocessor_segment_overrun
1339 jmp common_exception
1340 SYM_CODE_END(coprocessor_segment_overrun)
1342 SYM_CODE_START(invalid_TSS)
1344 pushl $do_invalid_TSS
1345 jmp common_exception
1346 SYM_CODE_END(invalid_TSS)
1348 SYM_CODE_START(segment_not_present)
1350 pushl $do_segment_not_present
1351 jmp common_exception
1352 SYM_CODE_END(segment_not_present)
1354 SYM_CODE_START(stack_segment)
1356 pushl $do_stack_segment
1357 jmp common_exception
1358 SYM_CODE_END(stack_segment)
1360 SYM_CODE_START(alignment_check)
1362 pushl $do_alignment_check
1363 jmp common_exception
1364 SYM_CODE_END(alignment_check)
1366 #ifdef CONFIG_X86_MCE
1367 SYM_CODE_START(machine_check)
1371 jmp common_exception
1372 SYM_CODE_END(machine_check)
1375 SYM_CODE_START(spurious_interrupt_bug)
1378 pushl $do_spurious_interrupt_bug
1379 jmp common_exception
1380 SYM_CODE_END(spurious_interrupt_bug)
1382 #ifdef CONFIG_XEN_PV
1383 SYM_FUNC_START(xen_hypervisor_callback)
1385 * Check to see if we got the event in the critical
1386 * region in xen_iret_direct, after we've reenabled
1387 * events and checked for pending events. This simulates
1388 * iret instruction's behaviour where it delivers a
1389 * pending interrupt when enabling interrupts:
1391 cmpl $xen_iret_start_crit, (%esp)
1393 cmpl $xen_iret_end_crit, (%esp)
1395 call xen_iret_crit_fixup
1397 pushl $-1 /* orig_ax = -1 => not a system call */
1399 ENCODE_FRAME_POINTER
1402 call xen_evtchn_do_upcall
1403 #ifndef CONFIG_PREEMPTION
1404 call xen_maybe_preempt_hcall
1407 SYM_FUNC_END(xen_hypervisor_callback)
1410 * Hypervisor uses this for application faults while it executes.
1411 * We get here for two reasons:
1412 * 1. Fault while reloading DS, ES, FS or GS
1413 * 2. Fault while executing IRET
1414 * Category 1 we fix up by reattempting the load, and zeroing the segment
1415 * register if the load fails.
1416 * Category 2 we fix up by jumping to do_iret_error. We cannot use the
1417 * normal Linux return path in this case because if we use the IRET hypercall
1418 * to pop the stack frame we end up in an infinite loop of failsafe callbacks.
1419 * We distinguish between categories by maintaining a status value in EAX.
1421 SYM_FUNC_START(xen_failsafe_callback)
1426 3: mov 12(%esp), %fs
1427 4: mov 16(%esp), %gs
1428 /* EAX == 0 => Category 1 (Bad segment)
1429 EAX != 0 => Category 2 (Bad IRET) */
1435 5: pushl $-1 /* orig_ax = -1 => not a system call */
1437 ENCODE_FRAME_POINTER
1438 jmp ret_from_exception
1440 .section .fixup, "ax"
1454 _ASM_EXTABLE(1b, 6b)
1455 _ASM_EXTABLE(2b, 7b)
1456 _ASM_EXTABLE(3b, 8b)
1457 _ASM_EXTABLE(4b, 9b)
1458 SYM_FUNC_END(xen_failsafe_callback)
1459 #endif /* CONFIG_XEN_PV */
1461 #ifdef CONFIG_XEN_PVHVM
1462 BUILD_INTERRUPT3(xen_hvm_callback_vector, HYPERVISOR_CALLBACK_VECTOR,
1463 xen_evtchn_do_upcall)
1467 #if IS_ENABLED(CONFIG_HYPERV)
1469 BUILD_INTERRUPT3(hyperv_callback_vector, HYPERVISOR_CALLBACK_VECTOR,
1470 hyperv_vector_handler)
1472 BUILD_INTERRUPT3(hyperv_reenlightenment_vector, HYPERV_REENLIGHTENMENT_VECTOR,
1473 hyperv_reenlightenment_intr)
1475 BUILD_INTERRUPT3(hv_stimer0_callback_vector, HYPERV_STIMER0_VECTOR,
1476 hv_stimer0_vector_handler)
1478 #endif /* CONFIG_HYPERV */
1480 SYM_CODE_START(page_fault)
1482 pushl $do_page_fault
1483 jmp common_exception_read_cr2
1484 SYM_CODE_END(page_fault)
1486 SYM_CODE_START_LOCAL_NOALIGN(common_exception_read_cr2)
1487 /* the function address is in %gs's slot on the stack */
1488 SAVE_ALL switch_stacks=1 skip_gs=1 unwind_espfix=1
1490 ENCODE_FRAME_POINTER
1494 movl PT_GS(%esp), %edi
1498 GET_CR2_INTO(%ecx) # might clobber %eax
1500 /* fixup orig %eax */
1501 movl PT_ORIG_EAX(%esp), %edx # get the error code
1502 movl $-1, PT_ORIG_EAX(%esp) # no syscall to restart
1505 movl %esp, %eax # pt_regs pointer
1507 jmp ret_from_exception
1508 SYM_CODE_END(common_exception_read_cr2)
1510 SYM_CODE_START_LOCAL_NOALIGN(common_exception)
1511 /* the function address is in %gs's slot on the stack */
1512 SAVE_ALL switch_stacks=1 skip_gs=1 unwind_espfix=1
1513 ENCODE_FRAME_POINTER
1517 movl PT_GS(%esp), %edi # get the function address
1521 /* fixup orig %eax */
1522 movl PT_ORIG_EAX(%esp), %edx # get the error code
1523 movl $-1, PT_ORIG_EAX(%esp) # no syscall to restart
1526 movl %esp, %eax # pt_regs pointer
1528 jmp ret_from_exception
1529 SYM_CODE_END(common_exception)
1531 SYM_CODE_START_LOCAL_NOALIGN(handle_exception)
1532 /* the function address is in %gs's slot on the stack */
1533 SAVE_ALL switch_stacks=1 skip_gs=1 unwind_espfix=1
1534 ENCODE_FRAME_POINTER
1538 movl PT_GS(%esp), %edi # get the function address
1542 /* fixup orig %eax */
1543 movl PT_ORIG_EAX(%esp), %edx # get the error code
1544 movl $-1, PT_ORIG_EAX(%esp) # no syscall to restart
1546 movl %esp, %eax # pt_regs pointer
1550 movl PT_EFLAGS(%esp), %eax # mix EFLAGS and CS
1551 movb PT_CS(%esp), %al
1552 andl $(X86_EFLAGS_VM | SEGMENT_RPL_MASK), %eax
1555 * We can be coming here from child spawned by kernel_thread().
1557 movl PT_CS(%esp), %eax
1558 andl $SEGMENT_RPL_MASK, %eax
1560 cmpl $USER_RPL, %eax # returning to v8086 or userspace ?
1563 PARANOID_EXIT_TO_KERNEL_MODE
1570 jmp restore_all_switch_stack
1571 SYM_CODE_END(handle_exception)
1573 SYM_CODE_START(debug)
1575 * Entry from sysenter is now handled in common_exception
1580 jmp common_exception
1583 SYM_CODE_START(double_fault)
1586 * This is a task gate handler, not an interrupt gate handler.
1587 * The error code is on the stack, but the stack is otherwise
1588 * empty. Interrupts are off. Our state is sane with the following
1591 * - CR0.TS is set. "TS" literally means "task switched".
1592 * - EFLAGS.NT is set because we're a "nested task".
1593 * - The doublefault TSS has back_link set and has been marked busy.
1594 * - TR points to the doublefault TSS and the normal TSS is busy.
1595 * - CR3 is the normal kernel PGD. This would be delightful, except
1596 * that the CPU didn't bother to save the old CR3 anywhere. This
1597 * would make it very awkward to return back to the context we came
1600 * The rest of EFLAGS is sanitized for us, so we don't need to
1601 * worry about AC or DF.
1603 * Don't even bother popping the error code. It's always zero,
1604 * and ignoring it makes us a bit more robust against buggy
1605 * hypervisor task gate implementations.
1607 * We will manually undo the task switch instead of doing a
1608 * task-switching IRET.
1611 clts /* clear CR0.TS */
1612 pushl $X86_EFLAGS_FIXED
1613 popfl /* clear EFLAGS.NT */
1615 call doublefault_shim
1617 /* We don't support returning, so we have no IRET here. */
1621 SYM_CODE_END(double_fault)
1624 * NMI is doubly nasty. It can happen on the first instruction of
1625 * entry_SYSENTER_32 (just like #DB), but it can also interrupt the beginning
1626 * of the #DB handler even if that #DB in turn hit before entry_SYSENTER_32
1627 * switched stacks. We handle both conditions by simply checking whether we
1628 * interrupted kernel code running on the SYSENTER stack.
1633 #ifdef CONFIG_X86_ESPFIX32
1635 * ESPFIX_SS is only ever set on the return to user path
1636 * after we've switched to the entry stack.
1640 cmpw $__ESPFIX_SS, %ax
1642 je .Lnmi_espfix_stack
1645 pushl %eax # pt_regs->orig_ax
1646 SAVE_ALL_NMI cr3_reg=%edi
1647 ENCODE_FRAME_POINTER
1648 xorl %edx, %edx # zero error code
1649 movl %esp, %eax # pt_regs pointer
1651 /* Are we currently on the SYSENTER stack? */
1652 movl PER_CPU_VAR(cpu_entry_area), %ecx
1653 addl $CPU_ENTRY_AREA_entry_stack + SIZEOF_entry_stack, %ecx
1654 subl %eax, %ecx /* ecx = (end of entry_stack) - esp */
1655 cmpl $SIZEOF_entry_stack, %ecx
1656 jb .Lnmi_from_sysenter_stack
1658 /* Not on SYSENTER stack. */
1662 .Lnmi_from_sysenter_stack:
1664 * We're on the SYSENTER stack. Switch off. No one (not even debug)
1665 * is using the thread stack right now, so it's safe for us to use it.
1668 movl PER_CPU_VAR(cpu_current_top_of_stack), %esp
1673 #ifdef CONFIG_X86_ESPFIX32
1674 testl $CS_FROM_ESPFIX, PT_CS(%esp)
1675 jnz .Lnmi_from_espfix
1678 CHECK_AND_APPLY_ESPFIX
1679 RESTORE_ALL_NMI cr3_reg=%edi pop=4
1682 #ifdef CONFIG_X86_ESPFIX32
1685 * Create the pointer to LSS back
1691 /* Copy the (short) IRET frame */
1692 pushl 4*4(%esp) # flags
1693 pushl 4*4(%esp) # cs
1694 pushl 4*4(%esp) # ip
1696 pushl %eax # orig_ax
1698 SAVE_ALL_NMI cr3_reg=%edi unwind_espfix=1
1699 ENCODE_FRAME_POINTER
1701 /* clear CS_FROM_KERNEL, set CS_FROM_ESPFIX */
1702 xorl $(CS_FROM_ESPFIX | CS_FROM_KERNEL), PT_CS(%esp)
1704 xorl %edx, %edx # zero error code
1705 movl %esp, %eax # pt_regs pointer
1706 jmp .Lnmi_from_sysenter_stack
1709 RESTORE_ALL_NMI cr3_reg=%edi
1711 * Because we cleared CS_FROM_KERNEL, IRET_FRAME 'forgot' to
1712 * fix up the gap and long frame:
1714 * 3 - original frame (exception)
1715 * 2 - ESPFIX block (above)
1716 * 6 - gap (FIXUP_FRAME)
1717 * 5 - long frame (FIXUP_FRAME)
1720 lss (1+5+6)*4(%esp), %esp # back to espfix stack
1725 SYM_CODE_START(int3)
1729 jmp common_exception
1732 SYM_CODE_START(general_protection)
1734 pushl $do_general_protection
1735 jmp common_exception
1736 SYM_CODE_END(general_protection)
1738 .pushsection .text, "ax"
1739 SYM_CODE_START(rewind_stack_do_exit)
1740 /* Prevent any naive code from trying to unwind to our caller. */
1743 movl PER_CPU_VAR(cpu_current_top_of_stack), %esi
1744 leal -TOP_OF_KERNEL_STACK_PADDING-PTREGS_SIZE(%esi), %esp
1748 SYM_CODE_END(rewind_stack_do_exit)