2 * linux/arch/x86_64/entry.S
4 * Copyright (C) 1991, 1992 Linus Torvalds
5 * Copyright (C) 2000, 2001, 2002 Andi Kleen SuSE Labs
6 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
8 * entry.S contains the system-call and fault low-level handling routines.
10 * Some of this is documented in Documentation/x86/entry_64.txt
12 * A note on terminology:
13 * - iret frame: Architecture defined interrupt frame from SS to RIP
14 * at the top of the kernel process stack.
17 * - ENTRY/END: Define functions in the symbol table.
18 * - TRACE_IRQ_*: Trace hardirq state for lock debugging.
19 * - idtentry: Define exception entry points.
21 #include <linux/linkage.h>
22 #include <asm/segment.h>
23 #include <asm/cache.h>
24 #include <asm/errno.h>
25 #include <asm/asm-offsets.h>
27 #include <asm/unistd.h>
28 #include <asm/thread_info.h>
29 #include <asm/hw_irq.h>
30 #include <asm/page_types.h>
31 #include <asm/irqflags.h>
32 #include <asm/paravirt.h>
33 #include <asm/percpu.h>
36 #include <asm/pgtable_types.h>
37 #include <asm/export.h>
38 #include <asm/frame.h>
39 #include <asm/nospec-branch.h>
40 #include <linux/err.h>
45 .section .entry.text, "ax"
47 #ifdef CONFIG_PARAVIRT
48 ENTRY(native_usergs_sysret64)
52 END(native_usergs_sysret64)
53 #endif /* CONFIG_PARAVIRT */
55 .macro TRACE_IRQS_IRETQ
56 #ifdef CONFIG_TRACE_IRQFLAGS
57 bt $9, EFLAGS(%rsp) /* interrupts off? */
65 * When dynamic function tracer is enabled it will add a breakpoint
66 * to all locations that it is about to modify, sync CPUs, update
67 * all the code, sync CPUs, then remove the breakpoints. In this time
68 * if lockdep is enabled, it might jump back into the debug handler
69 * outside the updating of the IST protection. (TRACE_IRQS_ON/OFF).
71 * We need to change the IDT table before calling TRACE_IRQS_ON/OFF to
72 * make sure the stack pointer does not get reset back to the top
73 * of the debug stack, and instead just reuses the current stack.
75 #if defined(CONFIG_DYNAMIC_FTRACE) && defined(CONFIG_TRACE_IRQFLAGS)
77 .macro TRACE_IRQS_OFF_DEBUG
78 call debug_stack_set_zero
80 call debug_stack_reset
83 .macro TRACE_IRQS_ON_DEBUG
84 call debug_stack_set_zero
86 call debug_stack_reset
89 .macro TRACE_IRQS_IRETQ_DEBUG
90 bt $9, EFLAGS(%rsp) /* interrupts off? */
97 # define TRACE_IRQS_OFF_DEBUG TRACE_IRQS_OFF
98 # define TRACE_IRQS_ON_DEBUG TRACE_IRQS_ON
99 # define TRACE_IRQS_IRETQ_DEBUG TRACE_IRQS_IRETQ
103 * 64-bit SYSCALL instruction entry. Up to 6 arguments in registers.
105 * This is the only entry point used for 64-bit system calls. The
106 * hardware interface is reasonably well designed and the register to
107 * argument mapping Linux uses fits well with the registers that are
108 * available when SYSCALL is used.
110 * SYSCALL instructions can be found inlined in libc implementations as
111 * well as some other programs and libraries. There are also a handful
112 * of SYSCALL instructions in the vDSO used, for example, as a
113 * clock_gettimeofday fallback.
115 * 64-bit SYSCALL saves rip to rcx, clears rflags.RF, then saves rflags to r11,
116 * then loads new ss, cs, and rip from previously programmed MSRs.
117 * rflags gets masked by a value from another MSR (so CLD and CLAC
118 * are not needed). SYSCALL does not save anything on the stack
119 * and does not change rsp.
121 * Registers on entry:
122 * rax system call number
124 * r11 saved rflags (note: r11 is callee-clobbered register in C ABI)
128 * r10 arg3 (needs to be moved to rcx to conform to C ABI)
131 * (note: r12-r15, rbp, rbx are callee-preserved in C ABI)
133 * Only called from user space.
135 * When user can change pt_regs->foo always force IRET. That is because
136 * it deals with uncanonical addresses better. SYSRET has trouble
137 * with them due to bugs in both AMD and Intel CPUs.
140 .pushsection .entry_trampoline, "ax"
143 * The code in here gets remapped into cpu_entry_area's trampoline. This means
144 * that the assembler and linker have the wrong idea as to where this code
145 * lives (and, in fact, it's mapped more than once, so it's not even at a
146 * fixed address). So we can't reference any symbols outside the entry
147 * trampoline and expect it to work.
149 * Instead, we carefully abuse %rip-relative addressing.
150 * _entry_trampoline(%rip) refers to the start of the remapped) entry
151 * trampoline. We can thus find cpu_entry_area with this macro:
154 #define CPU_ENTRY_AREA \
155 _entry_trampoline - CPU_ENTRY_AREA_entry_trampoline(%rip)
157 /* The top word of the SYSENTER stack is hot and is usable as scratch space. */
158 #define RSP_SCRATCH CPU_ENTRY_AREA_entry_stack + \
159 SIZEOF_entry_stack - 8 + CPU_ENTRY_AREA
161 ENTRY(entry_SYSCALL_64_trampoline)
165 /* Stash the user RSP. */
166 movq %rsp, RSP_SCRATCH
168 /* Note: using %rsp as a scratch reg. */
169 SWITCH_TO_KERNEL_CR3 scratch_reg=%rsp
171 /* Load the top of the task stack into RSP */
172 movq CPU_ENTRY_AREA_tss + TSS_sp1 + CPU_ENTRY_AREA, %rsp
174 /* Start building the simulated IRET frame. */
175 pushq $__USER_DS /* pt_regs->ss */
176 pushq RSP_SCRATCH /* pt_regs->sp */
177 pushq %r11 /* pt_regs->flags */
178 pushq $__USER_CS /* pt_regs->cs */
179 pushq %rcx /* pt_regs->ip */
182 * x86 lacks a near absolute jump, and we can't jump to the real
183 * entry text with a relative jump. We could push the target
184 * address and then use retq, but this destroys the pipeline on
185 * many CPUs (wasting over 20 cycles on Sandy Bridge). Instead,
186 * spill RDI and restore it in a second-stage trampoline.
189 movq $entry_SYSCALL_64_stage2, %rdi
191 END(entry_SYSCALL_64_trampoline)
195 ENTRY(entry_SYSCALL_64_stage2)
198 jmp entry_SYSCALL_64_after_hwframe
199 END(entry_SYSCALL_64_stage2)
201 ENTRY(entry_SYSCALL_64)
204 * Interrupts are off on entry.
205 * We do not frame this tiny irq-off block with TRACE_IRQS_OFF/ON,
206 * it is too small to ever cause noticeable irq latency.
211 * This path is not taken when PAGE_TABLE_ISOLATION is disabled so it
212 * is not required to switch CR3.
214 movq %rsp, PER_CPU_VAR(rsp_scratch)
215 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp
219 /* Construct struct pt_regs on stack */
220 pushq $__USER_DS /* pt_regs->ss */
221 pushq PER_CPU_VAR(rsp_scratch) /* pt_regs->sp */
222 pushq %r11 /* pt_regs->flags */
223 pushq $__USER_CS /* pt_regs->cs */
224 pushq %rcx /* pt_regs->ip */
225 GLOBAL(entry_SYSCALL_64_after_hwframe)
226 pushq %rax /* pt_regs->orig_ax */
227 pushq %rdi /* pt_regs->di */
228 pushq %rsi /* pt_regs->si */
229 pushq %rdx /* pt_regs->dx */
230 pushq %rcx /* pt_regs->cx */
231 pushq $-ENOSYS /* pt_regs->ax */
232 pushq %r8 /* pt_regs->r8 */
233 pushq %r9 /* pt_regs->r9 */
234 pushq %r10 /* pt_regs->r10 */
235 pushq %r11 /* pt_regs->r11 */
236 sub $(6*8), %rsp /* pt_regs->bp, bx, r12-15 not saved */
237 UNWIND_HINT_REGS extra=0
240 * If we need to do entry work or if we guess we'll need to do
241 * exit work, go straight to the slow path.
243 movq PER_CPU_VAR(current_task), %r11
244 testl $_TIF_WORK_SYSCALL_ENTRY|_TIF_ALLWORK_MASK, TASK_TI_flags(%r11)
245 jnz entry_SYSCALL64_slow_path
247 entry_SYSCALL_64_fastpath:
249 * Easy case: enable interrupts and issue the syscall. If the syscall
250 * needs pt_regs, we'll call a stub that disables interrupts again
251 * and jumps to the slow path.
254 ENABLE_INTERRUPTS(CLBR_NONE)
255 #if __SYSCALL_MASK == ~0
256 cmpq $__NR_syscall_max, %rax
258 andl $__SYSCALL_MASK, %eax
259 cmpl $__NR_syscall_max, %eax
261 ja 1f /* return -ENOSYS (already in pt_regs->ax) */
265 * This call instruction is handled specially in stub_ptregs_64.
266 * It might end up jumping to the slow path. If it jumps, RAX
267 * and all argument registers are clobbered.
269 #ifdef CONFIG_RETPOLINE
270 movq sys_call_table(, %rax, 8), %rax
271 call __x86_indirect_thunk_rax
273 call *sys_call_table(, %rax, 8)
275 .Lentry_SYSCALL_64_after_fastpath_call:
281 * If we get here, then we know that pt_regs is clean for SYSRET64.
282 * If we see that no exit work is required (which we are required
283 * to check with IRQs off), then we can go straight to SYSRET64.
285 DISABLE_INTERRUPTS(CLBR_ANY)
287 movq PER_CPU_VAR(current_task), %r11
288 testl $_TIF_ALLWORK_MASK, TASK_TI_flags(%r11)
292 TRACE_IRQS_ON /* user mode is traced as IRQs on */
294 movq EFLAGS(%rsp), %r11
295 addq $6*8, %rsp /* skip extra regs -- they were preserved */
297 jmp .Lpop_c_regs_except_rcx_r11_and_sysret
301 * The fast path looked good when we started, but something changed
302 * along the way and we need to switch to the slow path. Calling
303 * raise(3) will trigger this, for example. IRQs are off.
306 ENABLE_INTERRUPTS(CLBR_ANY)
309 call syscall_return_slowpath /* returns with IRQs disabled */
310 jmp return_from_SYSCALL_64
312 entry_SYSCALL64_slow_path:
316 call do_syscall_64 /* returns with IRQs disabled */
318 return_from_SYSCALL_64:
319 TRACE_IRQS_IRETQ /* we're about to change IF */
322 * Try to use SYSRET instead of IRET if we're returning to
323 * a completely clean 64-bit userspace context. If we're not,
324 * go to the slow exit path.
329 cmpq %rcx, %r11 /* SYSRET requires RCX == RIP */
330 jne swapgs_restore_regs_and_return_to_usermode
333 * On Intel CPUs, SYSRET with non-canonical RCX/RIP will #GP
334 * in kernel space. This essentially lets the user take over
335 * the kernel, since userspace controls RSP.
337 * If width of "canonical tail" ever becomes variable, this will need
338 * to be updated to remain correct on both old and new CPUs.
340 * Change top bits to match most significant bit (47th or 56th bit
341 * depending on paging mode) in the address.
343 shl $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx
344 sar $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx
346 /* If this changed %rcx, it was not canonical */
348 jne swapgs_restore_regs_and_return_to_usermode
350 cmpq $__USER_CS, CS(%rsp) /* CS must match SYSRET */
351 jne swapgs_restore_regs_and_return_to_usermode
354 cmpq %r11, EFLAGS(%rsp) /* R11 == RFLAGS */
355 jne swapgs_restore_regs_and_return_to_usermode
358 * SYSCALL clears RF when it saves RFLAGS in R11 and SYSRET cannot
359 * restore RF properly. If the slowpath sets it for whatever reason, we
360 * need to restore it correctly.
362 * SYSRET can restore TF, but unlike IRET, restoring TF results in a
363 * trap from userspace immediately after SYSRET. This would cause an
364 * infinite loop whenever #DB happens with register state that satisfies
365 * the opportunistic SYSRET conditions. For example, single-stepping
368 * movq $stuck_here, %rcx
373 * would never get past 'stuck_here'.
375 testq $(X86_EFLAGS_RF|X86_EFLAGS_TF), %r11
376 jnz swapgs_restore_regs_and_return_to_usermode
378 /* nothing to check for RSP */
380 cmpq $__USER_DS, SS(%rsp) /* SS must match SYSRET */
381 jne swapgs_restore_regs_and_return_to_usermode
384 * We win! This label is here just for ease of understanding
385 * perf profiles. Nothing jumps here.
387 syscall_return_via_sysret:
388 /* rcx and r11 are already restored (see code above) */
391 .Lpop_c_regs_except_rcx_r11_and_sysret:
392 popq %rsi /* skip r11 */
397 popq %rsi /* skip rcx */
402 * Now all regs are restored except RSP and RDI.
403 * Save old stack pointer and switch to trampoline stack.
406 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp
408 pushq RSP-RDI(%rdi) /* RSP */
409 pushq (%rdi) /* RDI */
412 * We are on the trampoline stack. All regs except RDI are live.
413 * We can do future final exit work right here.
415 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi
420 END(entry_SYSCALL_64)
422 ENTRY(stub_ptregs_64)
424 * Syscalls marked as needing ptregs land here.
425 * If we are on the fast path, we need to save the extra regs,
426 * which we achieve by trying again on the slow path. If we are on
427 * the slow path, the extra regs are already saved.
429 * RAX stores a pointer to the C function implementing the syscall.
432 cmpq $.Lentry_SYSCALL_64_after_fastpath_call, (%rsp)
436 * Called from fast path -- disable IRQs again, pop return address
437 * and jump to slow path
439 DISABLE_INTERRUPTS(CLBR_ANY)
442 UNWIND_HINT_REGS extra=0
443 jmp entry_SYSCALL64_slow_path
446 JMP_NOSPEC %rax /* Called from C */
449 .macro ptregs_stub func
452 leaq \func(%rip), %rax
457 /* Instantiate ptregs_stub for each ptregs-using syscall */
458 #define __SYSCALL_64_QUAL_(sym)
459 #define __SYSCALL_64_QUAL_ptregs(sym) ptregs_stub sym
460 #define __SYSCALL_64(nr, sym, qual) __SYSCALL_64_QUAL_##qual(sym)
461 #include <asm/syscalls_64.h>
467 ENTRY(__switch_to_asm)
470 * Save callee-saved registers
471 * This must match the order in inactive_task_frame
481 movq %rsp, TASK_threadsp(%rdi)
482 movq TASK_threadsp(%rsi), %rsp
484 #ifdef CONFIG_CC_STACKPROTECTOR
485 movq TASK_stack_canary(%rsi), %rbx
486 movq %rbx, PER_CPU_VAR(irq_stack_union)+stack_canary_offset
489 #ifdef CONFIG_RETPOLINE
491 * When switching from a shallower to a deeper call stack
492 * the RSB may either underflow or use entries populated
493 * with userspace addresses. On CPUs where those concerns
494 * exist, overwrite the RSB with entries which capture
495 * speculative execution to prevent attack.
498 FILL_RETURN_BUFFER RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW
501 /* restore callee-saved registers */
513 * A newly forked process directly context switches into this address.
515 * rax: prev task we switched from
516 * rbx: kernel thread func (NULL for user thread)
517 * r12: kernel thread arg
522 call schedule_tail /* rdi: 'prev' task parameter */
524 testq %rbx, %rbx /* from kernel_thread? */
525 jnz 1f /* kernel threads are uncommon */
530 call syscall_return_slowpath /* returns with IRQs disabled */
531 TRACE_IRQS_ON /* user mode is traced as IRQS on */
532 jmp swapgs_restore_regs_and_return_to_usermode
539 * A kernel thread is allowed to return here after successfully
540 * calling do_execve(). Exit to userspace to complete the execve()
548 * Build the entry stubs with some assembler magic.
549 * We pack 1 stub into every 8-byte block.
552 ENTRY(irq_entries_start)
553 vector=FIRST_EXTERNAL_VECTOR
554 .rept (FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR)
555 UNWIND_HINT_IRET_REGS
556 pushq $(~vector+0x80) /* Note: always in signed byte range */
561 END(irq_entries_start)
563 .macro DEBUG_ENTRY_ASSERT_IRQS_OFF
564 #ifdef CONFIG_DEBUG_ENTRY
567 testl $X86_EFLAGS_IF, %eax
576 * Enters the IRQ stack if we're not already using it. NMI-safe. Clobbers
577 * flags and puts old RSP into old_rsp, and leaves all other GPRs alone.
578 * Requires kernel GSBASE.
580 * The invariant is that, if irq_count != -1, then the IRQ stack is in use.
582 .macro ENTER_IRQ_STACK regs=1 old_rsp
583 DEBUG_ENTRY_ASSERT_IRQS_OFF
587 UNWIND_HINT_REGS base=\old_rsp
590 incl PER_CPU_VAR(irq_count)
591 jnz .Lirq_stack_push_old_rsp_\@
594 * Right now, if we just incremented irq_count to zero, we've
595 * claimed the IRQ stack but we haven't switched to it yet.
597 * If anything is added that can interrupt us here without using IST,
598 * it must be *extremely* careful to limit its stack usage. This
599 * could include kprobes and a hypothetical future IST-less #DB
602 * The OOPS unwinder relies on the word at the top of the IRQ
603 * stack linking back to the previous RSP for the entire time we're
604 * on the IRQ stack. For this to work reliably, we need to write
605 * it before we actually move ourselves to the IRQ stack.
608 movq \old_rsp, PER_CPU_VAR(irq_stack_union + IRQ_STACK_SIZE - 8)
609 movq PER_CPU_VAR(irq_stack_ptr), %rsp
611 #ifdef CONFIG_DEBUG_ENTRY
613 * If the first movq above becomes wrong due to IRQ stack layout
614 * changes, the only way we'll notice is if we try to unwind right
615 * here. Assert that we set up the stack right to catch this type
618 cmpq -8(%rsp), \old_rsp
619 je .Lirq_stack_okay\@
624 .Lirq_stack_push_old_rsp_\@:
628 UNWIND_HINT_REGS indirect=1
633 * Undoes ENTER_IRQ_STACK.
635 .macro LEAVE_IRQ_STACK regs=1
636 DEBUG_ENTRY_ASSERT_IRQS_OFF
637 /* We need to be off the IRQ stack before decrementing irq_count. */
645 * As in ENTER_IRQ_STACK, irq_count == 0, we are still claiming
646 * the irq stack but we're not on it.
649 decl PER_CPU_VAR(irq_count)
653 * Interrupt entry/exit.
655 * Interrupt entry points save only callee clobbered registers in fast path.
657 * Entry runs with interrupts off.
660 /* 0(%rsp): ~(interrupt number) */
661 .macro interrupt func
664 testb $3, CS-ORIG_RAX(%rsp)
667 call switch_to_thread_stack
670 ALLOC_PT_GPREGS_ON_STACK
679 * IRQ from user mode.
681 * We need to tell lockdep that IRQs are off. We can't do this until
682 * we fix gsbase, and we should do it before enter_from_user_mode
683 * (which can take locks). Since TRACE_IRQS_OFF idempotent,
684 * the simplest way to handle it is to just call it twice if
685 * we enter from user mode. There's no reason to optimize this since
686 * TRACE_IRQS_OFF is a no-op if lockdep is off.
690 CALL_enter_from_user_mode
693 ENTER_IRQ_STACK old_rsp=%rdi
694 /* We entered an interrupt context - irqs are off: */
697 call \func /* rdi points to pt_regs */
701 * The interrupt stubs push (~vector+0x80) onto the stack and
702 * then jump to common_interrupt.
704 .p2align CONFIG_X86_L1_CACHE_SHIFT
707 addq $-0x80, (%rsp) /* Adjust vector to [-256, -1] range */
709 /* 0(%rsp): old RSP */
711 DISABLE_INTERRUPTS(CLBR_ANY)
719 /* Interrupt came from user space */
722 call prepare_exit_to_usermode
725 GLOBAL(swapgs_restore_regs_and_return_to_usermode)
726 #ifdef CONFIG_DEBUG_ENTRY
727 /* Assert that pt_regs indicates user mode. */
744 * The stack is now user RDI, orig_ax, RIP, CS, EFLAGS, RSP, SS.
745 * Save old stack pointer and switch to trampoline stack.
748 movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp
750 /* Copy the IRET frame to the trampoline stack. */
751 pushq 6*8(%rdi) /* SS */
752 pushq 5*8(%rdi) /* RSP */
753 pushq 4*8(%rdi) /* EFLAGS */
754 pushq 3*8(%rdi) /* CS */
755 pushq 2*8(%rdi) /* RIP */
757 /* Push user RDI on the trampoline stack. */
761 * We are on the trampoline stack. All regs except RDI are live.
762 * We can do future final exit work right here.
765 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi
773 /* Returning to kernel space */
775 #ifdef CONFIG_PREEMPT
776 /* Interrupts are off */
777 /* Check if we need preemption */
778 bt $9, EFLAGS(%rsp) /* were interrupts off? */
780 0: cmpl $0, PER_CPU_VAR(__preempt_count)
782 call preempt_schedule_irq
787 * The iretq could re-enable interrupts:
791 GLOBAL(restore_regs_and_return_to_kernel)
792 #ifdef CONFIG_DEBUG_ENTRY
793 /* Assert that pt_regs indicates kernel mode. */
801 addq $8, %rsp /* skip regs->orig_ax */
805 UNWIND_HINT_IRET_REGS
807 * Are we returning to a stack segment from the LDT? Note: in
808 * 64-bit mode SS:RSP on the exception stack is always valid.
810 #ifdef CONFIG_X86_ESPFIX64
811 testb $4, (SS-RIP)(%rsp)
812 jnz native_irq_return_ldt
815 .global native_irq_return_iret
816 native_irq_return_iret:
818 * This may fault. Non-paranoid faults on return to userspace are
819 * handled by fixup_bad_iret. These include #SS, #GP, and #NP.
820 * Double-faults due to espfix64 are handled in do_double_fault.
821 * Other faults here are fatal.
825 #ifdef CONFIG_X86_ESPFIX64
826 native_irq_return_ldt:
828 * We are running with user GSBASE. All GPRs contain their user
829 * values. We have a percpu ESPFIX stack that is eight slots
830 * long (see ESPFIX_STACK_SIZE). espfix_waddr points to the bottom
831 * of the ESPFIX stack.
833 * We clobber RAX and RDI in this code. We stash RDI on the
834 * normal stack and RAX on the ESPFIX stack.
836 * The ESPFIX stack layout we set up looks like this:
838 * --- top of ESPFIX stack ---
843 * RIP <-- RSP points here when we're done
844 * RAX <-- espfix_waddr points here
845 * --- bottom of ESPFIX stack ---
848 pushq %rdi /* Stash user RDI */
849 SWAPGS /* to kernel GS */
850 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi /* to kernel CR3 */
852 movq PER_CPU_VAR(espfix_waddr), %rdi
853 movq %rax, (0*8)(%rdi) /* user RAX */
854 movq (1*8)(%rsp), %rax /* user RIP */
855 movq %rax, (1*8)(%rdi)
856 movq (2*8)(%rsp), %rax /* user CS */
857 movq %rax, (2*8)(%rdi)
858 movq (3*8)(%rsp), %rax /* user RFLAGS */
859 movq %rax, (3*8)(%rdi)
860 movq (5*8)(%rsp), %rax /* user SS */
861 movq %rax, (5*8)(%rdi)
862 movq (4*8)(%rsp), %rax /* user RSP */
863 movq %rax, (4*8)(%rdi)
864 /* Now RAX == RSP. */
866 andl $0xffff0000, %eax /* RAX = (RSP & 0xffff0000) */
869 * espfix_stack[31:16] == 0. The page tables are set up such that
870 * (espfix_stack | (X & 0xffff0000)) points to a read-only alias of
871 * espfix_waddr for any X. That is, there are 65536 RO aliases of
872 * the same page. Set up RSP so that RSP[31:16] contains the
873 * respective 16 bits of the /userspace/ RSP and RSP nonetheless
874 * still points to an RO alias of the ESPFIX stack.
876 orq PER_CPU_VAR(espfix_stack), %rax
878 SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi
879 SWAPGS /* to user GS */
880 popq %rdi /* Restore user RDI */
883 UNWIND_HINT_IRET_REGS offset=8
886 * At this point, we cannot write to the stack any more, but we can
889 popq %rax /* Restore user RAX */
892 * RSP now points to an ordinary IRET frame, except that the page
893 * is read-only and RSP[31:16] are preloaded with the userspace
894 * values. We can now IRET back to userspace.
896 jmp native_irq_return_iret
898 END(common_interrupt)
903 .macro apicinterrupt3 num sym do_sym
905 UNWIND_HINT_IRET_REGS
914 #ifdef CONFIG_TRACING
915 #define trace(sym) trace_##sym
916 #define smp_trace(sym) smp_trace_##sym
918 .macro trace_apicinterrupt num sym
919 apicinterrupt3 \num trace(\sym) smp_trace(\sym)
922 .macro trace_apicinterrupt num sym do_sym
926 /* Make sure APIC interrupt handlers end up in the irqentry section: */
927 #define PUSH_SECTION_IRQENTRY .pushsection .irqentry.text, "ax"
928 #define POP_SECTION_IRQENTRY .popsection
930 .macro apicinterrupt num sym do_sym
931 PUSH_SECTION_IRQENTRY
932 apicinterrupt3 \num \sym \do_sym
933 trace_apicinterrupt \num \sym
938 apicinterrupt3 IRQ_MOVE_CLEANUP_VECTOR irq_move_cleanup_interrupt smp_irq_move_cleanup_interrupt
939 apicinterrupt3 REBOOT_VECTOR reboot_interrupt smp_reboot_interrupt
943 apicinterrupt3 UV_BAU_MESSAGE uv_bau_message_intr1 uv_bau_message_interrupt
946 apicinterrupt LOCAL_TIMER_VECTOR apic_timer_interrupt smp_apic_timer_interrupt
947 apicinterrupt X86_PLATFORM_IPI_VECTOR x86_platform_ipi smp_x86_platform_ipi
949 #ifdef CONFIG_HAVE_KVM
950 apicinterrupt3 POSTED_INTR_VECTOR kvm_posted_intr_ipi smp_kvm_posted_intr_ipi
951 apicinterrupt3 POSTED_INTR_WAKEUP_VECTOR kvm_posted_intr_wakeup_ipi smp_kvm_posted_intr_wakeup_ipi
952 apicinterrupt3 POSTED_INTR_NESTED_VECTOR kvm_posted_intr_nested_ipi smp_kvm_posted_intr_nested_ipi
955 #ifdef CONFIG_X86_MCE_THRESHOLD
956 apicinterrupt THRESHOLD_APIC_VECTOR threshold_interrupt smp_threshold_interrupt
959 #ifdef CONFIG_X86_MCE_AMD
960 apicinterrupt DEFERRED_ERROR_VECTOR deferred_error_interrupt smp_deferred_error_interrupt
963 #ifdef CONFIG_X86_THERMAL_VECTOR
964 apicinterrupt THERMAL_APIC_VECTOR thermal_interrupt smp_thermal_interrupt
968 apicinterrupt CALL_FUNCTION_SINGLE_VECTOR call_function_single_interrupt smp_call_function_single_interrupt
969 apicinterrupt CALL_FUNCTION_VECTOR call_function_interrupt smp_call_function_interrupt
970 apicinterrupt RESCHEDULE_VECTOR reschedule_interrupt smp_reschedule_interrupt
973 apicinterrupt ERROR_APIC_VECTOR error_interrupt smp_error_interrupt
974 apicinterrupt SPURIOUS_APIC_VECTOR spurious_interrupt smp_spurious_interrupt
976 #ifdef CONFIG_IRQ_WORK
977 apicinterrupt IRQ_WORK_VECTOR irq_work_interrupt smp_irq_work_interrupt
981 * Exception entry points.
983 #define CPU_TSS_IST(x) PER_CPU_VAR(cpu_tss_rw) + (TSS_ist + ((x) - 1) * 8)
986 * Switch to the thread stack. This is called with the IRET frame and
987 * orig_ax on the stack. (That is, RDI..R12 are not on the stack and
988 * space has not been allocated for them.)
990 ENTRY(switch_to_thread_stack)
994 /* Need to switch before accessing the thread stack. */
995 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi
997 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp
998 UNWIND_HINT sp_offset=16 sp_reg=ORC_REG_DI
1000 pushq 7*8(%rdi) /* regs->ss */
1001 pushq 6*8(%rdi) /* regs->rsp */
1002 pushq 5*8(%rdi) /* regs->eflags */
1003 pushq 4*8(%rdi) /* regs->cs */
1004 pushq 3*8(%rdi) /* regs->ip */
1005 pushq 2*8(%rdi) /* regs->orig_ax */
1006 pushq 8(%rdi) /* return address */
1011 END(switch_to_thread_stack)
1013 .macro idtentry sym do_sym has_error_code:req paranoid=0 shift_ist=-1
1015 UNWIND_HINT_IRET_REGS offset=\has_error_code*8
1018 .if \shift_ist != -1 && \paranoid == 0
1019 .error "using shift_ist requires paranoid=1"
1024 .if \has_error_code == 0
1025 pushq $-1 /* ORIG_RAX: no syscall to restart */
1028 ALLOC_PT_GPREGS_ON_STACK
1031 testb $3, CS(%rsp) /* If coming from userspace, switch stacks */
1032 jnz .Lfrom_usermode_switch_stack_\@
1041 /* returned flag: ebx=0: need swapgs on exit, ebx=1: don't need it */
1044 .if \shift_ist != -1
1045 TRACE_IRQS_OFF_DEBUG /* reload IDT in case of recursion */
1051 movq %rsp, %rdi /* pt_regs pointer */
1054 movq ORIG_RAX(%rsp), %rsi /* get error code */
1055 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */
1057 xorl %esi, %esi /* no error code */
1060 .if \shift_ist != -1
1061 subq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist)
1066 .if \shift_ist != -1
1067 addq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist)
1070 /* these procedures expect "no swapgs" flag in ebx */
1079 * Entry from userspace. Switch stacks and treat it
1080 * as a normal entry. This means that paranoid handlers
1081 * run in real process context if user_mode(regs).
1083 .Lfrom_usermode_switch_stack_\@:
1086 movq %rsp, %rdi /* pt_regs pointer */
1089 movq ORIG_RAX(%rsp), %rsi /* get error code */
1090 movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */
1092 xorl %esi, %esi /* no error code */
1097 jmp error_exit /* %ebx: no swapgs flag */
1102 idtentry divide_error do_divide_error has_error_code=0
1103 idtentry overflow do_overflow has_error_code=0
1104 idtentry bounds do_bounds has_error_code=0
1105 idtentry invalid_op do_invalid_op has_error_code=0
1106 idtentry device_not_available do_device_not_available has_error_code=0
1107 idtentry double_fault do_double_fault has_error_code=1 paranoid=2
1108 idtentry coprocessor_segment_overrun do_coprocessor_segment_overrun has_error_code=0
1109 idtentry invalid_TSS do_invalid_TSS has_error_code=1
1110 idtentry segment_not_present do_segment_not_present has_error_code=1
1111 idtentry spurious_interrupt_bug do_spurious_interrupt_bug has_error_code=0
1112 idtentry coprocessor_error do_coprocessor_error has_error_code=0
1113 idtentry alignment_check do_alignment_check has_error_code=1
1114 idtentry simd_coprocessor_error do_simd_coprocessor_error has_error_code=0
1118 * Reload gs selector with exception handling
1121 ENTRY(native_load_gs_index)
1124 DISABLE_INTERRUPTS(CLBR_ANY & ~CLBR_RDI)
1128 2: ALTERNATIVE "", "mfence", X86_BUG_SWAPGS_FENCE
1133 ENDPROC(native_load_gs_index)
1134 EXPORT_SYMBOL(native_load_gs_index)
1136 _ASM_EXTABLE(.Lgs_change, bad_gs)
1137 .section .fixup, "ax"
1138 /* running with kernelgs */
1140 SWAPGS /* switch back to user gs */
1142 /* This can't be a string because the preprocessor needs to see it. */
1143 movl $__USER_DS, %eax
1146 ALTERNATIVE "", "ZAP_GS", X86_BUG_NULL_SEG
1152 /* Call softirq on interrupt stack. Interrupts are off. */
1153 ENTRY(do_softirq_own_stack)
1156 ENTER_IRQ_STACK regs=0 old_rsp=%r11
1158 LEAVE_IRQ_STACK regs=0
1161 ENDPROC(do_softirq_own_stack)
1164 idtentry hypervisor_callback xen_do_hypervisor_callback has_error_code=0
1167 * A note on the "critical region" in our callback handler.
1168 * We want to avoid stacking callback handlers due to events occurring
1169 * during handling of the last event. To do this, we keep events disabled
1170 * until we've done all processing. HOWEVER, we must enable events before
1171 * popping the stack frame (can't be done atomically) and so it would still
1172 * be possible to get enough handler activations to overflow the stack.
1173 * Although unlikely, bugs of that kind are hard to track down, so we'd
1174 * like to avoid the possibility.
1175 * So, on entry to the handler we detect whether we interrupted an
1176 * existing activation in its critical region -- if so, we pop the current
1177 * activation and restart the handler using the previous one.
1179 ENTRY(xen_do_hypervisor_callback) /* do_hypervisor_callback(struct *pt_regs) */
1182 * Since we don't modify %rdi, evtchn_do_upall(struct *pt_regs) will
1183 * see the correct pointer to the pt_regs
1186 movq %rdi, %rsp /* we don't return, adjust the stack frame */
1189 ENTER_IRQ_STACK old_rsp=%r10
1190 call xen_evtchn_do_upcall
1193 #ifndef CONFIG_PREEMPT
1194 call xen_maybe_preempt_hcall
1197 END(xen_do_hypervisor_callback)
1200 * Hypervisor uses this for application faults while it executes.
1201 * We get here for two reasons:
1202 * 1. Fault while reloading DS, ES, FS or GS
1203 * 2. Fault while executing IRET
1204 * Category 1 we do not need to fix up as Xen has already reloaded all segment
1205 * registers that could be reloaded and zeroed the others.
1206 * Category 2 we fix up by killing the current process. We cannot use the
1207 * normal Linux return path in this case because if we use the IRET hypercall
1208 * to pop the stack frame we end up in an infinite loop of failsafe callbacks.
1209 * We distinguish between categories by comparing each saved segment register
1210 * with its current contents: any discrepancy means we in category 1.
1212 ENTRY(xen_failsafe_callback)
1215 cmpw %cx, 0x10(%rsp)
1218 cmpw %cx, 0x18(%rsp)
1221 cmpw %cx, 0x20(%rsp)
1224 cmpw %cx, 0x28(%rsp)
1226 /* All segments match their saved values => Category 2 (Bad IRET). */
1231 UNWIND_HINT_IRET_REGS offset=8
1232 jmp general_protection
1233 1: /* Segment mismatch => Category 1 (Bad segment). Retry the IRET. */
1237 UNWIND_HINT_IRET_REGS
1238 pushq $-1 /* orig_ax = -1 => not a system call */
1239 ALLOC_PT_GPREGS_ON_STACK
1242 ENCODE_FRAME_POINTER
1244 END(xen_failsafe_callback)
1246 apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \
1247 xen_hvm_callback_vector xen_evtchn_do_upcall
1249 #endif /* CONFIG_XEN */
1251 #if IS_ENABLED(CONFIG_HYPERV)
1252 apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \
1253 hyperv_callback_vector hyperv_vector_handler
1254 #endif /* CONFIG_HYPERV */
1256 idtentry debug do_debug has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK
1257 idtentry int3 do_int3 has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK
1258 idtentry stack_segment do_stack_segment has_error_code=1
1261 idtentry xennmi do_nmi has_error_code=0
1262 idtentry xendebug do_debug has_error_code=0
1263 idtentry xenint3 do_int3 has_error_code=0
1266 idtentry general_protection do_general_protection has_error_code=1
1267 idtentry page_fault do_page_fault has_error_code=1
1269 #ifdef CONFIG_KVM_GUEST
1270 idtentry async_page_fault do_async_page_fault has_error_code=1
1273 #ifdef CONFIG_X86_MCE
1274 idtentry machine_check has_error_code=0 paranoid=1 do_sym=*machine_check_vector(%rip)
1278 * Save all registers in pt_regs, and switch gs if needed.
1279 * Use slow, but surefire "are we in kernel?" check.
1280 * Return: ebx=0: need swapgs on exit, ebx=1: otherwise
1282 ENTRY(paranoid_entry)
1287 ENCODE_FRAME_POINTER 8
1289 movl $MSR_GS_BASE, %ecx
1292 js 1f /* negative -> in kernel */
1297 SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg=%rax save_reg=%r14
1303 * "Paranoid" exit path from exception stack. This is invoked
1304 * only on return from non-NMI IST interrupts that came
1305 * from kernel space.
1307 * We may be returning to very strange contexts (e.g. very early
1308 * in syscall entry), so checking for preemption here would
1309 * be complicated. Fortunately, we there's no good reason
1310 * to try to handle preemption here.
1312 * On entry, ebx is "no swapgs" flag (1: don't need swapgs, 0: need it)
1314 ENTRY(paranoid_exit)
1316 DISABLE_INTERRUPTS(CLBR_ANY)
1317 TRACE_IRQS_OFF_DEBUG
1318 testl %ebx, %ebx /* swapgs needed? */
1319 jnz .Lparanoid_exit_no_swapgs
1321 RESTORE_CR3 scratch_reg=%rbx save_reg=%r14
1323 jmp .Lparanoid_exit_restore
1324 .Lparanoid_exit_no_swapgs:
1325 TRACE_IRQS_IRETQ_DEBUG
1326 .Lparanoid_exit_restore:
1327 jmp restore_regs_and_return_to_kernel
1331 * Save all registers in pt_regs, and switch gs if needed.
1332 * Return: EBX=0: came from user mode; EBX=1: otherwise
1339 ENCODE_FRAME_POINTER 8
1341 testb $3, CS+8(%rsp)
1342 jz .Lerror_kernelspace
1345 * We entered from user mode or we're pretending to have entered
1346 * from user mode due to an IRET fault.
1349 /* We have user CR3. Change to kernel CR3. */
1350 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
1352 .Lerror_entry_from_usermode_after_swapgs:
1353 /* Put us onto the real thread stack. */
1354 popq %r12 /* save return addr in %12 */
1355 movq %rsp, %rdi /* arg0 = pt_regs pointer */
1357 movq %rax, %rsp /* switch stack */
1358 ENCODE_FRAME_POINTER
1362 * We need to tell lockdep that IRQs are off. We can't do this until
1363 * we fix gsbase, and we should do it before enter_from_user_mode
1364 * (which can take locks).
1367 CALL_enter_from_user_mode
1375 * There are two places in the kernel that can potentially fault with
1376 * usergs. Handle them here. B stepping K8s sometimes report a
1377 * truncated RIP for IRET exceptions returning to compat mode. Check
1378 * for these here too.
1380 .Lerror_kernelspace:
1382 leaq native_irq_return_iret(%rip), %rcx
1383 cmpq %rcx, RIP+8(%rsp)
1385 movl %ecx, %eax /* zero extend */
1386 cmpq %rax, RIP+8(%rsp)
1388 cmpq $.Lgs_change, RIP+8(%rsp)
1389 jne .Lerror_entry_done
1392 * hack: .Lgs_change can fail with user gsbase. If this happens, fix up
1393 * gsbase and proceed. We'll fix up the exception and land in
1394 * .Lgs_change's error handler with kernel gsbase.
1397 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
1398 jmp .Lerror_entry_done
1401 /* Fix truncated RIP */
1402 movq %rcx, RIP+8(%rsp)
1407 * We came from an IRET to user mode, so we have user
1408 * gsbase and CR3. Switch to kernel gsbase and CR3:
1411 SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
1414 * Pretend that the exception came from user mode: set up pt_regs
1415 * as if we faulted immediately after IRET and clear EBX so that
1416 * error_exit knows that we will be returning to user mode.
1422 jmp .Lerror_entry_from_usermode_after_swapgs
1427 * On entry, EBX is a "return to kernel mode" flag:
1428 * 1: already in kernel mode, don't need SWAPGS
1429 * 0: user gsbase is loaded, we need SWAPGS and standard preparation for return to usermode
1433 DISABLE_INTERRUPTS(CLBR_ANY)
1441 * Runs on exception stack. Xen PV does not go through this path at all,
1442 * so we can use real assembly here.
1445 * %r14: Used to save/restore the CR3 of the interrupted context
1446 * when PAGE_TABLE_ISOLATION is in use. Do not clobber.
1449 UNWIND_HINT_IRET_REGS
1452 * We allow breakpoints in NMIs. If a breakpoint occurs, then
1453 * the iretq it performs will take us out of NMI context.
1454 * This means that we can have nested NMIs where the next
1455 * NMI is using the top of the stack of the previous NMI. We
1456 * can't let it execute because the nested NMI will corrupt the
1457 * stack of the previous NMI. NMI handlers are not re-entrant
1460 * To handle this case we do the following:
1461 * Check the a special location on the stack that contains
1462 * a variable that is set when NMIs are executing.
1463 * The interrupted task's stack is also checked to see if it
1465 * If the variable is not set and the stack is not the NMI
1467 * o Set the special variable on the stack
1468 * o Copy the interrupt frame into an "outermost" location on the
1470 * o Copy the interrupt frame into an "iret" location on the stack
1471 * o Continue processing the NMI
1472 * If the variable is set or the previous stack is the NMI stack:
1473 * o Modify the "iret" location to jump to the repeat_nmi
1474 * o return back to the first NMI
1476 * Now on exit of the first NMI, we first clear the stack variable
1477 * The NMI stack will tell any nested NMIs at that point that it is
1478 * nested. Then we pop the stack normally with iret, and if there was
1479 * a nested NMI that updated the copy interrupt stack frame, a
1480 * jump will be made to the repeat_nmi code that will handle the second
1483 * However, espfix prevents us from directly returning to userspace
1484 * with a single IRET instruction. Similarly, IRET to user mode
1485 * can fault. We therefore handle NMIs from user space like
1486 * other IST entries.
1491 /* Use %rdx as our temp variable throughout */
1494 testb $3, CS-RIP+8(%rsp)
1495 jz .Lnmi_from_kernel
1498 * NMI from user mode. We need to run on the thread stack, but we
1499 * can't go through the normal entry paths: NMIs are masked, and
1500 * we don't want to enable interrupts, because then we'll end
1501 * up in an awkward situation in which IRQs are on but NMIs
1504 * We also must not push anything to the stack before switching
1505 * stacks lest we corrupt the "NMI executing" variable.
1510 SWITCH_TO_KERNEL_CR3 scratch_reg=%rdx
1512 movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp
1513 UNWIND_HINT_IRET_REGS base=%rdx offset=8
1514 pushq 5*8(%rdx) /* pt_regs->ss */
1515 pushq 4*8(%rdx) /* pt_regs->rsp */
1516 pushq 3*8(%rdx) /* pt_regs->flags */
1517 pushq 2*8(%rdx) /* pt_regs->cs */
1518 pushq 1*8(%rdx) /* pt_regs->rip */
1519 UNWIND_HINT_IRET_REGS
1520 pushq $-1 /* pt_regs->orig_ax */
1521 pushq %rdi /* pt_regs->di */
1522 pushq %rsi /* pt_regs->si */
1523 pushq (%rdx) /* pt_regs->dx */
1524 pushq %rcx /* pt_regs->cx */
1525 pushq %rax /* pt_regs->ax */
1526 pushq %r8 /* pt_regs->r8 */
1527 pushq %r9 /* pt_regs->r9 */
1528 pushq %r10 /* pt_regs->r10 */
1529 pushq %r11 /* pt_regs->r11 */
1530 pushq %rbx /* pt_regs->rbx */
1531 pushq %rbp /* pt_regs->rbp */
1532 pushq %r12 /* pt_regs->r12 */
1533 pushq %r13 /* pt_regs->r13 */
1534 pushq %r14 /* pt_regs->r14 */
1535 pushq %r15 /* pt_regs->r15 */
1537 ENCODE_FRAME_POINTER
1540 * At this point we no longer need to worry about stack damage
1541 * due to nesting -- we're on the normal thread stack and we're
1542 * done with the NMI stack.
1550 * Return back to user mode. We must *not* do the normal exit
1551 * work, because we don't want to enable interrupts.
1553 jmp swapgs_restore_regs_and_return_to_usermode
1557 * Here's what our stack frame will look like:
1558 * +---------------------------------------------------------+
1560 * | original Return RSP |
1561 * | original RFLAGS |
1564 * +---------------------------------------------------------+
1565 * | temp storage for rdx |
1566 * +---------------------------------------------------------+
1567 * | "NMI executing" variable |
1568 * +---------------------------------------------------------+
1569 * | iret SS } Copied from "outermost" frame |
1570 * | iret Return RSP } on each loop iteration; overwritten |
1571 * | iret RFLAGS } by a nested NMI to force another |
1572 * | iret CS } iteration if needed. |
1574 * +---------------------------------------------------------+
1575 * | outermost SS } initialized in first_nmi; |
1576 * | outermost Return RSP } will not be changed before |
1577 * | outermost RFLAGS } NMI processing is done. |
1578 * | outermost CS } Copied to "iret" frame on each |
1579 * | outermost RIP } iteration. |
1580 * +---------------------------------------------------------+
1582 * +---------------------------------------------------------+
1584 * The "original" frame is used by hardware. Before re-enabling
1585 * NMIs, we need to be done with it, and we need to leave enough
1586 * space for the asm code here.
1588 * We return by executing IRET while RSP points to the "iret" frame.
1589 * That will either return for real or it will loop back into NMI
1592 * The "outermost" frame is copied to the "iret" frame on each
1593 * iteration of the loop, so each iteration starts with the "iret"
1594 * frame pointing to the final return target.
1598 * Determine whether we're a nested NMI.
1600 * If we interrupted kernel code between repeat_nmi and
1601 * end_repeat_nmi, then we are a nested NMI. We must not
1602 * modify the "iret" frame because it's being written by
1603 * the outer NMI. That's okay; the outer NMI handler is
1604 * about to about to call do_nmi anyway, so we can just
1605 * resume the outer NMI.
1608 movq $repeat_nmi, %rdx
1611 movq $end_repeat_nmi, %rdx
1617 * Now check "NMI executing". If it's set, then we're nested.
1618 * This will not detect if we interrupted an outer NMI just
1625 * Now test if the previous stack was an NMI stack. This covers
1626 * the case where we interrupt an outer NMI after it clears
1627 * "NMI executing" but before IRET. We need to be careful, though:
1628 * there is one case in which RSP could point to the NMI stack
1629 * despite there being no NMI active: naughty userspace controls
1630 * RSP at the very beginning of the SYSCALL targets. We can
1631 * pull a fast one on naughty userspace, though: we program
1632 * SYSCALL to mask DF, so userspace cannot cause DF to be set
1633 * if it controls the kernel's RSP. We set DF before we clear
1637 /* Compare the NMI stack (rdx) with the stack we came from (4*8(%rsp)) */
1638 cmpq %rdx, 4*8(%rsp)
1639 /* If the stack pointer is above the NMI stack, this is a normal NMI */
1642 subq $EXCEPTION_STKSZ, %rdx
1643 cmpq %rdx, 4*8(%rsp)
1644 /* If it is below the NMI stack, it is a normal NMI */
1647 /* Ah, it is within the NMI stack. */
1649 testb $(X86_EFLAGS_DF >> 8), (3*8 + 1)(%rsp)
1650 jz first_nmi /* RSP was user controlled. */
1652 /* This is a nested NMI. */
1656 * Modify the "iret" frame to point to repeat_nmi, forcing another
1657 * iteration of NMI handling.
1660 leaq -10*8(%rsp), %rdx
1667 /* Put stack back */
1673 /* We are returning to kernel mode, so this cannot result in a fault. */
1680 /* Make room for "NMI executing". */
1683 /* Leave room for the "iret" frame */
1686 /* Copy the "original" frame to the "outermost" frame */
1690 UNWIND_HINT_IRET_REGS
1692 /* Everything up to here is safe from nested NMIs */
1694 #ifdef CONFIG_DEBUG_ENTRY
1696 * For ease of testing, unmask NMIs right away. Disabled by
1697 * default because IRET is very expensive.
1700 pushq %rsp /* RSP (minus 8 because of the previous push) */
1701 addq $8, (%rsp) /* Fix up RSP */
1703 pushq $__KERNEL_CS /* CS */
1705 iretq /* continues at repeat_nmi below */
1706 UNWIND_HINT_IRET_REGS
1712 * If there was a nested NMI, the first NMI's iret will return
1713 * here. But NMIs are still enabled and we can take another
1714 * nested NMI. The nested NMI checks the interrupted RIP to see
1715 * if it is between repeat_nmi and end_repeat_nmi, and if so
1716 * it will just return, as we are about to repeat an NMI anyway.
1717 * This makes it safe to copy to the stack frame that a nested
1720 * RSP is pointing to "outermost RIP". gsbase is unknown, but, if
1721 * we're repeating an NMI, gsbase has the same value that it had on
1722 * the first iteration. paranoid_entry will load the kernel
1723 * gsbase if needed before we call do_nmi. "NMI executing"
1726 movq $1, 10*8(%rsp) /* Set "NMI executing". */
1729 * Copy the "outermost" frame to the "iret" frame. NMIs that nest
1730 * here must not modify the "iret" frame while we're writing to
1731 * it or it will end up containing garbage.
1741 * Everything below this point can be preempted by a nested NMI.
1742 * If this happens, then the inner NMI will change the "iret"
1743 * frame to point back to repeat_nmi.
1745 pushq $-1 /* ORIG_RAX: no syscall to restart */
1746 ALLOC_PT_GPREGS_ON_STACK
1749 * Use paranoid_entry to handle SWAPGS, but no need to use paranoid_exit
1750 * as we should not be calling schedule in NMI context.
1751 * Even with normal interrupts enabled. An NMI should not be
1752 * setting NEED_RESCHED or anything that normal interrupts and
1753 * exceptions might do.
1758 /* paranoidentry do_nmi, 0; without TRACE_IRQS_OFF */
1763 RESTORE_CR3 scratch_reg=%r15 save_reg=%r14
1765 testl %ebx, %ebx /* swapgs needed? */
1774 * Skip orig_ax and the "outermost" frame to point RSP at the "iret"
1775 * at the "iret" frame.
1780 * Clear "NMI executing". Set DF first so that we can easily
1781 * distinguish the remaining code between here and IRET from
1782 * the SYSCALL entry and exit paths.
1784 * We arguably should just inspect RIP instead, but I (Andy) wrote
1785 * this code when I had the misapprehension that Xen PV supported
1786 * NMIs, and Xen PV would break that approach.
1789 movq $0, 5*8(%rsp) /* clear "NMI executing" */
1792 * iretq reads the "iret" frame and exits the NMI stack in a
1793 * single instruction. We are returning to kernel mode, so this
1794 * cannot result in a fault. Similarly, we don't need to worry
1795 * about espfix64 on the way back to kernel mode.
1800 ENTRY(ignore_sysret)
1806 ENTRY(rewind_stack_do_exit)
1808 /* Prevent any naive code from trying to unwind to our caller. */
1811 movq PER_CPU_VAR(cpu_current_top_of_stack), %rax
1812 leaq -PTREGS_SIZE(%rax), %rsp
1813 UNWIND_HINT_FUNC sp_offset=PTREGS_SIZE
1816 END(rewind_stack_do_exit)