1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Advanced Micro Devices, Inc.
5 * Author: Jacob Shin <jacob.shin@amd.com>
8 #include <linux/perf_event.h>
9 #include <linux/percpu.h>
10 #include <linux/types.h>
11 #include <linux/slab.h>
12 #include <linux/init.h>
13 #include <linux/cpu.h>
14 #include <linux/cpumask.h>
16 #include <asm/cpufeature.h>
17 #include <asm/perf_event.h>
21 #define NUM_COUNTERS_NB 4
22 #define NUM_COUNTERS_L2 4
23 #define NUM_COUNTERS_L3 6
24 #define MAX_COUNTERS 6
26 #define RDPMC_BASE_NB 6
27 #define RDPMC_BASE_LLC 10
29 #define COUNTER_SHIFT 16
32 #define pr_fmt(fmt) "amd_uncore: " fmt
34 static int num_counters_llc
;
35 static int num_counters_nb
;
38 static HLIST_HEAD(uncore_unused_list
);
47 cpumask_t
*active_mask
;
49 struct perf_event
*events
[MAX_COUNTERS
];
50 struct hlist_node node
;
53 static struct amd_uncore
* __percpu
*amd_uncore_nb
;
54 static struct amd_uncore
* __percpu
*amd_uncore_llc
;
56 static struct pmu amd_nb_pmu
;
57 static struct pmu amd_llc_pmu
;
59 static cpumask_t amd_nb_active_mask
;
60 static cpumask_t amd_llc_active_mask
;
62 static bool is_nb_event(struct perf_event
*event
)
64 return event
->pmu
->type
== amd_nb_pmu
.type
;
67 static bool is_llc_event(struct perf_event
*event
)
69 return event
->pmu
->type
== amd_llc_pmu
.type
;
72 static struct amd_uncore
*event_to_amd_uncore(struct perf_event
*event
)
74 if (is_nb_event(event
) && amd_uncore_nb
)
75 return *per_cpu_ptr(amd_uncore_nb
, event
->cpu
);
76 else if (is_llc_event(event
) && amd_uncore_llc
)
77 return *per_cpu_ptr(amd_uncore_llc
, event
->cpu
);
82 static void amd_uncore_read(struct perf_event
*event
)
84 struct hw_perf_event
*hwc
= &event
->hw
;
89 * since we do not enable counter overflow interrupts,
90 * we do not have to worry about prev_count changing on us
93 prev
= local64_read(&hwc
->prev_count
);
94 rdpmcl(hwc
->event_base_rdpmc
, new);
95 local64_set(&hwc
->prev_count
, new);
96 delta
= (new << COUNTER_SHIFT
) - (prev
<< COUNTER_SHIFT
);
97 delta
>>= COUNTER_SHIFT
;
98 local64_add(delta
, &event
->count
);
101 static void amd_uncore_start(struct perf_event
*event
, int flags
)
103 struct hw_perf_event
*hwc
= &event
->hw
;
105 if (flags
& PERF_EF_RELOAD
)
106 wrmsrl(hwc
->event_base
, (u64
)local64_read(&hwc
->prev_count
));
109 wrmsrl(hwc
->config_base
, (hwc
->config
| ARCH_PERFMON_EVENTSEL_ENABLE
));
110 perf_event_update_userpage(event
);
113 static void amd_uncore_stop(struct perf_event
*event
, int flags
)
115 struct hw_perf_event
*hwc
= &event
->hw
;
117 wrmsrl(hwc
->config_base
, hwc
->config
);
118 hwc
->state
|= PERF_HES_STOPPED
;
120 if ((flags
& PERF_EF_UPDATE
) && !(hwc
->state
& PERF_HES_UPTODATE
)) {
121 amd_uncore_read(event
);
122 hwc
->state
|= PERF_HES_UPTODATE
;
126 static int amd_uncore_add(struct perf_event
*event
, int flags
)
129 struct amd_uncore
*uncore
= event_to_amd_uncore(event
);
130 struct hw_perf_event
*hwc
= &event
->hw
;
132 /* are we already assigned? */
133 if (hwc
->idx
!= -1 && uncore
->events
[hwc
->idx
] == event
)
136 for (i
= 0; i
< uncore
->num_counters
; i
++) {
137 if (uncore
->events
[i
] == event
) {
143 /* if not, take the first available counter */
145 for (i
= 0; i
< uncore
->num_counters
; i
++) {
146 if (cmpxchg(&uncore
->events
[i
], NULL
, event
) == NULL
) {
156 hwc
->config_base
= uncore
->msr_base
+ (2 * hwc
->idx
);
157 hwc
->event_base
= uncore
->msr_base
+ 1 + (2 * hwc
->idx
);
158 hwc
->event_base_rdpmc
= uncore
->rdpmc_base
+ hwc
->idx
;
159 hwc
->state
= PERF_HES_UPTODATE
| PERF_HES_STOPPED
;
161 if (flags
& PERF_EF_START
)
162 amd_uncore_start(event
, PERF_EF_RELOAD
);
167 static void amd_uncore_del(struct perf_event
*event
, int flags
)
170 struct amd_uncore
*uncore
= event_to_amd_uncore(event
);
171 struct hw_perf_event
*hwc
= &event
->hw
;
173 amd_uncore_stop(event
, PERF_EF_UPDATE
);
175 for (i
= 0; i
< uncore
->num_counters
; i
++) {
176 if (cmpxchg(&uncore
->events
[i
], event
, NULL
) == event
)
183 static int amd_uncore_event_init(struct perf_event
*event
)
185 struct amd_uncore
*uncore
;
186 struct hw_perf_event
*hwc
= &event
->hw
;
188 if (event
->attr
.type
!= event
->pmu
->type
)
192 * NB and Last level cache counters (MSRs) are shared across all cores
193 * that share the same NB / Last level cache. Interrupts can be directed
194 * to a single target core, however, event counts generated by processes
195 * running on other cores cannot be masked out. So we do not support
196 * sampling and per-thread events.
198 if (is_sampling_event(event
) || event
->attach_state
& PERF_ATTACH_TASK
)
201 /* and we do not enable counter overflow interrupts */
202 hwc
->config
= event
->attr
.config
& AMD64_RAW_EVENT_MASK_NB
;
206 * SliceMask and ThreadMask need to be set for certain L3 events in
207 * Family 17h. For other events, the two fields do not affect the count.
210 hwc
->config
|= (AMD64_L3_SLICE_MASK
| AMD64_L3_THREAD_MASK
);
215 uncore
= event_to_amd_uncore(event
);
220 * since request can come in to any of the shared cores, we will remap
221 * to a single common cpu.
223 event
->cpu
= uncore
->cpu
;
228 static ssize_t
amd_uncore_attr_show_cpumask(struct device
*dev
,
229 struct device_attribute
*attr
,
232 cpumask_t
*active_mask
;
233 struct pmu
*pmu
= dev_get_drvdata(dev
);
235 if (pmu
->type
== amd_nb_pmu
.type
)
236 active_mask
= &amd_nb_active_mask
;
237 else if (pmu
->type
== amd_llc_pmu
.type
)
238 active_mask
= &amd_llc_active_mask
;
242 return cpumap_print_to_pagebuf(true, buf
, active_mask
);
244 static DEVICE_ATTR(cpumask
, S_IRUGO
, amd_uncore_attr_show_cpumask
, NULL
);
246 static struct attribute
*amd_uncore_attrs
[] = {
247 &dev_attr_cpumask
.attr
,
251 static struct attribute_group amd_uncore_attr_group
= {
252 .attrs
= amd_uncore_attrs
,
256 * Similar to PMU_FORMAT_ATTR but allowing for format_attr to be assigned based
259 #define AMD_FORMAT_ATTR(_dev, _name, _format) \
261 _dev##_show##_name(struct device *dev, \
262 struct device_attribute *attr, \
265 BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE); \
266 return sprintf(page, _format "\n"); \
268 static struct device_attribute format_attr_##_dev##_name = __ATTR_RO(_dev);
270 /* Used for each uncore counter type */
271 #define AMD_ATTRIBUTE(_name) \
272 static struct attribute *amd_uncore_format_attr_##_name[] = { \
273 &format_attr_event_##_name.attr, \
274 &format_attr_umask.attr, \
277 static struct attribute_group amd_uncore_format_group_##_name = { \
279 .attrs = amd_uncore_format_attr_##_name, \
281 static const struct attribute_group *amd_uncore_attr_groups_##_name[] = { \
282 &amd_uncore_attr_group, \
283 &amd_uncore_format_group_##_name, \
287 AMD_FORMAT_ATTR(event
, , "config:0-7,32-35");
288 AMD_FORMAT_ATTR(umask
, , "config:8-15");
289 AMD_FORMAT_ATTR(event
, _df
, "config:0-7,32-35,59-60");
290 AMD_FORMAT_ATTR(event
, _l3
, "config:0-7");
294 static struct pmu amd_nb_pmu
= {
295 .task_ctx_nr
= perf_invalid_context
,
296 .event_init
= amd_uncore_event_init
,
297 .add
= amd_uncore_add
,
298 .del
= amd_uncore_del
,
299 .start
= amd_uncore_start
,
300 .stop
= amd_uncore_stop
,
301 .read
= amd_uncore_read
,
302 .capabilities
= PERF_PMU_CAP_NO_EXCLUDE
,
305 static struct pmu amd_llc_pmu
= {
306 .task_ctx_nr
= perf_invalid_context
,
307 .event_init
= amd_uncore_event_init
,
308 .add
= amd_uncore_add
,
309 .del
= amd_uncore_del
,
310 .start
= amd_uncore_start
,
311 .stop
= amd_uncore_stop
,
312 .read
= amd_uncore_read
,
313 .capabilities
= PERF_PMU_CAP_NO_EXCLUDE
,
316 static struct amd_uncore
*amd_uncore_alloc(unsigned int cpu
)
318 return kzalloc_node(sizeof(struct amd_uncore
), GFP_KERNEL
,
322 static int amd_uncore_cpu_up_prepare(unsigned int cpu
)
324 struct amd_uncore
*uncore_nb
= NULL
, *uncore_llc
;
327 uncore_nb
= amd_uncore_alloc(cpu
);
330 uncore_nb
->cpu
= cpu
;
331 uncore_nb
->num_counters
= num_counters_nb
;
332 uncore_nb
->rdpmc_base
= RDPMC_BASE_NB
;
333 uncore_nb
->msr_base
= MSR_F15H_NB_PERF_CTL
;
334 uncore_nb
->active_mask
= &amd_nb_active_mask
;
335 uncore_nb
->pmu
= &amd_nb_pmu
;
337 *per_cpu_ptr(amd_uncore_nb
, cpu
) = uncore_nb
;
340 if (amd_uncore_llc
) {
341 uncore_llc
= amd_uncore_alloc(cpu
);
344 uncore_llc
->cpu
= cpu
;
345 uncore_llc
->num_counters
= num_counters_llc
;
346 uncore_llc
->rdpmc_base
= RDPMC_BASE_LLC
;
347 uncore_llc
->msr_base
= MSR_F16H_L2I_PERF_CTL
;
348 uncore_llc
->active_mask
= &amd_llc_active_mask
;
349 uncore_llc
->pmu
= &amd_llc_pmu
;
351 *per_cpu_ptr(amd_uncore_llc
, cpu
) = uncore_llc
;
358 *per_cpu_ptr(amd_uncore_nb
, cpu
) = NULL
;
363 static struct amd_uncore
*
364 amd_uncore_find_online_sibling(struct amd_uncore
*this,
365 struct amd_uncore
* __percpu
*uncores
)
368 struct amd_uncore
*that
;
370 for_each_online_cpu(cpu
) {
371 that
= *per_cpu_ptr(uncores
, cpu
);
379 if (this->id
== that
->id
) {
380 hlist_add_head(&this->node
, &uncore_unused_list
);
390 static int amd_uncore_cpu_starting(unsigned int cpu
)
392 unsigned int eax
, ebx
, ecx
, edx
;
393 struct amd_uncore
*uncore
;
396 uncore
= *per_cpu_ptr(amd_uncore_nb
, cpu
);
397 cpuid(0x8000001e, &eax
, &ebx
, &ecx
, &edx
);
398 uncore
->id
= ecx
& 0xff;
400 uncore
= amd_uncore_find_online_sibling(uncore
, amd_uncore_nb
);
401 *per_cpu_ptr(amd_uncore_nb
, cpu
) = uncore
;
404 if (amd_uncore_llc
) {
405 uncore
= *per_cpu_ptr(amd_uncore_llc
, cpu
);
406 uncore
->id
= per_cpu(cpu_llc_id
, cpu
);
408 uncore
= amd_uncore_find_online_sibling(uncore
, amd_uncore_llc
);
409 *per_cpu_ptr(amd_uncore_llc
, cpu
) = uncore
;
415 static void uncore_clean_online(void)
417 struct amd_uncore
*uncore
;
418 struct hlist_node
*n
;
420 hlist_for_each_entry_safe(uncore
, n
, &uncore_unused_list
, node
) {
421 hlist_del(&uncore
->node
);
426 static void uncore_online(unsigned int cpu
,
427 struct amd_uncore
* __percpu
*uncores
)
429 struct amd_uncore
*uncore
= *per_cpu_ptr(uncores
, cpu
);
431 uncore_clean_online();
433 if (cpu
== uncore
->cpu
)
434 cpumask_set_cpu(cpu
, uncore
->active_mask
);
437 static int amd_uncore_cpu_online(unsigned int cpu
)
440 uncore_online(cpu
, amd_uncore_nb
);
443 uncore_online(cpu
, amd_uncore_llc
);
448 static void uncore_down_prepare(unsigned int cpu
,
449 struct amd_uncore
* __percpu
*uncores
)
452 struct amd_uncore
*this = *per_cpu_ptr(uncores
, cpu
);
454 if (this->cpu
!= cpu
)
457 /* this cpu is going down, migrate to a shared sibling if possible */
458 for_each_online_cpu(i
) {
459 struct amd_uncore
*that
= *per_cpu_ptr(uncores
, i
);
465 perf_pmu_migrate_context(this->pmu
, cpu
, i
);
466 cpumask_clear_cpu(cpu
, that
->active_mask
);
467 cpumask_set_cpu(i
, that
->active_mask
);
474 static int amd_uncore_cpu_down_prepare(unsigned int cpu
)
477 uncore_down_prepare(cpu
, amd_uncore_nb
);
480 uncore_down_prepare(cpu
, amd_uncore_llc
);
485 static void uncore_dead(unsigned int cpu
, struct amd_uncore
* __percpu
*uncores
)
487 struct amd_uncore
*uncore
= *per_cpu_ptr(uncores
, cpu
);
489 if (cpu
== uncore
->cpu
)
490 cpumask_clear_cpu(cpu
, uncore
->active_mask
);
492 if (!--uncore
->refcnt
)
494 *per_cpu_ptr(uncores
, cpu
) = NULL
;
497 static int amd_uncore_cpu_dead(unsigned int cpu
)
500 uncore_dead(cpu
, amd_uncore_nb
);
503 uncore_dead(cpu
, amd_uncore_llc
);
508 static int __init
amd_uncore_init(void)
512 if (boot_cpu_data
.x86_vendor
!= X86_VENDOR_AMD
&&
513 boot_cpu_data
.x86_vendor
!= X86_VENDOR_HYGON
)
516 if (!boot_cpu_has(X86_FEATURE_TOPOEXT
))
519 if (boot_cpu_data
.x86
== 0x17 || boot_cpu_data
.x86
== 0x18) {
521 * For F17h or F18h, the Northbridge counters are
522 * repurposed as Data Fabric counters. Also, L3
523 * counters are supported too. The PMUs are exported
524 * based on family as either L2 or L3 and NB or DF.
526 num_counters_nb
= NUM_COUNTERS_NB
;
527 num_counters_llc
= NUM_COUNTERS_L3
;
528 amd_nb_pmu
.name
= "amd_df";
529 amd_llc_pmu
.name
= "amd_l3";
530 format_attr_event_df
.show
= &event_show_df
;
531 format_attr_event_l3
.show
= &event_show_l3
;
534 num_counters_nb
= NUM_COUNTERS_NB
;
535 num_counters_llc
= NUM_COUNTERS_L2
;
536 amd_nb_pmu
.name
= "amd_nb";
537 amd_llc_pmu
.name
= "amd_l2";
538 format_attr_event_df
= format_attr_event
;
539 format_attr_event_l3
= format_attr_event
;
543 amd_nb_pmu
.attr_groups
= amd_uncore_attr_groups_df
;
544 amd_llc_pmu
.attr_groups
= amd_uncore_attr_groups_l3
;
546 if (boot_cpu_has(X86_FEATURE_PERFCTR_NB
)) {
547 amd_uncore_nb
= alloc_percpu(struct amd_uncore
*);
548 if (!amd_uncore_nb
) {
552 ret
= perf_pmu_register(&amd_nb_pmu
, amd_nb_pmu
.name
, -1);
556 pr_info("%s NB counters detected\n",
557 boot_cpu_data
.x86_vendor
== X86_VENDOR_HYGON
?
562 if (boot_cpu_has(X86_FEATURE_PERFCTR_LLC
)) {
563 amd_uncore_llc
= alloc_percpu(struct amd_uncore
*);
564 if (!amd_uncore_llc
) {
568 ret
= perf_pmu_register(&amd_llc_pmu
, amd_llc_pmu
.name
, -1);
572 pr_info("%s LLC counters detected\n",
573 boot_cpu_data
.x86_vendor
== X86_VENDOR_HYGON
?
579 * Install callbacks. Core will call them for each online cpu.
581 if (cpuhp_setup_state(CPUHP_PERF_X86_AMD_UNCORE_PREP
,
582 "perf/x86/amd/uncore:prepare",
583 amd_uncore_cpu_up_prepare
, amd_uncore_cpu_dead
))
586 if (cpuhp_setup_state(CPUHP_AP_PERF_X86_AMD_UNCORE_STARTING
,
587 "perf/x86/amd/uncore:starting",
588 amd_uncore_cpu_starting
, NULL
))
590 if (cpuhp_setup_state(CPUHP_AP_PERF_X86_AMD_UNCORE_ONLINE
,
591 "perf/x86/amd/uncore:online",
592 amd_uncore_cpu_online
,
593 amd_uncore_cpu_down_prepare
))
598 cpuhp_remove_state(CPUHP_AP_PERF_X86_AMD_UNCORE_STARTING
);
600 cpuhp_remove_state(CPUHP_PERF_X86_AMD_UNCORE_PREP
);
602 if (boot_cpu_has(X86_FEATURE_PERFCTR_NB
))
603 perf_pmu_unregister(&amd_nb_pmu
);
605 free_percpu(amd_uncore_llc
);
608 free_percpu(amd_uncore_nb
);
612 device_initcall(amd_uncore_init
);