2 * Copyright (C) 2013 Advanced Micro Devices, Inc.
4 * Author: Jacob Shin <jacob.shin@amd.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/perf_event.h>
12 #include <linux/percpu.h>
13 #include <linux/types.h>
14 #include <linux/slab.h>
15 #include <linux/init.h>
16 #include <linux/cpu.h>
17 #include <linux/cpumask.h>
19 #include <asm/cpufeature.h>
20 #include <asm/perf_event.h>
23 #define NUM_COUNTERS_NB 4
24 #define NUM_COUNTERS_L2 4
25 #define NUM_COUNTERS_L3 6
26 #define MAX_COUNTERS 6
28 #define RDPMC_BASE_NB 6
29 #define RDPMC_BASE_LLC 10
31 #define COUNTER_SHIFT 16
33 static int num_counters_llc
;
34 static int num_counters_nb
;
36 static HLIST_HEAD(uncore_unused_list
);
45 cpumask_t
*active_mask
;
47 struct perf_event
*events
[MAX_COUNTERS
];
48 struct hlist_node node
;
51 static struct amd_uncore
* __percpu
*amd_uncore_nb
;
52 static struct amd_uncore
* __percpu
*amd_uncore_llc
;
54 static struct pmu amd_nb_pmu
;
55 static struct pmu amd_llc_pmu
;
57 static cpumask_t amd_nb_active_mask
;
58 static cpumask_t amd_llc_active_mask
;
60 static bool is_nb_event(struct perf_event
*event
)
62 return event
->pmu
->type
== amd_nb_pmu
.type
;
65 static bool is_llc_event(struct perf_event
*event
)
67 return event
->pmu
->type
== amd_llc_pmu
.type
;
70 static struct amd_uncore
*event_to_amd_uncore(struct perf_event
*event
)
72 if (is_nb_event(event
) && amd_uncore_nb
)
73 return *per_cpu_ptr(amd_uncore_nb
, event
->cpu
);
74 else if (is_llc_event(event
) && amd_uncore_llc
)
75 return *per_cpu_ptr(amd_uncore_llc
, event
->cpu
);
80 static void amd_uncore_read(struct perf_event
*event
)
82 struct hw_perf_event
*hwc
= &event
->hw
;
87 * since we do not enable counter overflow interrupts,
88 * we do not have to worry about prev_count changing on us
91 prev
= local64_read(&hwc
->prev_count
);
92 rdpmcl(hwc
->event_base_rdpmc
, new);
93 local64_set(&hwc
->prev_count
, new);
94 delta
= (new << COUNTER_SHIFT
) - (prev
<< COUNTER_SHIFT
);
95 delta
>>= COUNTER_SHIFT
;
96 local64_add(delta
, &event
->count
);
99 static void amd_uncore_start(struct perf_event
*event
, int flags
)
101 struct hw_perf_event
*hwc
= &event
->hw
;
103 if (flags
& PERF_EF_RELOAD
)
104 wrmsrl(hwc
->event_base
, (u64
)local64_read(&hwc
->prev_count
));
107 wrmsrl(hwc
->config_base
, (hwc
->config
| ARCH_PERFMON_EVENTSEL_ENABLE
));
108 perf_event_update_userpage(event
);
111 static void amd_uncore_stop(struct perf_event
*event
, int flags
)
113 struct hw_perf_event
*hwc
= &event
->hw
;
115 wrmsrl(hwc
->config_base
, hwc
->config
);
116 hwc
->state
|= PERF_HES_STOPPED
;
118 if ((flags
& PERF_EF_UPDATE
) && !(hwc
->state
& PERF_HES_UPTODATE
)) {
119 amd_uncore_read(event
);
120 hwc
->state
|= PERF_HES_UPTODATE
;
124 static int amd_uncore_add(struct perf_event
*event
, int flags
)
127 struct amd_uncore
*uncore
= event_to_amd_uncore(event
);
128 struct hw_perf_event
*hwc
= &event
->hw
;
130 /* are we already assigned? */
131 if (hwc
->idx
!= -1 && uncore
->events
[hwc
->idx
] == event
)
134 for (i
= 0; i
< uncore
->num_counters
; i
++) {
135 if (uncore
->events
[i
] == event
) {
141 /* if not, take the first available counter */
143 for (i
= 0; i
< uncore
->num_counters
; i
++) {
144 if (cmpxchg(&uncore
->events
[i
], NULL
, event
) == NULL
) {
154 hwc
->config_base
= uncore
->msr_base
+ (2 * hwc
->idx
);
155 hwc
->event_base
= uncore
->msr_base
+ 1 + (2 * hwc
->idx
);
156 hwc
->event_base_rdpmc
= uncore
->rdpmc_base
+ hwc
->idx
;
157 hwc
->state
= PERF_HES_UPTODATE
| PERF_HES_STOPPED
;
159 if (flags
& PERF_EF_START
)
160 amd_uncore_start(event
, PERF_EF_RELOAD
);
165 static void amd_uncore_del(struct perf_event
*event
, int flags
)
168 struct amd_uncore
*uncore
= event_to_amd_uncore(event
);
169 struct hw_perf_event
*hwc
= &event
->hw
;
171 amd_uncore_stop(event
, PERF_EF_UPDATE
);
173 for (i
= 0; i
< uncore
->num_counters
; i
++) {
174 if (cmpxchg(&uncore
->events
[i
], event
, NULL
) == event
)
181 static int amd_uncore_event_init(struct perf_event
*event
)
183 struct amd_uncore
*uncore
;
184 struct hw_perf_event
*hwc
= &event
->hw
;
186 if (event
->attr
.type
!= event
->pmu
->type
)
190 * NB and Last level cache counters (MSRs) are shared across all cores
191 * that share the same NB / Last level cache. Interrupts can be directed
192 * to a single target core, however, event counts generated by processes
193 * running on other cores cannot be masked out. So we do not support
194 * sampling and per-thread events.
196 if (is_sampling_event(event
) || event
->attach_state
& PERF_ATTACH_TASK
)
199 /* NB and Last level cache counters do not have usr/os/guest/host bits */
200 if (event
->attr
.exclude_user
|| event
->attr
.exclude_kernel
||
201 event
->attr
.exclude_host
|| event
->attr
.exclude_guest
)
204 /* and we do not enable counter overflow interrupts */
205 hwc
->config
= event
->attr
.config
& AMD64_RAW_EVENT_MASK_NB
;
211 uncore
= event_to_amd_uncore(event
);
216 * since request can come in to any of the shared cores, we will remap
217 * to a single common cpu.
219 event
->cpu
= uncore
->cpu
;
224 static ssize_t
amd_uncore_attr_show_cpumask(struct device
*dev
,
225 struct device_attribute
*attr
,
228 cpumask_t
*active_mask
;
229 struct pmu
*pmu
= dev_get_drvdata(dev
);
231 if (pmu
->type
== amd_nb_pmu
.type
)
232 active_mask
= &amd_nb_active_mask
;
233 else if (pmu
->type
== amd_llc_pmu
.type
)
234 active_mask
= &amd_llc_active_mask
;
238 return cpumap_print_to_pagebuf(true, buf
, active_mask
);
240 static DEVICE_ATTR(cpumask
, S_IRUGO
, amd_uncore_attr_show_cpumask
, NULL
);
242 static struct attribute
*amd_uncore_attrs
[] = {
243 &dev_attr_cpumask
.attr
,
247 static struct attribute_group amd_uncore_attr_group
= {
248 .attrs
= amd_uncore_attrs
,
252 * Similar to PMU_FORMAT_ATTR but allowing for format_attr to be assigned based
255 #define AMD_FORMAT_ATTR(_dev, _name, _format) \
257 _dev##_show##_name(struct device *dev, \
258 struct device_attribute *attr, \
261 BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE); \
262 return sprintf(page, _format "\n"); \
264 static struct device_attribute format_attr_##_dev##_name = __ATTR_RO(_dev);
266 /* Used for each uncore counter type */
267 #define AMD_ATTRIBUTE(_name) \
268 static struct attribute *amd_uncore_format_attr_##_name[] = { \
269 &format_attr_event_##_name.attr, \
270 &format_attr_umask.attr, \
273 static struct attribute_group amd_uncore_format_group_##_name = { \
275 .attrs = amd_uncore_format_attr_##_name, \
277 static const struct attribute_group *amd_uncore_attr_groups_##_name[] = { \
278 &amd_uncore_attr_group, \
279 &amd_uncore_format_group_##_name, \
283 AMD_FORMAT_ATTR(event
, , "config:0-7,32-35");
284 AMD_FORMAT_ATTR(umask
, , "config:8-15");
285 AMD_FORMAT_ATTR(event
, _df
, "config:0-7,32-35,59-60");
286 AMD_FORMAT_ATTR(event
, _l3
, "config:0-7");
290 static struct pmu amd_nb_pmu
= {
291 .task_ctx_nr
= perf_invalid_context
,
292 .event_init
= amd_uncore_event_init
,
293 .add
= amd_uncore_add
,
294 .del
= amd_uncore_del
,
295 .start
= amd_uncore_start
,
296 .stop
= amd_uncore_stop
,
297 .read
= amd_uncore_read
,
300 static struct pmu amd_llc_pmu
= {
301 .task_ctx_nr
= perf_invalid_context
,
302 .event_init
= amd_uncore_event_init
,
303 .add
= amd_uncore_add
,
304 .del
= amd_uncore_del
,
305 .start
= amd_uncore_start
,
306 .stop
= amd_uncore_stop
,
307 .read
= amd_uncore_read
,
310 static struct amd_uncore
*amd_uncore_alloc(unsigned int cpu
)
312 return kzalloc_node(sizeof(struct amd_uncore
), GFP_KERNEL
,
316 static int amd_uncore_cpu_up_prepare(unsigned int cpu
)
318 struct amd_uncore
*uncore_nb
= NULL
, *uncore_llc
;
321 uncore_nb
= amd_uncore_alloc(cpu
);
324 uncore_nb
->cpu
= cpu
;
325 uncore_nb
->num_counters
= num_counters_nb
;
326 uncore_nb
->rdpmc_base
= RDPMC_BASE_NB
;
327 uncore_nb
->msr_base
= MSR_F15H_NB_PERF_CTL
;
328 uncore_nb
->active_mask
= &amd_nb_active_mask
;
329 uncore_nb
->pmu
= &amd_nb_pmu
;
331 *per_cpu_ptr(amd_uncore_nb
, cpu
) = uncore_nb
;
334 if (amd_uncore_llc
) {
335 uncore_llc
= amd_uncore_alloc(cpu
);
338 uncore_llc
->cpu
= cpu
;
339 uncore_llc
->num_counters
= num_counters_llc
;
340 uncore_llc
->rdpmc_base
= RDPMC_BASE_LLC
;
341 uncore_llc
->msr_base
= MSR_F16H_L2I_PERF_CTL
;
342 uncore_llc
->active_mask
= &amd_llc_active_mask
;
343 uncore_llc
->pmu
= &amd_llc_pmu
;
345 *per_cpu_ptr(amd_uncore_llc
, cpu
) = uncore_llc
;
352 *per_cpu_ptr(amd_uncore_nb
, cpu
) = NULL
;
357 static struct amd_uncore
*
358 amd_uncore_find_online_sibling(struct amd_uncore
*this,
359 struct amd_uncore
* __percpu
*uncores
)
362 struct amd_uncore
*that
;
364 for_each_online_cpu(cpu
) {
365 that
= *per_cpu_ptr(uncores
, cpu
);
373 if (this->id
== that
->id
) {
374 hlist_add_head(&this->node
, &uncore_unused_list
);
384 static int amd_uncore_cpu_starting(unsigned int cpu
)
386 unsigned int eax
, ebx
, ecx
, edx
;
387 struct amd_uncore
*uncore
;
390 uncore
= *per_cpu_ptr(amd_uncore_nb
, cpu
);
391 cpuid(0x8000001e, &eax
, &ebx
, &ecx
, &edx
);
392 uncore
->id
= ecx
& 0xff;
394 uncore
= amd_uncore_find_online_sibling(uncore
, amd_uncore_nb
);
395 *per_cpu_ptr(amd_uncore_nb
, cpu
) = uncore
;
398 if (amd_uncore_llc
) {
399 unsigned int apicid
= cpu_data(cpu
).apicid
;
400 unsigned int nshared
;
402 uncore
= *per_cpu_ptr(amd_uncore_llc
, cpu
);
403 cpuid_count(0x8000001d, 2, &eax
, &ebx
, &ecx
, &edx
);
404 nshared
= ((eax
>> 14) & 0xfff) + 1;
405 uncore
->id
= apicid
- (apicid
% nshared
);
407 uncore
= amd_uncore_find_online_sibling(uncore
, amd_uncore_llc
);
408 *per_cpu_ptr(amd_uncore_llc
, cpu
) = uncore
;
414 static void uncore_clean_online(void)
416 struct amd_uncore
*uncore
;
417 struct hlist_node
*n
;
419 hlist_for_each_entry_safe(uncore
, n
, &uncore_unused_list
, node
) {
420 hlist_del(&uncore
->node
);
425 static void uncore_online(unsigned int cpu
,
426 struct amd_uncore
* __percpu
*uncores
)
428 struct amd_uncore
*uncore
= *per_cpu_ptr(uncores
, cpu
);
430 uncore_clean_online();
432 if (cpu
== uncore
->cpu
)
433 cpumask_set_cpu(cpu
, uncore
->active_mask
);
436 static int amd_uncore_cpu_online(unsigned int cpu
)
439 uncore_online(cpu
, amd_uncore_nb
);
442 uncore_online(cpu
, amd_uncore_llc
);
447 static void uncore_down_prepare(unsigned int cpu
,
448 struct amd_uncore
* __percpu
*uncores
)
451 struct amd_uncore
*this = *per_cpu_ptr(uncores
, cpu
);
453 if (this->cpu
!= cpu
)
456 /* this cpu is going down, migrate to a shared sibling if possible */
457 for_each_online_cpu(i
) {
458 struct amd_uncore
*that
= *per_cpu_ptr(uncores
, i
);
464 perf_pmu_migrate_context(this->pmu
, cpu
, i
);
465 cpumask_clear_cpu(cpu
, that
->active_mask
);
466 cpumask_set_cpu(i
, that
->active_mask
);
473 static int amd_uncore_cpu_down_prepare(unsigned int cpu
)
476 uncore_down_prepare(cpu
, amd_uncore_nb
);
479 uncore_down_prepare(cpu
, amd_uncore_llc
);
484 static void uncore_dead(unsigned int cpu
, struct amd_uncore
* __percpu
*uncores
)
486 struct amd_uncore
*uncore
= *per_cpu_ptr(uncores
, cpu
);
488 if (cpu
== uncore
->cpu
)
489 cpumask_clear_cpu(cpu
, uncore
->active_mask
);
491 if (!--uncore
->refcnt
)
493 *per_cpu_ptr(uncores
, cpu
) = NULL
;
496 static int amd_uncore_cpu_dead(unsigned int cpu
)
499 uncore_dead(cpu
, amd_uncore_nb
);
502 uncore_dead(cpu
, amd_uncore_llc
);
507 static int __init
amd_uncore_init(void)
511 if (boot_cpu_data
.x86_vendor
!= X86_VENDOR_AMD
)
514 switch(boot_cpu_data
.x86
) {
517 num_counters_nb
= NUM_COUNTERS_NB
;
518 num_counters_llc
= NUM_COUNTERS_L3
;
520 * For Family17h, the NorthBridge counters are
521 * re-purposed as Data Fabric counters. Also, support is
522 * added for L3 counters. The pmus are exported based on
523 * family as either L2 or L3 and NB or DF.
525 amd_nb_pmu
.name
= "amd_df";
526 amd_llc_pmu
.name
= "amd_l3";
527 format_attr_event_df
.show
= &event_show_df
;
528 format_attr_event_l3
.show
= &event_show_l3
;
531 /* Family 16h - may change: */
532 num_counters_nb
= NUM_COUNTERS_NB
;
533 num_counters_llc
= NUM_COUNTERS_L2
;
534 amd_nb_pmu
.name
= "amd_nb";
535 amd_llc_pmu
.name
= "amd_l2";
536 format_attr_event_df
= format_attr_event
;
537 format_attr_event_l3
= format_attr_event
;
541 * All prior families have the same number of
542 * NorthBridge and Last Level Cache counters
544 num_counters_nb
= NUM_COUNTERS_NB
;
545 num_counters_llc
= NUM_COUNTERS_L2
;
546 amd_nb_pmu
.name
= "amd_nb";
547 amd_llc_pmu
.name
= "amd_l2";
548 format_attr_event_df
= format_attr_event
;
549 format_attr_event_l3
= format_attr_event
;
552 amd_nb_pmu
.attr_groups
= amd_uncore_attr_groups_df
;
553 amd_llc_pmu
.attr_groups
= amd_uncore_attr_groups_l3
;
555 if (!boot_cpu_has(X86_FEATURE_TOPOEXT
))
558 if (boot_cpu_has(X86_FEATURE_PERFCTR_NB
)) {
559 amd_uncore_nb
= alloc_percpu(struct amd_uncore
*);
560 if (!amd_uncore_nb
) {
564 ret
= perf_pmu_register(&amd_nb_pmu
, amd_nb_pmu
.name
, -1);
568 pr_info("perf: AMD NB counters detected\n");
572 if (boot_cpu_has(X86_FEATURE_PERFCTR_L2
)) {
573 amd_uncore_llc
= alloc_percpu(struct amd_uncore
*);
574 if (!amd_uncore_llc
) {
578 ret
= perf_pmu_register(&amd_llc_pmu
, amd_llc_pmu
.name
, -1);
582 pr_info("perf: AMD LLC counters detected\n");
587 * Install callbacks. Core will call them for each online cpu.
589 if (cpuhp_setup_state(CPUHP_PERF_X86_AMD_UNCORE_PREP
,
590 "perf/x86/amd/uncore:prepare",
591 amd_uncore_cpu_up_prepare
, amd_uncore_cpu_dead
))
594 if (cpuhp_setup_state(CPUHP_AP_PERF_X86_AMD_UNCORE_STARTING
,
595 "perf/x86/amd/uncore:starting",
596 amd_uncore_cpu_starting
, NULL
))
598 if (cpuhp_setup_state(CPUHP_AP_PERF_X86_AMD_UNCORE_ONLINE
,
599 "perf/x86/amd/uncore:online",
600 amd_uncore_cpu_online
,
601 amd_uncore_cpu_down_prepare
))
606 cpuhp_remove_state(CPUHP_AP_PERF_X86_AMD_UNCORE_STARTING
);
608 cpuhp_remove_state(CPUHP_PERF_X86_AMD_UNCORE_PREP
);
610 if (boot_cpu_has(X86_FEATURE_PERFCTR_NB
))
611 perf_pmu_unregister(&amd_nb_pmu
);
613 free_percpu(amd_uncore_llc
);
616 free_percpu(amd_uncore_nb
);
621 device_initcall(amd_uncore_init
);