2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/export.h>
21 #include <linux/init.h>
22 #include <linux/kdebug.h>
23 #include <linux/sched.h>
24 #include <linux/uaccess.h>
25 #include <linux/slab.h>
26 #include <linux/cpu.h>
27 #include <linux/bitops.h>
28 #include <linux/device.h>
31 #include <asm/stacktrace.h>
34 #include <asm/alternative.h>
35 #include <asm/mmu_context.h>
36 #include <asm/tlbflush.h>
37 #include <asm/timer.h>
40 #include <asm/unwind.h>
42 #include "perf_event.h"
44 struct x86_pmu x86_pmu __read_mostly
;
46 DEFINE_PER_CPU(struct cpu_hw_events
, cpu_hw_events
) = {
50 struct static_key rdpmc_always_available
= STATIC_KEY_INIT_FALSE
;
52 u64 __read_mostly hw_cache_event_ids
53 [PERF_COUNT_HW_CACHE_MAX
]
54 [PERF_COUNT_HW_CACHE_OP_MAX
]
55 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
56 u64 __read_mostly hw_cache_extra_regs
57 [PERF_COUNT_HW_CACHE_MAX
]
58 [PERF_COUNT_HW_CACHE_OP_MAX
]
59 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
62 * Propagate event elapsed time into the generic event.
63 * Can only be executed on the CPU where the event is active.
64 * Returns the delta events processed.
66 u64
x86_perf_event_update(struct perf_event
*event
)
68 struct hw_perf_event
*hwc
= &event
->hw
;
69 int shift
= 64 - x86_pmu
.cntval_bits
;
70 u64 prev_raw_count
, new_raw_count
;
74 if (idx
== INTEL_PMC_IDX_FIXED_BTS
)
78 * Careful: an NMI might modify the previous event value.
80 * Our tactic to handle this is to first atomically read and
81 * exchange a new raw count - then add that new-prev delta
82 * count to the generic event atomically:
85 prev_raw_count
= local64_read(&hwc
->prev_count
);
86 rdpmcl(hwc
->event_base_rdpmc
, new_raw_count
);
88 if (local64_cmpxchg(&hwc
->prev_count
, prev_raw_count
,
89 new_raw_count
) != prev_raw_count
)
93 * Now we have the new raw value and have updated the prev
94 * timestamp already. We can now calculate the elapsed delta
95 * (event-)time and add that to the generic event.
97 * Careful, not all hw sign-extends above the physical width
100 delta
= (new_raw_count
<< shift
) - (prev_raw_count
<< shift
);
103 local64_add(delta
, &event
->count
);
104 local64_sub(delta
, &hwc
->period_left
);
106 return new_raw_count
;
110 * Find and validate any extra registers to set up.
112 static int x86_pmu_extra_regs(u64 config
, struct perf_event
*event
)
114 struct hw_perf_event_extra
*reg
;
115 struct extra_reg
*er
;
117 reg
= &event
->hw
.extra_reg
;
119 if (!x86_pmu
.extra_regs
)
122 for (er
= x86_pmu
.extra_regs
; er
->msr
; er
++) {
123 if (er
->event
!= (config
& er
->config_mask
))
125 if (event
->attr
.config1
& ~er
->valid_mask
)
127 /* Check if the extra msrs can be safely accessed*/
128 if (!er
->extra_msr_access
)
132 reg
->config
= event
->attr
.config1
;
139 static atomic_t active_events
;
140 static atomic_t pmc_refcount
;
141 static DEFINE_MUTEX(pmc_reserve_mutex
);
143 #ifdef CONFIG_X86_LOCAL_APIC
145 static bool reserve_pmc_hardware(void)
149 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
150 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i
)))
154 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
155 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i
)))
162 for (i
--; i
>= 0; i
--)
163 release_evntsel_nmi(x86_pmu_config_addr(i
));
165 i
= x86_pmu
.num_counters
;
168 for (i
--; i
>= 0; i
--)
169 release_perfctr_nmi(x86_pmu_event_addr(i
));
174 static void release_pmc_hardware(void)
178 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
179 release_perfctr_nmi(x86_pmu_event_addr(i
));
180 release_evntsel_nmi(x86_pmu_config_addr(i
));
186 static bool reserve_pmc_hardware(void) { return true; }
187 static void release_pmc_hardware(void) {}
191 static bool check_hw_exists(void)
193 u64 val
, val_fail
, val_new
= ~0;
194 int i
, reg
, reg_fail
, ret
= 0;
199 * Check to see if the BIOS enabled any of the counters, if so
202 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
203 reg
= x86_pmu_config_addr(i
);
204 ret
= rdmsrl_safe(reg
, &val
);
207 if (val
& ARCH_PERFMON_EVENTSEL_ENABLE
) {
216 if (x86_pmu
.num_counters_fixed
) {
217 reg
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
218 ret
= rdmsrl_safe(reg
, &val
);
221 for (i
= 0; i
< x86_pmu
.num_counters_fixed
; i
++) {
222 if (val
& (0x03 << i
*4)) {
231 * If all the counters are enabled, the below test will always
232 * fail. The tools will also become useless in this scenario.
233 * Just fail and disable the hardware counters.
236 if (reg_safe
== -1) {
242 * Read the current value, change it and read it back to see if it
243 * matches, this is needed to detect certain hardware emulators
244 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
246 reg
= x86_pmu_event_addr(reg_safe
);
247 if (rdmsrl_safe(reg
, &val
))
250 ret
= wrmsrl_safe(reg
, val
);
251 ret
|= rdmsrl_safe(reg
, &val_new
);
252 if (ret
|| val
!= val_new
)
256 * We still allow the PMU driver to operate:
259 pr_cont("Broken BIOS detected, complain to your hardware vendor.\n");
260 pr_err(FW_BUG
"the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n",
267 if (boot_cpu_has(X86_FEATURE_HYPERVISOR
)) {
268 pr_cont("PMU not available due to virtualization, using software events only.\n");
270 pr_cont("Broken PMU hardware detected, using software events only.\n");
271 pr_err("Failed to access perfctr msr (MSR %x is %Lx)\n",
278 static void hw_perf_event_destroy(struct perf_event
*event
)
280 x86_release_hardware();
281 atomic_dec(&active_events
);
284 void hw_perf_lbr_event_destroy(struct perf_event
*event
)
286 hw_perf_event_destroy(event
);
288 /* undo the lbr/bts event accounting */
289 x86_del_exclusive(x86_lbr_exclusive_lbr
);
292 static inline int x86_pmu_initialized(void)
294 return x86_pmu
.handle_irq
!= NULL
;
298 set_ext_hw_attr(struct hw_perf_event
*hwc
, struct perf_event
*event
)
300 struct perf_event_attr
*attr
= &event
->attr
;
301 unsigned int cache_type
, cache_op
, cache_result
;
304 config
= attr
->config
;
306 cache_type
= (config
>> 0) & 0xff;
307 if (cache_type
>= PERF_COUNT_HW_CACHE_MAX
)
310 cache_op
= (config
>> 8) & 0xff;
311 if (cache_op
>= PERF_COUNT_HW_CACHE_OP_MAX
)
314 cache_result
= (config
>> 16) & 0xff;
315 if (cache_result
>= PERF_COUNT_HW_CACHE_RESULT_MAX
)
318 val
= hw_cache_event_ids
[cache_type
][cache_op
][cache_result
];
327 attr
->config1
= hw_cache_extra_regs
[cache_type
][cache_op
][cache_result
];
328 return x86_pmu_extra_regs(val
, event
);
331 int x86_reserve_hardware(void)
335 if (!atomic_inc_not_zero(&pmc_refcount
)) {
336 mutex_lock(&pmc_reserve_mutex
);
337 if (atomic_read(&pmc_refcount
) == 0) {
338 if (!reserve_pmc_hardware())
341 reserve_ds_buffers();
344 atomic_inc(&pmc_refcount
);
345 mutex_unlock(&pmc_reserve_mutex
);
351 void x86_release_hardware(void)
353 if (atomic_dec_and_mutex_lock(&pmc_refcount
, &pmc_reserve_mutex
)) {
354 release_pmc_hardware();
355 release_ds_buffers();
356 mutex_unlock(&pmc_reserve_mutex
);
361 * Check if we can create event of a certain type (that no conflicting events
364 int x86_add_exclusive(unsigned int what
)
369 * When lbr_pt_coexist we allow PT to coexist with either LBR or BTS.
370 * LBR and BTS are still mutually exclusive.
372 if (x86_pmu
.lbr_pt_coexist
&& what
== x86_lbr_exclusive_pt
)
375 if (!atomic_inc_not_zero(&x86_pmu
.lbr_exclusive
[what
])) {
376 mutex_lock(&pmc_reserve_mutex
);
377 for (i
= 0; i
< ARRAY_SIZE(x86_pmu
.lbr_exclusive
); i
++) {
378 if (i
!= what
&& atomic_read(&x86_pmu
.lbr_exclusive
[i
]))
381 atomic_inc(&x86_pmu
.lbr_exclusive
[what
]);
382 mutex_unlock(&pmc_reserve_mutex
);
385 atomic_inc(&active_events
);
389 mutex_unlock(&pmc_reserve_mutex
);
393 void x86_del_exclusive(unsigned int what
)
395 if (x86_pmu
.lbr_pt_coexist
&& what
== x86_lbr_exclusive_pt
)
398 atomic_dec(&x86_pmu
.lbr_exclusive
[what
]);
399 atomic_dec(&active_events
);
402 int x86_setup_perfctr(struct perf_event
*event
)
404 struct perf_event_attr
*attr
= &event
->attr
;
405 struct hw_perf_event
*hwc
= &event
->hw
;
408 if (!is_sampling_event(event
)) {
409 hwc
->sample_period
= x86_pmu
.max_period
;
410 hwc
->last_period
= hwc
->sample_period
;
411 local64_set(&hwc
->period_left
, hwc
->sample_period
);
414 if (attr
->type
== PERF_TYPE_RAW
)
415 return x86_pmu_extra_regs(event
->attr
.config
, event
);
417 if (attr
->type
== PERF_TYPE_HW_CACHE
)
418 return set_ext_hw_attr(hwc
, event
);
420 if (attr
->config
>= x86_pmu
.max_events
)
426 config
= x86_pmu
.event_map(attr
->config
);
437 if (attr
->config
== PERF_COUNT_HW_BRANCH_INSTRUCTIONS
&&
438 !attr
->freq
&& hwc
->sample_period
== 1) {
439 /* BTS is not supported by this architecture. */
440 if (!x86_pmu
.bts_active
)
443 /* BTS is currently only allowed for user-mode. */
444 if (!attr
->exclude_kernel
)
447 /* disallow bts if conflicting events are present */
448 if (x86_add_exclusive(x86_lbr_exclusive_lbr
))
451 event
->destroy
= hw_perf_lbr_event_destroy
;
454 hwc
->config
|= config
;
460 * check that branch_sample_type is compatible with
461 * settings needed for precise_ip > 1 which implies
462 * using the LBR to capture ALL taken branches at the
463 * priv levels of the measurement
465 static inline int precise_br_compat(struct perf_event
*event
)
467 u64 m
= event
->attr
.branch_sample_type
;
470 /* must capture all branches */
471 if (!(m
& PERF_SAMPLE_BRANCH_ANY
))
474 m
&= PERF_SAMPLE_BRANCH_KERNEL
| PERF_SAMPLE_BRANCH_USER
;
476 if (!event
->attr
.exclude_user
)
477 b
|= PERF_SAMPLE_BRANCH_USER
;
479 if (!event
->attr
.exclude_kernel
)
480 b
|= PERF_SAMPLE_BRANCH_KERNEL
;
483 * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
489 int x86_pmu_hw_config(struct perf_event
*event
)
491 if (event
->attr
.precise_ip
) {
494 /* Support for constant skid */
495 if (x86_pmu
.pebs_active
&& !x86_pmu
.pebs_broken
) {
498 /* Support for IP fixup */
499 if (x86_pmu
.lbr_nr
|| x86_pmu
.intel_cap
.pebs_format
>= 2)
502 if (x86_pmu
.pebs_prec_dist
)
506 if (event
->attr
.precise_ip
> precise
)
509 /* There's no sense in having PEBS for non sampling events: */
510 if (!is_sampling_event(event
))
514 * check that PEBS LBR correction does not conflict with
515 * whatever the user is asking with attr->branch_sample_type
517 if (event
->attr
.precise_ip
> 1 && x86_pmu
.intel_cap
.pebs_format
< 2) {
518 u64
*br_type
= &event
->attr
.branch_sample_type
;
520 if (has_branch_stack(event
)) {
521 if (!precise_br_compat(event
))
524 /* branch_sample_type is compatible */
528 * user did not specify branch_sample_type
530 * For PEBS fixups, we capture all
531 * the branches at the priv level of the
534 *br_type
= PERF_SAMPLE_BRANCH_ANY
;
536 if (!event
->attr
.exclude_user
)
537 *br_type
|= PERF_SAMPLE_BRANCH_USER
;
539 if (!event
->attr
.exclude_kernel
)
540 *br_type
|= PERF_SAMPLE_BRANCH_KERNEL
;
544 if (event
->attr
.branch_sample_type
& PERF_SAMPLE_BRANCH_CALL_STACK
)
545 event
->attach_state
|= PERF_ATTACH_TASK_DATA
;
549 * (keep 'enabled' bit clear for now)
551 event
->hw
.config
= ARCH_PERFMON_EVENTSEL_INT
;
554 * Count user and OS events unless requested not to
556 if (!event
->attr
.exclude_user
)
557 event
->hw
.config
|= ARCH_PERFMON_EVENTSEL_USR
;
558 if (!event
->attr
.exclude_kernel
)
559 event
->hw
.config
|= ARCH_PERFMON_EVENTSEL_OS
;
561 if (event
->attr
.type
== PERF_TYPE_RAW
)
562 event
->hw
.config
|= event
->attr
.config
& X86_RAW_EVENT_MASK
;
564 if (event
->attr
.sample_period
&& x86_pmu
.limit_period
) {
565 if (x86_pmu
.limit_period(event
, event
->attr
.sample_period
) >
566 event
->attr
.sample_period
)
570 return x86_setup_perfctr(event
);
574 * Setup the hardware configuration for a given attr_type
576 static int __x86_pmu_event_init(struct perf_event
*event
)
580 if (!x86_pmu_initialized())
583 err
= x86_reserve_hardware();
587 atomic_inc(&active_events
);
588 event
->destroy
= hw_perf_event_destroy
;
591 event
->hw
.last_cpu
= -1;
592 event
->hw
.last_tag
= ~0ULL;
595 event
->hw
.extra_reg
.idx
= EXTRA_REG_NONE
;
596 event
->hw
.branch_reg
.idx
= EXTRA_REG_NONE
;
598 return x86_pmu
.hw_config(event
);
601 void x86_pmu_disable_all(void)
603 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
606 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
609 if (!test_bit(idx
, cpuc
->active_mask
))
611 rdmsrl(x86_pmu_config_addr(idx
), val
);
612 if (!(val
& ARCH_PERFMON_EVENTSEL_ENABLE
))
614 val
&= ~ARCH_PERFMON_EVENTSEL_ENABLE
;
615 wrmsrl(x86_pmu_config_addr(idx
), val
);
620 * There may be PMI landing after enabled=0. The PMI hitting could be before or
623 * If PMI hits before disable_all, the PMU will be disabled in the NMI handler.
624 * It will not be re-enabled in the NMI handler again, because enabled=0. After
625 * handling the NMI, disable_all will be called, which will not change the
626 * state either. If PMI hits after disable_all, the PMU is already disabled
627 * before entering NMI handler. The NMI handler will not change the state
630 * So either situation is harmless.
632 static void x86_pmu_disable(struct pmu
*pmu
)
634 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
636 if (!x86_pmu_initialized())
646 x86_pmu
.disable_all();
649 void x86_pmu_enable_all(int added
)
651 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
654 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
655 struct hw_perf_event
*hwc
= &cpuc
->events
[idx
]->hw
;
657 if (!test_bit(idx
, cpuc
->active_mask
))
660 __x86_pmu_enable_event(hwc
, ARCH_PERFMON_EVENTSEL_ENABLE
);
664 static struct pmu pmu
;
666 static inline int is_x86_event(struct perf_event
*event
)
668 return event
->pmu
== &pmu
;
672 * Event scheduler state:
674 * Assign events iterating over all events and counters, beginning
675 * with events with least weights first. Keep the current iterator
676 * state in struct sched_state.
680 int event
; /* event index */
681 int counter
; /* counter index */
682 int unassigned
; /* number of events to be assigned left */
683 int nr_gp
; /* number of GP counters used */
684 unsigned long used
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
687 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
688 #define SCHED_STATES_MAX 2
695 struct event_constraint
**constraints
;
696 struct sched_state state
;
697 struct sched_state saved
[SCHED_STATES_MAX
];
701 * Initialize interator that runs through all events and counters.
703 static void perf_sched_init(struct perf_sched
*sched
, struct event_constraint
**constraints
,
704 int num
, int wmin
, int wmax
, int gpmax
)
708 memset(sched
, 0, sizeof(*sched
));
709 sched
->max_events
= num
;
710 sched
->max_weight
= wmax
;
711 sched
->max_gp
= gpmax
;
712 sched
->constraints
= constraints
;
714 for (idx
= 0; idx
< num
; idx
++) {
715 if (constraints
[idx
]->weight
== wmin
)
719 sched
->state
.event
= idx
; /* start with min weight */
720 sched
->state
.weight
= wmin
;
721 sched
->state
.unassigned
= num
;
724 static void perf_sched_save_state(struct perf_sched
*sched
)
726 if (WARN_ON_ONCE(sched
->saved_states
>= SCHED_STATES_MAX
))
729 sched
->saved
[sched
->saved_states
] = sched
->state
;
730 sched
->saved_states
++;
733 static bool perf_sched_restore_state(struct perf_sched
*sched
)
735 if (!sched
->saved_states
)
738 sched
->saved_states
--;
739 sched
->state
= sched
->saved
[sched
->saved_states
];
741 /* continue with next counter: */
742 clear_bit(sched
->state
.counter
++, sched
->state
.used
);
748 * Select a counter for the current event to schedule. Return true on
751 static bool __perf_sched_find_counter(struct perf_sched
*sched
)
753 struct event_constraint
*c
;
756 if (!sched
->state
.unassigned
)
759 if (sched
->state
.event
>= sched
->max_events
)
762 c
= sched
->constraints
[sched
->state
.event
];
763 /* Prefer fixed purpose counters */
764 if (c
->idxmsk64
& (~0ULL << INTEL_PMC_IDX_FIXED
)) {
765 idx
= INTEL_PMC_IDX_FIXED
;
766 for_each_set_bit_from(idx
, c
->idxmsk
, X86_PMC_IDX_MAX
) {
767 if (!__test_and_set_bit(idx
, sched
->state
.used
))
772 /* Grab the first unused counter starting with idx */
773 idx
= sched
->state
.counter
;
774 for_each_set_bit_from(idx
, c
->idxmsk
, INTEL_PMC_IDX_FIXED
) {
775 if (!__test_and_set_bit(idx
, sched
->state
.used
)) {
776 if (sched
->state
.nr_gp
++ >= sched
->max_gp
)
786 sched
->state
.counter
= idx
;
789 perf_sched_save_state(sched
);
794 static bool perf_sched_find_counter(struct perf_sched
*sched
)
796 while (!__perf_sched_find_counter(sched
)) {
797 if (!perf_sched_restore_state(sched
))
805 * Go through all unassigned events and find the next one to schedule.
806 * Take events with the least weight first. Return true on success.
808 static bool perf_sched_next_event(struct perf_sched
*sched
)
810 struct event_constraint
*c
;
812 if (!sched
->state
.unassigned
|| !--sched
->state
.unassigned
)
817 sched
->state
.event
++;
818 if (sched
->state
.event
>= sched
->max_events
) {
820 sched
->state
.event
= 0;
821 sched
->state
.weight
++;
822 if (sched
->state
.weight
> sched
->max_weight
)
825 c
= sched
->constraints
[sched
->state
.event
];
826 } while (c
->weight
!= sched
->state
.weight
);
828 sched
->state
.counter
= 0; /* start with first counter */
834 * Assign a counter for each event.
836 int perf_assign_events(struct event_constraint
**constraints
, int n
,
837 int wmin
, int wmax
, int gpmax
, int *assign
)
839 struct perf_sched sched
;
841 perf_sched_init(&sched
, constraints
, n
, wmin
, wmax
, gpmax
);
844 if (!perf_sched_find_counter(&sched
))
847 assign
[sched
.state
.event
] = sched
.state
.counter
;
848 } while (perf_sched_next_event(&sched
));
850 return sched
.state
.unassigned
;
852 EXPORT_SYMBOL_GPL(perf_assign_events
);
854 int x86_schedule_events(struct cpu_hw_events
*cpuc
, int n
, int *assign
)
856 struct event_constraint
*c
;
857 unsigned long used_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
858 struct perf_event
*e
;
859 int i
, wmin
, wmax
, unsched
= 0;
860 struct hw_perf_event
*hwc
;
862 bitmap_zero(used_mask
, X86_PMC_IDX_MAX
);
864 if (x86_pmu
.start_scheduling
)
865 x86_pmu
.start_scheduling(cpuc
);
867 for (i
= 0, wmin
= X86_PMC_IDX_MAX
, wmax
= 0; i
< n
; i
++) {
868 cpuc
->event_constraint
[i
] = NULL
;
869 c
= x86_pmu
.get_event_constraints(cpuc
, i
, cpuc
->event_list
[i
]);
870 cpuc
->event_constraint
[i
] = c
;
872 wmin
= min(wmin
, c
->weight
);
873 wmax
= max(wmax
, c
->weight
);
877 * fastpath, try to reuse previous register
879 for (i
= 0; i
< n
; i
++) {
880 hwc
= &cpuc
->event_list
[i
]->hw
;
881 c
= cpuc
->event_constraint
[i
];
887 /* constraint still honored */
888 if (!test_bit(hwc
->idx
, c
->idxmsk
))
891 /* not already used */
892 if (test_bit(hwc
->idx
, used_mask
))
895 __set_bit(hwc
->idx
, used_mask
);
897 assign
[i
] = hwc
->idx
;
902 int gpmax
= x86_pmu
.num_counters
;
905 * Do not allow scheduling of more than half the available
908 * This helps avoid counter starvation of sibling thread by
909 * ensuring at most half the counters cannot be in exclusive
910 * mode. There is no designated counters for the limits. Any
911 * N/2 counters can be used. This helps with events with
912 * specific counter constraints.
914 if (is_ht_workaround_enabled() && !cpuc
->is_fake
&&
915 READ_ONCE(cpuc
->excl_cntrs
->exclusive_present
))
918 unsched
= perf_assign_events(cpuc
->event_constraint
, n
, wmin
,
919 wmax
, gpmax
, assign
);
923 * In case of success (unsched = 0), mark events as committed,
924 * so we do not put_constraint() in case new events are added
925 * and fail to be scheduled
927 * We invoke the lower level commit callback to lock the resource
929 * We do not need to do all of this in case we are called to
930 * validate an event group (assign == NULL)
932 if (!unsched
&& assign
) {
933 for (i
= 0; i
< n
; i
++) {
934 e
= cpuc
->event_list
[i
];
935 e
->hw
.flags
|= PERF_X86_EVENT_COMMITTED
;
936 if (x86_pmu
.commit_scheduling
)
937 x86_pmu
.commit_scheduling(cpuc
, i
, assign
[i
]);
940 for (i
= 0; i
< n
; i
++) {
941 e
= cpuc
->event_list
[i
];
943 * do not put_constraint() on comitted events,
944 * because they are good to go
946 if ((e
->hw
.flags
& PERF_X86_EVENT_COMMITTED
))
950 * release events that failed scheduling
952 if (x86_pmu
.put_event_constraints
)
953 x86_pmu
.put_event_constraints(cpuc
, e
);
957 if (x86_pmu
.stop_scheduling
)
958 x86_pmu
.stop_scheduling(cpuc
);
960 return unsched
? -EINVAL
: 0;
964 * dogrp: true if must collect siblings events (group)
965 * returns total number of events and error code
967 static int collect_events(struct cpu_hw_events
*cpuc
, struct perf_event
*leader
, bool dogrp
)
969 struct perf_event
*event
;
972 max_count
= x86_pmu
.num_counters
+ x86_pmu
.num_counters_fixed
;
974 /* current number of events already accepted */
977 if (is_x86_event(leader
)) {
980 cpuc
->event_list
[n
] = leader
;
986 list_for_each_entry(event
, &leader
->sibling_list
, group_entry
) {
987 if (!is_x86_event(event
) ||
988 event
->state
<= PERF_EVENT_STATE_OFF
)
994 cpuc
->event_list
[n
] = event
;
1000 static inline void x86_assign_hw_event(struct perf_event
*event
,
1001 struct cpu_hw_events
*cpuc
, int i
)
1003 struct hw_perf_event
*hwc
= &event
->hw
;
1005 hwc
->idx
= cpuc
->assign
[i
];
1006 hwc
->last_cpu
= smp_processor_id();
1007 hwc
->last_tag
= ++cpuc
->tags
[i
];
1009 if (hwc
->idx
== INTEL_PMC_IDX_FIXED_BTS
) {
1010 hwc
->config_base
= 0;
1011 hwc
->event_base
= 0;
1012 } else if (hwc
->idx
>= INTEL_PMC_IDX_FIXED
) {
1013 hwc
->config_base
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
1014 hwc
->event_base
= MSR_ARCH_PERFMON_FIXED_CTR0
+ (hwc
->idx
- INTEL_PMC_IDX_FIXED
);
1015 hwc
->event_base_rdpmc
= (hwc
->idx
- INTEL_PMC_IDX_FIXED
) | 1<<30;
1017 hwc
->config_base
= x86_pmu_config_addr(hwc
->idx
);
1018 hwc
->event_base
= x86_pmu_event_addr(hwc
->idx
);
1019 hwc
->event_base_rdpmc
= x86_pmu_rdpmc_index(hwc
->idx
);
1023 static inline int match_prev_assignment(struct hw_perf_event
*hwc
,
1024 struct cpu_hw_events
*cpuc
,
1027 return hwc
->idx
== cpuc
->assign
[i
] &&
1028 hwc
->last_cpu
== smp_processor_id() &&
1029 hwc
->last_tag
== cpuc
->tags
[i
];
1032 static void x86_pmu_start(struct perf_event
*event
, int flags
);
1034 static void x86_pmu_enable(struct pmu
*pmu
)
1036 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1037 struct perf_event
*event
;
1038 struct hw_perf_event
*hwc
;
1039 int i
, added
= cpuc
->n_added
;
1041 if (!x86_pmu_initialized())
1047 if (cpuc
->n_added
) {
1048 int n_running
= cpuc
->n_events
- cpuc
->n_added
;
1050 * apply assignment obtained either from
1051 * hw_perf_group_sched_in() or x86_pmu_enable()
1053 * step1: save events moving to new counters
1055 for (i
= 0; i
< n_running
; i
++) {
1056 event
= cpuc
->event_list
[i
];
1060 * we can avoid reprogramming counter if:
1061 * - assigned same counter as last time
1062 * - running on same CPU as last time
1063 * - no other event has used the counter since
1065 if (hwc
->idx
== -1 ||
1066 match_prev_assignment(hwc
, cpuc
, i
))
1070 * Ensure we don't accidentally enable a stopped
1071 * counter simply because we rescheduled.
1073 if (hwc
->state
& PERF_HES_STOPPED
)
1074 hwc
->state
|= PERF_HES_ARCH
;
1076 x86_pmu_stop(event
, PERF_EF_UPDATE
);
1080 * step2: reprogram moved events into new counters
1082 for (i
= 0; i
< cpuc
->n_events
; i
++) {
1083 event
= cpuc
->event_list
[i
];
1086 if (!match_prev_assignment(hwc
, cpuc
, i
))
1087 x86_assign_hw_event(event
, cpuc
, i
);
1088 else if (i
< n_running
)
1091 if (hwc
->state
& PERF_HES_ARCH
)
1094 x86_pmu_start(event
, PERF_EF_RELOAD
);
1097 perf_events_lapic_init();
1103 x86_pmu
.enable_all(added
);
1106 static DEFINE_PER_CPU(u64
[X86_PMC_IDX_MAX
], pmc_prev_left
);
1109 * Set the next IRQ period, based on the hwc->period_left value.
1110 * To be called with the event disabled in hw:
1112 int x86_perf_event_set_period(struct perf_event
*event
)
1114 struct hw_perf_event
*hwc
= &event
->hw
;
1115 s64 left
= local64_read(&hwc
->period_left
);
1116 s64 period
= hwc
->sample_period
;
1117 int ret
= 0, idx
= hwc
->idx
;
1119 if (idx
== INTEL_PMC_IDX_FIXED_BTS
)
1123 * If we are way outside a reasonable range then just skip forward:
1125 if (unlikely(left
<= -period
)) {
1127 local64_set(&hwc
->period_left
, left
);
1128 hwc
->last_period
= period
;
1132 if (unlikely(left
<= 0)) {
1134 local64_set(&hwc
->period_left
, left
);
1135 hwc
->last_period
= period
;
1139 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1141 if (unlikely(left
< 2))
1144 if (left
> x86_pmu
.max_period
)
1145 left
= x86_pmu
.max_period
;
1147 if (x86_pmu
.limit_period
)
1148 left
= x86_pmu
.limit_period(event
, left
);
1150 per_cpu(pmc_prev_left
[idx
], smp_processor_id()) = left
;
1152 if (!(hwc
->flags
& PERF_X86_EVENT_AUTO_RELOAD
) ||
1153 local64_read(&hwc
->prev_count
) != (u64
)-left
) {
1155 * The hw event starts counting from this event offset,
1156 * mark it to be able to extra future deltas:
1158 local64_set(&hwc
->prev_count
, (u64
)-left
);
1160 wrmsrl(hwc
->event_base
, (u64
)(-left
) & x86_pmu
.cntval_mask
);
1164 * Due to erratum on certan cpu we need
1165 * a second write to be sure the register
1166 * is updated properly
1168 if (x86_pmu
.perfctr_second_write
) {
1169 wrmsrl(hwc
->event_base
,
1170 (u64
)(-left
) & x86_pmu
.cntval_mask
);
1173 perf_event_update_userpage(event
);
1178 void x86_pmu_enable_event(struct perf_event
*event
)
1180 if (__this_cpu_read(cpu_hw_events
.enabled
))
1181 __x86_pmu_enable_event(&event
->hw
,
1182 ARCH_PERFMON_EVENTSEL_ENABLE
);
1186 * Add a single event to the PMU.
1188 * The event is added to the group of enabled events
1189 * but only if it can be scehduled with existing events.
1191 static int x86_pmu_add(struct perf_event
*event
, int flags
)
1193 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1194 struct hw_perf_event
*hwc
;
1195 int assign
[X86_PMC_IDX_MAX
];
1200 n0
= cpuc
->n_events
;
1201 ret
= n
= collect_events(cpuc
, event
, false);
1205 hwc
->state
= PERF_HES_UPTODATE
| PERF_HES_STOPPED
;
1206 if (!(flags
& PERF_EF_START
))
1207 hwc
->state
|= PERF_HES_ARCH
;
1210 * If group events scheduling transaction was started,
1211 * skip the schedulability test here, it will be performed
1212 * at commit time (->commit_txn) as a whole.
1214 * If commit fails, we'll call ->del() on all events
1215 * for which ->add() was called.
1217 if (cpuc
->txn_flags
& PERF_PMU_TXN_ADD
)
1220 ret
= x86_pmu
.schedule_events(cpuc
, n
, assign
);
1224 * copy new assignment, now we know it is possible
1225 * will be used by hw_perf_enable()
1227 memcpy(cpuc
->assign
, assign
, n
*sizeof(int));
1231 * Commit the collect_events() state. See x86_pmu_del() and
1235 cpuc
->n_added
+= n
- n0
;
1236 cpuc
->n_txn
+= n
- n0
;
1240 * This is before x86_pmu_enable() will call x86_pmu_start(),
1241 * so we enable LBRs before an event needs them etc..
1251 static void x86_pmu_start(struct perf_event
*event
, int flags
)
1253 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1254 int idx
= event
->hw
.idx
;
1256 if (WARN_ON_ONCE(!(event
->hw
.state
& PERF_HES_STOPPED
)))
1259 if (WARN_ON_ONCE(idx
== -1))
1262 if (flags
& PERF_EF_RELOAD
) {
1263 WARN_ON_ONCE(!(event
->hw
.state
& PERF_HES_UPTODATE
));
1264 x86_perf_event_set_period(event
);
1267 event
->hw
.state
= 0;
1269 cpuc
->events
[idx
] = event
;
1270 __set_bit(idx
, cpuc
->active_mask
);
1271 __set_bit(idx
, cpuc
->running
);
1272 x86_pmu
.enable(event
);
1273 perf_event_update_userpage(event
);
1276 void perf_event_print_debug(void)
1278 u64 ctrl
, status
, overflow
, pmc_ctrl
, pmc_count
, prev_left
, fixed
;
1280 struct cpu_hw_events
*cpuc
;
1281 unsigned long flags
;
1284 if (!x86_pmu
.num_counters
)
1287 local_irq_save(flags
);
1289 cpu
= smp_processor_id();
1290 cpuc
= &per_cpu(cpu_hw_events
, cpu
);
1292 if (x86_pmu
.version
>= 2) {
1293 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
1294 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
1295 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, overflow
);
1296 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL
, fixed
);
1299 pr_info("CPU#%d: ctrl: %016llx\n", cpu
, ctrl
);
1300 pr_info("CPU#%d: status: %016llx\n", cpu
, status
);
1301 pr_info("CPU#%d: overflow: %016llx\n", cpu
, overflow
);
1302 pr_info("CPU#%d: fixed: %016llx\n", cpu
, fixed
);
1303 if (x86_pmu
.pebs_constraints
) {
1304 rdmsrl(MSR_IA32_PEBS_ENABLE
, pebs
);
1305 pr_info("CPU#%d: pebs: %016llx\n", cpu
, pebs
);
1307 if (x86_pmu
.lbr_nr
) {
1308 rdmsrl(MSR_IA32_DEBUGCTLMSR
, debugctl
);
1309 pr_info("CPU#%d: debugctl: %016llx\n", cpu
, debugctl
);
1312 pr_info("CPU#%d: active: %016llx\n", cpu
, *(u64
*)cpuc
->active_mask
);
1314 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1315 rdmsrl(x86_pmu_config_addr(idx
), pmc_ctrl
);
1316 rdmsrl(x86_pmu_event_addr(idx
), pmc_count
);
1318 prev_left
= per_cpu(pmc_prev_left
[idx
], cpu
);
1320 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1321 cpu
, idx
, pmc_ctrl
);
1322 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1323 cpu
, idx
, pmc_count
);
1324 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1325 cpu
, idx
, prev_left
);
1327 for (idx
= 0; idx
< x86_pmu
.num_counters_fixed
; idx
++) {
1328 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0
+ idx
, pmc_count
);
1330 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1331 cpu
, idx
, pmc_count
);
1333 local_irq_restore(flags
);
1336 void x86_pmu_stop(struct perf_event
*event
, int flags
)
1338 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1339 struct hw_perf_event
*hwc
= &event
->hw
;
1341 if (__test_and_clear_bit(hwc
->idx
, cpuc
->active_mask
)) {
1342 x86_pmu
.disable(event
);
1343 cpuc
->events
[hwc
->idx
] = NULL
;
1344 WARN_ON_ONCE(hwc
->state
& PERF_HES_STOPPED
);
1345 hwc
->state
|= PERF_HES_STOPPED
;
1348 if ((flags
& PERF_EF_UPDATE
) && !(hwc
->state
& PERF_HES_UPTODATE
)) {
1350 * Drain the remaining delta count out of a event
1351 * that we are disabling:
1353 x86_perf_event_update(event
);
1354 hwc
->state
|= PERF_HES_UPTODATE
;
1358 static void x86_pmu_del(struct perf_event
*event
, int flags
)
1360 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1364 * event is descheduled
1366 event
->hw
.flags
&= ~PERF_X86_EVENT_COMMITTED
;
1369 * If we're called during a txn, we only need to undo x86_pmu.add.
1370 * The events never got scheduled and ->cancel_txn will truncate
1373 * XXX assumes any ->del() called during a TXN will only be on
1374 * an event added during that same TXN.
1376 if (cpuc
->txn_flags
& PERF_PMU_TXN_ADD
)
1380 * Not a TXN, therefore cleanup properly.
1382 x86_pmu_stop(event
, PERF_EF_UPDATE
);
1384 for (i
= 0; i
< cpuc
->n_events
; i
++) {
1385 if (event
== cpuc
->event_list
[i
])
1389 if (WARN_ON_ONCE(i
== cpuc
->n_events
)) /* called ->del() without ->add() ? */
1392 /* If we have a newly added event; make sure to decrease n_added. */
1393 if (i
>= cpuc
->n_events
- cpuc
->n_added
)
1396 if (x86_pmu
.put_event_constraints
)
1397 x86_pmu
.put_event_constraints(cpuc
, event
);
1399 /* Delete the array entry. */
1400 while (++i
< cpuc
->n_events
) {
1401 cpuc
->event_list
[i
-1] = cpuc
->event_list
[i
];
1402 cpuc
->event_constraint
[i
-1] = cpuc
->event_constraint
[i
];
1406 perf_event_update_userpage(event
);
1411 * This is after x86_pmu_stop(); so we disable LBRs after any
1412 * event can need them etc..
1418 int x86_pmu_handle_irq(struct pt_regs
*regs
)
1420 struct perf_sample_data data
;
1421 struct cpu_hw_events
*cpuc
;
1422 struct perf_event
*event
;
1423 int idx
, handled
= 0;
1426 cpuc
= this_cpu_ptr(&cpu_hw_events
);
1429 * Some chipsets need to unmask the LVTPC in a particular spot
1430 * inside the nmi handler. As a result, the unmasking was pushed
1431 * into all the nmi handlers.
1433 * This generic handler doesn't seem to have any issues where the
1434 * unmasking occurs so it was left at the top.
1436 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1438 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1439 if (!test_bit(idx
, cpuc
->active_mask
)) {
1441 * Though we deactivated the counter some cpus
1442 * might still deliver spurious interrupts still
1443 * in flight. Catch them:
1445 if (__test_and_clear_bit(idx
, cpuc
->running
))
1450 event
= cpuc
->events
[idx
];
1452 val
= x86_perf_event_update(event
);
1453 if (val
& (1ULL << (x86_pmu
.cntval_bits
- 1)))
1460 perf_sample_data_init(&data
, 0, event
->hw
.last_period
);
1462 if (!x86_perf_event_set_period(event
))
1465 if (perf_event_overflow(event
, &data
, regs
))
1466 x86_pmu_stop(event
, 0);
1470 inc_irq_stat(apic_perf_irqs
);
1475 void perf_events_lapic_init(void)
1477 if (!x86_pmu
.apic
|| !x86_pmu_initialized())
1481 * Always use NMI for PMU
1483 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1487 perf_event_nmi_handler(unsigned int cmd
, struct pt_regs
*regs
)
1494 * All PMUs/events that share this PMI handler should make sure to
1495 * increment active_events for their events.
1497 if (!atomic_read(&active_events
))
1500 start_clock
= sched_clock();
1501 ret
= x86_pmu
.handle_irq(regs
);
1502 finish_clock
= sched_clock();
1504 perf_sample_event_took(finish_clock
- start_clock
);
1508 NOKPROBE_SYMBOL(perf_event_nmi_handler
);
1510 struct event_constraint emptyconstraint
;
1511 struct event_constraint unconstrained
;
1513 static int x86_pmu_prepare_cpu(unsigned int cpu
)
1515 struct cpu_hw_events
*cpuc
= &per_cpu(cpu_hw_events
, cpu
);
1518 for (i
= 0 ; i
< X86_PERF_KFREE_MAX
; i
++)
1519 cpuc
->kfree_on_online
[i
] = NULL
;
1520 if (x86_pmu
.cpu_prepare
)
1521 return x86_pmu
.cpu_prepare(cpu
);
1525 static int x86_pmu_dead_cpu(unsigned int cpu
)
1527 if (x86_pmu
.cpu_dead
)
1528 x86_pmu
.cpu_dead(cpu
);
1532 static int x86_pmu_online_cpu(unsigned int cpu
)
1534 struct cpu_hw_events
*cpuc
= &per_cpu(cpu_hw_events
, cpu
);
1537 for (i
= 0 ; i
< X86_PERF_KFREE_MAX
; i
++) {
1538 kfree(cpuc
->kfree_on_online
[i
]);
1539 cpuc
->kfree_on_online
[i
] = NULL
;
1544 static int x86_pmu_starting_cpu(unsigned int cpu
)
1546 if (x86_pmu
.cpu_starting
)
1547 x86_pmu
.cpu_starting(cpu
);
1551 static int x86_pmu_dying_cpu(unsigned int cpu
)
1553 if (x86_pmu
.cpu_dying
)
1554 x86_pmu
.cpu_dying(cpu
);
1558 static void __init
pmu_check_apic(void)
1560 if (boot_cpu_has(X86_FEATURE_APIC
))
1564 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1565 pr_info("no hardware sampling interrupt available.\n");
1568 * If we have a PMU initialized but no APIC
1569 * interrupts, we cannot sample hardware
1570 * events (user-space has to fall back and
1571 * sample via a hrtimer based software event):
1573 pmu
.capabilities
|= PERF_PMU_CAP_NO_INTERRUPT
;
1577 static struct attribute_group x86_pmu_format_group
= {
1583 * Remove all undefined events (x86_pmu.event_map(id) == 0)
1584 * out of events_attr attributes.
1586 static void __init
filter_events(struct attribute
**attrs
)
1588 struct device_attribute
*d
;
1589 struct perf_pmu_events_attr
*pmu_attr
;
1593 for (i
= 0; attrs
[i
]; i
++) {
1594 d
= (struct device_attribute
*)attrs
[i
];
1595 pmu_attr
= container_of(d
, struct perf_pmu_events_attr
, attr
);
1597 if (pmu_attr
->event_str
)
1599 if (x86_pmu
.event_map(i
+ offset
))
1602 for (j
= i
; attrs
[j
]; j
++)
1603 attrs
[j
] = attrs
[j
+ 1];
1605 /* Check the shifted attr. */
1609 * event_map() is index based, the attrs array is organized
1610 * by increasing event index. If we shift the events, then
1611 * we need to compensate for the event_map(), otherwise
1612 * we are looking up the wrong event in the map
1618 /* Merge two pointer arrays */
1619 __init
struct attribute
**merge_attr(struct attribute
**a
, struct attribute
**b
)
1621 struct attribute
**new;
1624 for (j
= 0; a
[j
]; j
++)
1626 for (i
= 0; b
[i
]; i
++)
1630 new = kmalloc(sizeof(struct attribute
*) * j
, GFP_KERNEL
);
1635 for (i
= 0; a
[i
]; i
++)
1637 for (i
= 0; b
[i
]; i
++)
1644 ssize_t
events_sysfs_show(struct device
*dev
, struct device_attribute
*attr
, char *page
)
1646 struct perf_pmu_events_attr
*pmu_attr
= \
1647 container_of(attr
, struct perf_pmu_events_attr
, attr
);
1648 u64 config
= x86_pmu
.event_map(pmu_attr
->id
);
1650 /* string trumps id */
1651 if (pmu_attr
->event_str
)
1652 return sprintf(page
, "%s", pmu_attr
->event_str
);
1654 return x86_pmu
.events_sysfs_show(page
, config
);
1656 EXPORT_SYMBOL_GPL(events_sysfs_show
);
1658 ssize_t
events_ht_sysfs_show(struct device
*dev
, struct device_attribute
*attr
,
1661 struct perf_pmu_events_ht_attr
*pmu_attr
=
1662 container_of(attr
, struct perf_pmu_events_ht_attr
, attr
);
1665 * Report conditional events depending on Hyper-Threading.
1667 * This is overly conservative as usually the HT special
1668 * handling is not needed if the other CPU thread is idle.
1670 * Note this does not (and cannot) handle the case when thread
1671 * siblings are invisible, for example with virtualization
1672 * if they are owned by some other guest. The user tool
1673 * has to re-read when a thread sibling gets onlined later.
1675 return sprintf(page
, "%s",
1676 topology_max_smt_threads() > 1 ?
1677 pmu_attr
->event_str_ht
:
1678 pmu_attr
->event_str_noht
);
1681 EVENT_ATTR(cpu
-cycles
, CPU_CYCLES
);
1682 EVENT_ATTR(instructions
, INSTRUCTIONS
);
1683 EVENT_ATTR(cache
-references
, CACHE_REFERENCES
);
1684 EVENT_ATTR(cache
-misses
, CACHE_MISSES
);
1685 EVENT_ATTR(branch
-instructions
, BRANCH_INSTRUCTIONS
);
1686 EVENT_ATTR(branch
-misses
, BRANCH_MISSES
);
1687 EVENT_ATTR(bus
-cycles
, BUS_CYCLES
);
1688 EVENT_ATTR(stalled
-cycles
-frontend
, STALLED_CYCLES_FRONTEND
);
1689 EVENT_ATTR(stalled
-cycles
-backend
, STALLED_CYCLES_BACKEND
);
1690 EVENT_ATTR(ref
-cycles
, REF_CPU_CYCLES
);
1692 static struct attribute
*empty_attrs
;
1694 static struct attribute
*events_attr
[] = {
1695 EVENT_PTR(CPU_CYCLES
),
1696 EVENT_PTR(INSTRUCTIONS
),
1697 EVENT_PTR(CACHE_REFERENCES
),
1698 EVENT_PTR(CACHE_MISSES
),
1699 EVENT_PTR(BRANCH_INSTRUCTIONS
),
1700 EVENT_PTR(BRANCH_MISSES
),
1701 EVENT_PTR(BUS_CYCLES
),
1702 EVENT_PTR(STALLED_CYCLES_FRONTEND
),
1703 EVENT_PTR(STALLED_CYCLES_BACKEND
),
1704 EVENT_PTR(REF_CPU_CYCLES
),
1708 static struct attribute_group x86_pmu_events_group
= {
1710 .attrs
= events_attr
,
1713 ssize_t
x86_event_sysfs_show(char *page
, u64 config
, u64 event
)
1715 u64 umask
= (config
& ARCH_PERFMON_EVENTSEL_UMASK
) >> 8;
1716 u64 cmask
= (config
& ARCH_PERFMON_EVENTSEL_CMASK
) >> 24;
1717 bool edge
= (config
& ARCH_PERFMON_EVENTSEL_EDGE
);
1718 bool pc
= (config
& ARCH_PERFMON_EVENTSEL_PIN_CONTROL
);
1719 bool any
= (config
& ARCH_PERFMON_EVENTSEL_ANY
);
1720 bool inv
= (config
& ARCH_PERFMON_EVENTSEL_INV
);
1724 * We have whole page size to spend and just little data
1725 * to write, so we can safely use sprintf.
1727 ret
= sprintf(page
, "event=0x%02llx", event
);
1730 ret
+= sprintf(page
+ ret
, ",umask=0x%02llx", umask
);
1733 ret
+= sprintf(page
+ ret
, ",edge");
1736 ret
+= sprintf(page
+ ret
, ",pc");
1739 ret
+= sprintf(page
+ ret
, ",any");
1742 ret
+= sprintf(page
+ ret
, ",inv");
1745 ret
+= sprintf(page
+ ret
, ",cmask=0x%02llx", cmask
);
1747 ret
+= sprintf(page
+ ret
, "\n");
1752 static int __init
init_hw_perf_events(void)
1754 struct x86_pmu_quirk
*quirk
;
1757 pr_info("Performance Events: ");
1759 switch (boot_cpu_data
.x86_vendor
) {
1760 case X86_VENDOR_INTEL
:
1761 err
= intel_pmu_init();
1763 case X86_VENDOR_AMD
:
1764 err
= amd_pmu_init();
1770 pr_cont("no PMU driver, software events only.\n");
1776 /* sanity check that the hardware exists or is emulated */
1777 if (!check_hw_exists())
1780 pr_cont("%s PMU driver.\n", x86_pmu
.name
);
1782 x86_pmu
.attr_rdpmc
= 1; /* enable userspace RDPMC usage by default */
1784 for (quirk
= x86_pmu
.quirks
; quirk
; quirk
= quirk
->next
)
1787 if (!x86_pmu
.intel_ctrl
)
1788 x86_pmu
.intel_ctrl
= (1 << x86_pmu
.num_counters
) - 1;
1790 perf_events_lapic_init();
1791 register_nmi_handler(NMI_LOCAL
, perf_event_nmi_handler
, 0, "PMI");
1793 unconstrained
= (struct event_constraint
)
1794 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu
.num_counters
) - 1,
1795 0, x86_pmu
.num_counters
, 0, 0);
1797 x86_pmu_format_group
.attrs
= x86_pmu
.format_attrs
;
1799 if (x86_pmu
.event_attrs
)
1800 x86_pmu_events_group
.attrs
= x86_pmu
.event_attrs
;
1802 if (!x86_pmu
.events_sysfs_show
)
1803 x86_pmu_events_group
.attrs
= &empty_attrs
;
1805 filter_events(x86_pmu_events_group
.attrs
);
1807 if (x86_pmu
.cpu_events
) {
1808 struct attribute
**tmp
;
1810 tmp
= merge_attr(x86_pmu_events_group
.attrs
, x86_pmu
.cpu_events
);
1812 x86_pmu_events_group
.attrs
= tmp
;
1815 pr_info("... version: %d\n", x86_pmu
.version
);
1816 pr_info("... bit width: %d\n", x86_pmu
.cntval_bits
);
1817 pr_info("... generic registers: %d\n", x86_pmu
.num_counters
);
1818 pr_info("... value mask: %016Lx\n", x86_pmu
.cntval_mask
);
1819 pr_info("... max period: %016Lx\n", x86_pmu
.max_period
);
1820 pr_info("... fixed-purpose events: %d\n", x86_pmu
.num_counters_fixed
);
1821 pr_info("... event mask: %016Lx\n", x86_pmu
.intel_ctrl
);
1824 * Install callbacks. Core will call them for each online
1827 err
= cpuhp_setup_state(CPUHP_PERF_X86_PREPARE
, "perf/x86:prepare",
1828 x86_pmu_prepare_cpu
, x86_pmu_dead_cpu
);
1832 err
= cpuhp_setup_state(CPUHP_AP_PERF_X86_STARTING
,
1833 "perf/x86:starting", x86_pmu_starting_cpu
,
1838 err
= cpuhp_setup_state(CPUHP_AP_PERF_X86_ONLINE
, "perf/x86:online",
1839 x86_pmu_online_cpu
, NULL
);
1843 err
= perf_pmu_register(&pmu
, "cpu", PERF_TYPE_RAW
);
1850 cpuhp_remove_state(CPUHP_AP_PERF_X86_ONLINE
);
1852 cpuhp_remove_state(CPUHP_AP_PERF_X86_STARTING
);
1854 cpuhp_remove_state(CPUHP_PERF_X86_PREPARE
);
1857 early_initcall(init_hw_perf_events
);
1859 static inline void x86_pmu_read(struct perf_event
*event
)
1861 x86_perf_event_update(event
);
1865 * Start group events scheduling transaction
1866 * Set the flag to make pmu::enable() not perform the
1867 * schedulability test, it will be performed at commit time
1869 * We only support PERF_PMU_TXN_ADD transactions. Save the
1870 * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
1873 static void x86_pmu_start_txn(struct pmu
*pmu
, unsigned int txn_flags
)
1875 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1877 WARN_ON_ONCE(cpuc
->txn_flags
); /* txn already in flight */
1879 cpuc
->txn_flags
= txn_flags
;
1880 if (txn_flags
& ~PERF_PMU_TXN_ADD
)
1883 perf_pmu_disable(pmu
);
1884 __this_cpu_write(cpu_hw_events
.n_txn
, 0);
1888 * Stop group events scheduling transaction
1889 * Clear the flag and pmu::enable() will perform the
1890 * schedulability test.
1892 static void x86_pmu_cancel_txn(struct pmu
*pmu
)
1894 unsigned int txn_flags
;
1895 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1897 WARN_ON_ONCE(!cpuc
->txn_flags
); /* no txn in flight */
1899 txn_flags
= cpuc
->txn_flags
;
1900 cpuc
->txn_flags
= 0;
1901 if (txn_flags
& ~PERF_PMU_TXN_ADD
)
1905 * Truncate collected array by the number of events added in this
1906 * transaction. See x86_pmu_add() and x86_pmu_*_txn().
1908 __this_cpu_sub(cpu_hw_events
.n_added
, __this_cpu_read(cpu_hw_events
.n_txn
));
1909 __this_cpu_sub(cpu_hw_events
.n_events
, __this_cpu_read(cpu_hw_events
.n_txn
));
1910 perf_pmu_enable(pmu
);
1914 * Commit group events scheduling transaction
1915 * Perform the group schedulability test as a whole
1916 * Return 0 if success
1918 * Does not cancel the transaction on failure; expects the caller to do this.
1920 static int x86_pmu_commit_txn(struct pmu
*pmu
)
1922 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1923 int assign
[X86_PMC_IDX_MAX
];
1926 WARN_ON_ONCE(!cpuc
->txn_flags
); /* no txn in flight */
1928 if (cpuc
->txn_flags
& ~PERF_PMU_TXN_ADD
) {
1929 cpuc
->txn_flags
= 0;
1935 if (!x86_pmu_initialized())
1938 ret
= x86_pmu
.schedule_events(cpuc
, n
, assign
);
1943 * copy new assignment, now we know it is possible
1944 * will be used by hw_perf_enable()
1946 memcpy(cpuc
->assign
, assign
, n
*sizeof(int));
1948 cpuc
->txn_flags
= 0;
1949 perf_pmu_enable(pmu
);
1953 * a fake_cpuc is used to validate event groups. Due to
1954 * the extra reg logic, we need to also allocate a fake
1955 * per_core and per_cpu structure. Otherwise, group events
1956 * using extra reg may conflict without the kernel being
1957 * able to catch this when the last event gets added to
1960 static void free_fake_cpuc(struct cpu_hw_events
*cpuc
)
1962 kfree(cpuc
->shared_regs
);
1966 static struct cpu_hw_events
*allocate_fake_cpuc(void)
1968 struct cpu_hw_events
*cpuc
;
1969 int cpu
= raw_smp_processor_id();
1971 cpuc
= kzalloc(sizeof(*cpuc
), GFP_KERNEL
);
1973 return ERR_PTR(-ENOMEM
);
1975 /* only needed, if we have extra_regs */
1976 if (x86_pmu
.extra_regs
) {
1977 cpuc
->shared_regs
= allocate_shared_regs(cpu
);
1978 if (!cpuc
->shared_regs
)
1984 free_fake_cpuc(cpuc
);
1985 return ERR_PTR(-ENOMEM
);
1989 * validate that we can schedule this event
1991 static int validate_event(struct perf_event
*event
)
1993 struct cpu_hw_events
*fake_cpuc
;
1994 struct event_constraint
*c
;
1997 fake_cpuc
= allocate_fake_cpuc();
1998 if (IS_ERR(fake_cpuc
))
1999 return PTR_ERR(fake_cpuc
);
2001 c
= x86_pmu
.get_event_constraints(fake_cpuc
, -1, event
);
2003 if (!c
|| !c
->weight
)
2006 if (x86_pmu
.put_event_constraints
)
2007 x86_pmu
.put_event_constraints(fake_cpuc
, event
);
2009 free_fake_cpuc(fake_cpuc
);
2015 * validate a single event group
2017 * validation include:
2018 * - check events are compatible which each other
2019 * - events do not compete for the same counter
2020 * - number of events <= number of counters
2022 * validation ensures the group can be loaded onto the
2023 * PMU if it was the only group available.
2025 static int validate_group(struct perf_event
*event
)
2027 struct perf_event
*leader
= event
->group_leader
;
2028 struct cpu_hw_events
*fake_cpuc
;
2029 int ret
= -EINVAL
, n
;
2031 fake_cpuc
= allocate_fake_cpuc();
2032 if (IS_ERR(fake_cpuc
))
2033 return PTR_ERR(fake_cpuc
);
2035 * the event is not yet connected with its
2036 * siblings therefore we must first collect
2037 * existing siblings, then add the new event
2038 * before we can simulate the scheduling
2040 n
= collect_events(fake_cpuc
, leader
, true);
2044 fake_cpuc
->n_events
= n
;
2045 n
= collect_events(fake_cpuc
, event
, false);
2049 fake_cpuc
->n_events
= n
;
2051 ret
= x86_pmu
.schedule_events(fake_cpuc
, n
, NULL
);
2054 free_fake_cpuc(fake_cpuc
);
2058 static int x86_pmu_event_init(struct perf_event
*event
)
2063 switch (event
->attr
.type
) {
2065 case PERF_TYPE_HARDWARE
:
2066 case PERF_TYPE_HW_CACHE
:
2073 err
= __x86_pmu_event_init(event
);
2076 * we temporarily connect event to its pmu
2077 * such that validate_group() can classify
2078 * it as an x86 event using is_x86_event()
2083 if (event
->group_leader
!= event
)
2084 err
= validate_group(event
);
2086 err
= validate_event(event
);
2092 event
->destroy(event
);
2095 if (ACCESS_ONCE(x86_pmu
.attr_rdpmc
))
2096 event
->hw
.flags
|= PERF_X86_EVENT_RDPMC_ALLOWED
;
2101 static void refresh_pce(void *ignored
)
2104 load_mm_cr4(current
->mm
);
2107 static void x86_pmu_event_mapped(struct perf_event
*event
)
2109 if (!(event
->hw
.flags
& PERF_X86_EVENT_RDPMC_ALLOWED
))
2112 if (atomic_inc_return(¤t
->mm
->context
.perf_rdpmc_allowed
) == 1)
2113 on_each_cpu_mask(mm_cpumask(current
->mm
), refresh_pce
, NULL
, 1);
2116 static void x86_pmu_event_unmapped(struct perf_event
*event
)
2121 if (!(event
->hw
.flags
& PERF_X86_EVENT_RDPMC_ALLOWED
))
2124 if (atomic_dec_and_test(¤t
->mm
->context
.perf_rdpmc_allowed
))
2125 on_each_cpu_mask(mm_cpumask(current
->mm
), refresh_pce
, NULL
, 1);
2128 static int x86_pmu_event_idx(struct perf_event
*event
)
2130 int idx
= event
->hw
.idx
;
2132 if (!(event
->hw
.flags
& PERF_X86_EVENT_RDPMC_ALLOWED
))
2135 if (x86_pmu
.num_counters_fixed
&& idx
>= INTEL_PMC_IDX_FIXED
) {
2136 idx
-= INTEL_PMC_IDX_FIXED
;
2143 static ssize_t
get_attr_rdpmc(struct device
*cdev
,
2144 struct device_attribute
*attr
,
2147 return snprintf(buf
, 40, "%d\n", x86_pmu
.attr_rdpmc
);
2150 static ssize_t
set_attr_rdpmc(struct device
*cdev
,
2151 struct device_attribute
*attr
,
2152 const char *buf
, size_t count
)
2157 ret
= kstrtoul(buf
, 0, &val
);
2164 if (x86_pmu
.attr_rdpmc_broken
)
2167 if ((val
== 2) != (x86_pmu
.attr_rdpmc
== 2)) {
2169 * Changing into or out of always available, aka
2170 * perf-event-bypassing mode. This path is extremely slow,
2171 * but only root can trigger it, so it's okay.
2174 static_key_slow_inc(&rdpmc_always_available
);
2176 static_key_slow_dec(&rdpmc_always_available
);
2177 on_each_cpu(refresh_pce
, NULL
, 1);
2180 x86_pmu
.attr_rdpmc
= val
;
2185 static DEVICE_ATTR(rdpmc
, S_IRUSR
| S_IWUSR
, get_attr_rdpmc
, set_attr_rdpmc
);
2187 static struct attribute
*x86_pmu_attrs
[] = {
2188 &dev_attr_rdpmc
.attr
,
2192 static struct attribute_group x86_pmu_attr_group
= {
2193 .attrs
= x86_pmu_attrs
,
2196 static const struct attribute_group
*x86_pmu_attr_groups
[] = {
2197 &x86_pmu_attr_group
,
2198 &x86_pmu_format_group
,
2199 &x86_pmu_events_group
,
2203 static void x86_pmu_sched_task(struct perf_event_context
*ctx
, bool sched_in
)
2205 if (x86_pmu
.sched_task
)
2206 x86_pmu
.sched_task(ctx
, sched_in
);
2209 void perf_check_microcode(void)
2211 if (x86_pmu
.check_microcode
)
2212 x86_pmu
.check_microcode();
2214 EXPORT_SYMBOL_GPL(perf_check_microcode
);
2216 static struct pmu pmu
= {
2217 .pmu_enable
= x86_pmu_enable
,
2218 .pmu_disable
= x86_pmu_disable
,
2220 .attr_groups
= x86_pmu_attr_groups
,
2222 .event_init
= x86_pmu_event_init
,
2224 .event_mapped
= x86_pmu_event_mapped
,
2225 .event_unmapped
= x86_pmu_event_unmapped
,
2229 .start
= x86_pmu_start
,
2230 .stop
= x86_pmu_stop
,
2231 .read
= x86_pmu_read
,
2233 .start_txn
= x86_pmu_start_txn
,
2234 .cancel_txn
= x86_pmu_cancel_txn
,
2235 .commit_txn
= x86_pmu_commit_txn
,
2237 .event_idx
= x86_pmu_event_idx
,
2238 .sched_task
= x86_pmu_sched_task
,
2239 .task_ctx_size
= sizeof(struct x86_perf_task_context
),
2242 void arch_perf_update_userpage(struct perf_event
*event
,
2243 struct perf_event_mmap_page
*userpg
, u64 now
)
2245 struct cyc2ns_data
*data
;
2247 userpg
->cap_user_time
= 0;
2248 userpg
->cap_user_time_zero
= 0;
2249 userpg
->cap_user_rdpmc
=
2250 !!(event
->hw
.flags
& PERF_X86_EVENT_RDPMC_ALLOWED
);
2251 userpg
->pmc_width
= x86_pmu
.cntval_bits
;
2253 if (!sched_clock_stable())
2256 data
= cyc2ns_read_begin();
2259 * Internal timekeeping for enabled/running/stopped times
2260 * is always in the local_clock domain.
2262 userpg
->cap_user_time
= 1;
2263 userpg
->time_mult
= data
->cyc2ns_mul
;
2264 userpg
->time_shift
= data
->cyc2ns_shift
;
2265 userpg
->time_offset
= data
->cyc2ns_offset
- now
;
2268 * cap_user_time_zero doesn't make sense when we're using a different
2269 * time base for the records.
2271 if (!event
->attr
.use_clockid
) {
2272 userpg
->cap_user_time_zero
= 1;
2273 userpg
->time_zero
= data
->cyc2ns_offset
;
2276 cyc2ns_read_end(data
);
2280 perf_callchain_kernel(struct perf_callchain_entry_ctx
*entry
, struct pt_regs
*regs
)
2282 struct unwind_state state
;
2285 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
2286 /* TODO: We don't support guest os callchain now */
2290 if (perf_callchain_store(entry
, regs
->ip
))
2293 for (unwind_start(&state
, current
, regs
, NULL
); !unwind_done(&state
);
2294 unwind_next_frame(&state
)) {
2295 addr
= unwind_get_return_address(&state
);
2296 if (!addr
|| perf_callchain_store(entry
, addr
))
2302 valid_user_frame(const void __user
*fp
, unsigned long size
)
2304 return (__range_not_ok(fp
, size
, TASK_SIZE
) == 0);
2307 static unsigned long get_segment_base(unsigned int segment
)
2309 struct desc_struct
*desc
;
2310 unsigned int idx
= segment
>> 3;
2312 if ((segment
& SEGMENT_TI_MASK
) == SEGMENT_LDT
) {
2313 #ifdef CONFIG_MODIFY_LDT_SYSCALL
2314 struct ldt_struct
*ldt
;
2316 if (idx
> LDT_ENTRIES
)
2319 /* IRQs are off, so this synchronizes with smp_store_release */
2320 ldt
= lockless_dereference(current
->active_mm
->context
.ldt
);
2321 if (!ldt
|| idx
> ldt
->size
)
2324 desc
= &ldt
->entries
[idx
];
2329 if (idx
> GDT_ENTRIES
)
2332 desc
= raw_cpu_ptr(gdt_page
.gdt
) + idx
;
2335 return get_desc_base(desc
);
2338 #ifdef CONFIG_IA32_EMULATION
2340 #include <asm/compat.h>
2343 perf_callchain_user32(struct pt_regs
*regs
, struct perf_callchain_entry_ctx
*entry
)
2345 /* 32-bit process in 64-bit kernel. */
2346 unsigned long ss_base
, cs_base
;
2347 struct stack_frame_ia32 frame
;
2348 const void __user
*fp
;
2350 if (!test_thread_flag(TIF_IA32
))
2353 cs_base
= get_segment_base(regs
->cs
);
2354 ss_base
= get_segment_base(regs
->ss
);
2356 fp
= compat_ptr(ss_base
+ regs
->bp
);
2357 pagefault_disable();
2358 while (entry
->nr
< entry
->max_stack
) {
2359 unsigned long bytes
;
2360 frame
.next_frame
= 0;
2361 frame
.return_address
= 0;
2363 if (!valid_user_frame(fp
, sizeof(frame
)))
2366 bytes
= __copy_from_user_nmi(&frame
.next_frame
, fp
, 4);
2369 bytes
= __copy_from_user_nmi(&frame
.return_address
, fp
+4, 4);
2373 perf_callchain_store(entry
, cs_base
+ frame
.return_address
);
2374 fp
= compat_ptr(ss_base
+ frame
.next_frame
);
2381 perf_callchain_user32(struct pt_regs
*regs
, struct perf_callchain_entry_ctx
*entry
)
2388 perf_callchain_user(struct perf_callchain_entry_ctx
*entry
, struct pt_regs
*regs
)
2390 struct stack_frame frame
;
2391 const unsigned long __user
*fp
;
2393 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
2394 /* TODO: We don't support guest os callchain now */
2399 * We don't know what to do with VM86 stacks.. ignore them for now.
2401 if (regs
->flags
& (X86_VM_MASK
| PERF_EFLAGS_VM
))
2404 fp
= (unsigned long __user
*)regs
->bp
;
2406 perf_callchain_store(entry
, regs
->ip
);
2411 if (perf_callchain_user32(regs
, entry
))
2414 pagefault_disable();
2415 while (entry
->nr
< entry
->max_stack
) {
2416 unsigned long bytes
;
2418 frame
.next_frame
= NULL
;
2419 frame
.return_address
= 0;
2421 if (!valid_user_frame(fp
, sizeof(frame
)))
2424 bytes
= __copy_from_user_nmi(&frame
.next_frame
, fp
, sizeof(*fp
));
2427 bytes
= __copy_from_user_nmi(&frame
.return_address
, fp
+ 1, sizeof(*fp
));
2431 perf_callchain_store(entry
, frame
.return_address
);
2432 fp
= (void __user
*)frame
.next_frame
;
2438 * Deal with code segment offsets for the various execution modes:
2440 * VM86 - the good olde 16 bit days, where the linear address is
2441 * 20 bits and we use regs->ip + 0x10 * regs->cs.
2443 * IA32 - Where we need to look at GDT/LDT segment descriptor tables
2444 * to figure out what the 32bit base address is.
2446 * X32 - has TIF_X32 set, but is running in x86_64
2448 * X86_64 - CS,DS,SS,ES are all zero based.
2450 static unsigned long code_segment_base(struct pt_regs
*regs
)
2453 * For IA32 we look at the GDT/LDT segment base to convert the
2454 * effective IP to a linear address.
2457 #ifdef CONFIG_X86_32
2459 * If we are in VM86 mode, add the segment offset to convert to a
2462 if (regs
->flags
& X86_VM_MASK
)
2463 return 0x10 * regs
->cs
;
2465 if (user_mode(regs
) && regs
->cs
!= __USER_CS
)
2466 return get_segment_base(regs
->cs
);
2468 if (user_mode(regs
) && !user_64bit_mode(regs
) &&
2469 regs
->cs
!= __USER32_CS
)
2470 return get_segment_base(regs
->cs
);
2475 unsigned long perf_instruction_pointer(struct pt_regs
*regs
)
2477 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest())
2478 return perf_guest_cbs
->get_guest_ip();
2480 return regs
->ip
+ code_segment_base(regs
);
2483 unsigned long perf_misc_flags(struct pt_regs
*regs
)
2487 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
2488 if (perf_guest_cbs
->is_user_mode())
2489 misc
|= PERF_RECORD_MISC_GUEST_USER
;
2491 misc
|= PERF_RECORD_MISC_GUEST_KERNEL
;
2493 if (user_mode(regs
))
2494 misc
|= PERF_RECORD_MISC_USER
;
2496 misc
|= PERF_RECORD_MISC_KERNEL
;
2499 if (regs
->flags
& PERF_EFLAGS_EXACT
)
2500 misc
|= PERF_RECORD_MISC_EXACT_IP
;
2505 void perf_get_x86_pmu_capability(struct x86_pmu_capability
*cap
)
2507 cap
->version
= x86_pmu
.version
;
2508 cap
->num_counters_gp
= x86_pmu
.num_counters
;
2509 cap
->num_counters_fixed
= x86_pmu
.num_counters_fixed
;
2510 cap
->bit_width_gp
= x86_pmu
.cntval_bits
;
2511 cap
->bit_width_fixed
= x86_pmu
.cntval_bits
;
2512 cap
->events_mask
= (unsigned int)x86_pmu
.events_maskl
;
2513 cap
->events_mask_len
= x86_pmu
.events_mask_len
;
2515 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability
);