2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/export.h>
21 #include <linux/init.h>
22 #include <linux/kdebug.h>
23 #include <linux/sched/mm.h>
24 #include <linux/sched/clock.h>
25 #include <linux/uaccess.h>
26 #include <linux/slab.h>
27 #include <linux/cpu.h>
28 #include <linux/bitops.h>
29 #include <linux/device.h>
32 #include <asm/stacktrace.h>
35 #include <asm/alternative.h>
36 #include <asm/mmu_context.h>
37 #include <asm/tlbflush.h>
38 #include <asm/timer.h>
41 #include <asm/unwind.h>
43 #include "perf_event.h"
45 struct x86_pmu x86_pmu __read_mostly
;
47 DEFINE_PER_CPU(struct cpu_hw_events
, cpu_hw_events
) = {
51 struct static_key rdpmc_always_available
= STATIC_KEY_INIT_FALSE
;
53 u64 __read_mostly hw_cache_event_ids
54 [PERF_COUNT_HW_CACHE_MAX
]
55 [PERF_COUNT_HW_CACHE_OP_MAX
]
56 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
57 u64 __read_mostly hw_cache_extra_regs
58 [PERF_COUNT_HW_CACHE_MAX
]
59 [PERF_COUNT_HW_CACHE_OP_MAX
]
60 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
63 * Propagate event elapsed time into the generic event.
64 * Can only be executed on the CPU where the event is active.
65 * Returns the delta events processed.
67 u64
x86_perf_event_update(struct perf_event
*event
)
69 struct hw_perf_event
*hwc
= &event
->hw
;
70 int shift
= 64 - x86_pmu
.cntval_bits
;
71 u64 prev_raw_count
, new_raw_count
;
75 if (idx
== INTEL_PMC_IDX_FIXED_BTS
)
79 * Careful: an NMI might modify the previous event value.
81 * Our tactic to handle this is to first atomically read and
82 * exchange a new raw count - then add that new-prev delta
83 * count to the generic event atomically:
86 prev_raw_count
= local64_read(&hwc
->prev_count
);
87 rdpmcl(hwc
->event_base_rdpmc
, new_raw_count
);
89 if (local64_cmpxchg(&hwc
->prev_count
, prev_raw_count
,
90 new_raw_count
) != prev_raw_count
)
94 * Now we have the new raw value and have updated the prev
95 * timestamp already. We can now calculate the elapsed delta
96 * (event-)time and add that to the generic event.
98 * Careful, not all hw sign-extends above the physical width
101 delta
= (new_raw_count
<< shift
) - (prev_raw_count
<< shift
);
104 local64_add(delta
, &event
->count
);
105 local64_sub(delta
, &hwc
->period_left
);
107 return new_raw_count
;
111 * Find and validate any extra registers to set up.
113 static int x86_pmu_extra_regs(u64 config
, struct perf_event
*event
)
115 struct hw_perf_event_extra
*reg
;
116 struct extra_reg
*er
;
118 reg
= &event
->hw
.extra_reg
;
120 if (!x86_pmu
.extra_regs
)
123 for (er
= x86_pmu
.extra_regs
; er
->msr
; er
++) {
124 if (er
->event
!= (config
& er
->config_mask
))
126 if (event
->attr
.config1
& ~er
->valid_mask
)
128 /* Check if the extra msrs can be safely accessed*/
129 if (!er
->extra_msr_access
)
133 reg
->config
= event
->attr
.config1
;
140 static atomic_t active_events
;
141 static atomic_t pmc_refcount
;
142 static DEFINE_MUTEX(pmc_reserve_mutex
);
144 #ifdef CONFIG_X86_LOCAL_APIC
146 static bool reserve_pmc_hardware(void)
150 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
151 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i
)))
155 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
156 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i
)))
163 for (i
--; i
>= 0; i
--)
164 release_evntsel_nmi(x86_pmu_config_addr(i
));
166 i
= x86_pmu
.num_counters
;
169 for (i
--; i
>= 0; i
--)
170 release_perfctr_nmi(x86_pmu_event_addr(i
));
175 static void release_pmc_hardware(void)
179 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
180 release_perfctr_nmi(x86_pmu_event_addr(i
));
181 release_evntsel_nmi(x86_pmu_config_addr(i
));
187 static bool reserve_pmc_hardware(void) { return true; }
188 static void release_pmc_hardware(void) {}
192 static bool check_hw_exists(void)
194 u64 val
, val_fail
, val_new
= ~0;
195 int i
, reg
, reg_fail
, ret
= 0;
200 * Check to see if the BIOS enabled any of the counters, if so
203 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
204 reg
= x86_pmu_config_addr(i
);
205 ret
= rdmsrl_safe(reg
, &val
);
208 if (val
& ARCH_PERFMON_EVENTSEL_ENABLE
) {
217 if (x86_pmu
.num_counters_fixed
) {
218 reg
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
219 ret
= rdmsrl_safe(reg
, &val
);
222 for (i
= 0; i
< x86_pmu
.num_counters_fixed
; i
++) {
223 if (val
& (0x03 << i
*4)) {
232 * If all the counters are enabled, the below test will always
233 * fail. The tools will also become useless in this scenario.
234 * Just fail and disable the hardware counters.
237 if (reg_safe
== -1) {
243 * Read the current value, change it and read it back to see if it
244 * matches, this is needed to detect certain hardware emulators
245 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
247 reg
= x86_pmu_event_addr(reg_safe
);
248 if (rdmsrl_safe(reg
, &val
))
251 ret
= wrmsrl_safe(reg
, val
);
252 ret
|= rdmsrl_safe(reg
, &val_new
);
253 if (ret
|| val
!= val_new
)
257 * We still allow the PMU driver to operate:
260 pr_cont("Broken BIOS detected, complain to your hardware vendor.\n");
261 pr_err(FW_BUG
"the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n",
268 if (boot_cpu_has(X86_FEATURE_HYPERVISOR
)) {
269 pr_cont("PMU not available due to virtualization, using software events only.\n");
271 pr_cont("Broken PMU hardware detected, using software events only.\n");
272 pr_err("Failed to access perfctr msr (MSR %x is %Lx)\n",
279 static void hw_perf_event_destroy(struct perf_event
*event
)
281 x86_release_hardware();
282 atomic_dec(&active_events
);
285 void hw_perf_lbr_event_destroy(struct perf_event
*event
)
287 hw_perf_event_destroy(event
);
289 /* undo the lbr/bts event accounting */
290 x86_del_exclusive(x86_lbr_exclusive_lbr
);
293 static inline int x86_pmu_initialized(void)
295 return x86_pmu
.handle_irq
!= NULL
;
299 set_ext_hw_attr(struct hw_perf_event
*hwc
, struct perf_event
*event
)
301 struct perf_event_attr
*attr
= &event
->attr
;
302 unsigned int cache_type
, cache_op
, cache_result
;
305 config
= attr
->config
;
307 cache_type
= (config
>> 0) & 0xff;
308 if (cache_type
>= PERF_COUNT_HW_CACHE_MAX
)
311 cache_op
= (config
>> 8) & 0xff;
312 if (cache_op
>= PERF_COUNT_HW_CACHE_OP_MAX
)
315 cache_result
= (config
>> 16) & 0xff;
316 if (cache_result
>= PERF_COUNT_HW_CACHE_RESULT_MAX
)
319 val
= hw_cache_event_ids
[cache_type
][cache_op
][cache_result
];
328 attr
->config1
= hw_cache_extra_regs
[cache_type
][cache_op
][cache_result
];
329 return x86_pmu_extra_regs(val
, event
);
332 int x86_reserve_hardware(void)
336 if (!atomic_inc_not_zero(&pmc_refcount
)) {
337 mutex_lock(&pmc_reserve_mutex
);
338 if (atomic_read(&pmc_refcount
) == 0) {
339 if (!reserve_pmc_hardware())
342 reserve_ds_buffers();
345 atomic_inc(&pmc_refcount
);
346 mutex_unlock(&pmc_reserve_mutex
);
352 void x86_release_hardware(void)
354 if (atomic_dec_and_mutex_lock(&pmc_refcount
, &pmc_reserve_mutex
)) {
355 release_pmc_hardware();
356 release_ds_buffers();
357 mutex_unlock(&pmc_reserve_mutex
);
362 * Check if we can create event of a certain type (that no conflicting events
365 int x86_add_exclusive(unsigned int what
)
370 * When lbr_pt_coexist we allow PT to coexist with either LBR or BTS.
371 * LBR and BTS are still mutually exclusive.
373 if (x86_pmu
.lbr_pt_coexist
&& what
== x86_lbr_exclusive_pt
)
376 if (!atomic_inc_not_zero(&x86_pmu
.lbr_exclusive
[what
])) {
377 mutex_lock(&pmc_reserve_mutex
);
378 for (i
= 0; i
< ARRAY_SIZE(x86_pmu
.lbr_exclusive
); i
++) {
379 if (i
!= what
&& atomic_read(&x86_pmu
.lbr_exclusive
[i
]))
382 atomic_inc(&x86_pmu
.lbr_exclusive
[what
]);
383 mutex_unlock(&pmc_reserve_mutex
);
386 atomic_inc(&active_events
);
390 mutex_unlock(&pmc_reserve_mutex
);
394 void x86_del_exclusive(unsigned int what
)
396 if (x86_pmu
.lbr_pt_coexist
&& what
== x86_lbr_exclusive_pt
)
399 atomic_dec(&x86_pmu
.lbr_exclusive
[what
]);
400 atomic_dec(&active_events
);
403 int x86_setup_perfctr(struct perf_event
*event
)
405 struct perf_event_attr
*attr
= &event
->attr
;
406 struct hw_perf_event
*hwc
= &event
->hw
;
409 if (!is_sampling_event(event
)) {
410 hwc
->sample_period
= x86_pmu
.max_period
;
411 hwc
->last_period
= hwc
->sample_period
;
412 local64_set(&hwc
->period_left
, hwc
->sample_period
);
415 if (attr
->type
== PERF_TYPE_RAW
)
416 return x86_pmu_extra_regs(event
->attr
.config
, event
);
418 if (attr
->type
== PERF_TYPE_HW_CACHE
)
419 return set_ext_hw_attr(hwc
, event
);
421 if (attr
->config
>= x86_pmu
.max_events
)
427 config
= x86_pmu
.event_map(attr
->config
);
438 if (attr
->config
== PERF_COUNT_HW_BRANCH_INSTRUCTIONS
&&
439 !attr
->freq
&& hwc
->sample_period
== 1) {
440 /* BTS is not supported by this architecture. */
441 if (!x86_pmu
.bts_active
)
444 /* BTS is currently only allowed for user-mode. */
445 if (!attr
->exclude_kernel
)
448 /* disallow bts if conflicting events are present */
449 if (x86_add_exclusive(x86_lbr_exclusive_lbr
))
452 event
->destroy
= hw_perf_lbr_event_destroy
;
455 hwc
->config
|= config
;
461 * check that branch_sample_type is compatible with
462 * settings needed for precise_ip > 1 which implies
463 * using the LBR to capture ALL taken branches at the
464 * priv levels of the measurement
466 static inline int precise_br_compat(struct perf_event
*event
)
468 u64 m
= event
->attr
.branch_sample_type
;
471 /* must capture all branches */
472 if (!(m
& PERF_SAMPLE_BRANCH_ANY
))
475 m
&= PERF_SAMPLE_BRANCH_KERNEL
| PERF_SAMPLE_BRANCH_USER
;
477 if (!event
->attr
.exclude_user
)
478 b
|= PERF_SAMPLE_BRANCH_USER
;
480 if (!event
->attr
.exclude_kernel
)
481 b
|= PERF_SAMPLE_BRANCH_KERNEL
;
484 * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
490 int x86_pmu_hw_config(struct perf_event
*event
)
492 if (event
->attr
.precise_ip
) {
495 /* Support for constant skid */
496 if (x86_pmu
.pebs_active
&& !x86_pmu
.pebs_broken
) {
499 /* Support for IP fixup */
500 if (x86_pmu
.lbr_nr
|| x86_pmu
.intel_cap
.pebs_format
>= 2)
503 if (x86_pmu
.pebs_prec_dist
)
507 if (event
->attr
.precise_ip
> precise
)
510 /* There's no sense in having PEBS for non sampling events: */
511 if (!is_sampling_event(event
))
515 * check that PEBS LBR correction does not conflict with
516 * whatever the user is asking with attr->branch_sample_type
518 if (event
->attr
.precise_ip
> 1 && x86_pmu
.intel_cap
.pebs_format
< 2) {
519 u64
*br_type
= &event
->attr
.branch_sample_type
;
521 if (has_branch_stack(event
)) {
522 if (!precise_br_compat(event
))
525 /* branch_sample_type is compatible */
529 * user did not specify branch_sample_type
531 * For PEBS fixups, we capture all
532 * the branches at the priv level of the
535 *br_type
= PERF_SAMPLE_BRANCH_ANY
;
537 if (!event
->attr
.exclude_user
)
538 *br_type
|= PERF_SAMPLE_BRANCH_USER
;
540 if (!event
->attr
.exclude_kernel
)
541 *br_type
|= PERF_SAMPLE_BRANCH_KERNEL
;
545 if (event
->attr
.branch_sample_type
& PERF_SAMPLE_BRANCH_CALL_STACK
)
546 event
->attach_state
|= PERF_ATTACH_TASK_DATA
;
550 * (keep 'enabled' bit clear for now)
552 event
->hw
.config
= ARCH_PERFMON_EVENTSEL_INT
;
555 * Count user and OS events unless requested not to
557 if (!event
->attr
.exclude_user
)
558 event
->hw
.config
|= ARCH_PERFMON_EVENTSEL_USR
;
559 if (!event
->attr
.exclude_kernel
)
560 event
->hw
.config
|= ARCH_PERFMON_EVENTSEL_OS
;
562 if (event
->attr
.type
== PERF_TYPE_RAW
)
563 event
->hw
.config
|= event
->attr
.config
& X86_RAW_EVENT_MASK
;
565 if (event
->attr
.sample_period
&& x86_pmu
.limit_period
) {
566 if (x86_pmu
.limit_period(event
, event
->attr
.sample_period
) >
567 event
->attr
.sample_period
)
571 return x86_setup_perfctr(event
);
575 * Setup the hardware configuration for a given attr_type
577 static int __x86_pmu_event_init(struct perf_event
*event
)
581 if (!x86_pmu_initialized())
584 err
= x86_reserve_hardware();
588 atomic_inc(&active_events
);
589 event
->destroy
= hw_perf_event_destroy
;
592 event
->hw
.last_cpu
= -1;
593 event
->hw
.last_tag
= ~0ULL;
596 event
->hw
.extra_reg
.idx
= EXTRA_REG_NONE
;
597 event
->hw
.branch_reg
.idx
= EXTRA_REG_NONE
;
599 return x86_pmu
.hw_config(event
);
602 void x86_pmu_disable_all(void)
604 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
607 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
610 if (!test_bit(idx
, cpuc
->active_mask
))
612 rdmsrl(x86_pmu_config_addr(idx
), val
);
613 if (!(val
& ARCH_PERFMON_EVENTSEL_ENABLE
))
615 val
&= ~ARCH_PERFMON_EVENTSEL_ENABLE
;
616 wrmsrl(x86_pmu_config_addr(idx
), val
);
621 * There may be PMI landing after enabled=0. The PMI hitting could be before or
624 * If PMI hits before disable_all, the PMU will be disabled in the NMI handler.
625 * It will not be re-enabled in the NMI handler again, because enabled=0. After
626 * handling the NMI, disable_all will be called, which will not change the
627 * state either. If PMI hits after disable_all, the PMU is already disabled
628 * before entering NMI handler. The NMI handler will not change the state
631 * So either situation is harmless.
633 static void x86_pmu_disable(struct pmu
*pmu
)
635 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
637 if (!x86_pmu_initialized())
647 x86_pmu
.disable_all();
650 void x86_pmu_enable_all(int added
)
652 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
655 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
656 struct hw_perf_event
*hwc
= &cpuc
->events
[idx
]->hw
;
658 if (!test_bit(idx
, cpuc
->active_mask
))
661 __x86_pmu_enable_event(hwc
, ARCH_PERFMON_EVENTSEL_ENABLE
);
665 static struct pmu pmu
;
667 static inline int is_x86_event(struct perf_event
*event
)
669 return event
->pmu
== &pmu
;
673 * Event scheduler state:
675 * Assign events iterating over all events and counters, beginning
676 * with events with least weights first. Keep the current iterator
677 * state in struct sched_state.
681 int event
; /* event index */
682 int counter
; /* counter index */
683 int unassigned
; /* number of events to be assigned left */
684 int nr_gp
; /* number of GP counters used */
685 unsigned long used
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
688 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
689 #define SCHED_STATES_MAX 2
696 struct event_constraint
**constraints
;
697 struct sched_state state
;
698 struct sched_state saved
[SCHED_STATES_MAX
];
702 * Initialize interator that runs through all events and counters.
704 static void perf_sched_init(struct perf_sched
*sched
, struct event_constraint
**constraints
,
705 int num
, int wmin
, int wmax
, int gpmax
)
709 memset(sched
, 0, sizeof(*sched
));
710 sched
->max_events
= num
;
711 sched
->max_weight
= wmax
;
712 sched
->max_gp
= gpmax
;
713 sched
->constraints
= constraints
;
715 for (idx
= 0; idx
< num
; idx
++) {
716 if (constraints
[idx
]->weight
== wmin
)
720 sched
->state
.event
= idx
; /* start with min weight */
721 sched
->state
.weight
= wmin
;
722 sched
->state
.unassigned
= num
;
725 static void perf_sched_save_state(struct perf_sched
*sched
)
727 if (WARN_ON_ONCE(sched
->saved_states
>= SCHED_STATES_MAX
))
730 sched
->saved
[sched
->saved_states
] = sched
->state
;
731 sched
->saved_states
++;
734 static bool perf_sched_restore_state(struct perf_sched
*sched
)
736 if (!sched
->saved_states
)
739 sched
->saved_states
--;
740 sched
->state
= sched
->saved
[sched
->saved_states
];
742 /* continue with next counter: */
743 clear_bit(sched
->state
.counter
++, sched
->state
.used
);
749 * Select a counter for the current event to schedule. Return true on
752 static bool __perf_sched_find_counter(struct perf_sched
*sched
)
754 struct event_constraint
*c
;
757 if (!sched
->state
.unassigned
)
760 if (sched
->state
.event
>= sched
->max_events
)
763 c
= sched
->constraints
[sched
->state
.event
];
764 /* Prefer fixed purpose counters */
765 if (c
->idxmsk64
& (~0ULL << INTEL_PMC_IDX_FIXED
)) {
766 idx
= INTEL_PMC_IDX_FIXED
;
767 for_each_set_bit_from(idx
, c
->idxmsk
, X86_PMC_IDX_MAX
) {
768 if (!__test_and_set_bit(idx
, sched
->state
.used
))
773 /* Grab the first unused counter starting with idx */
774 idx
= sched
->state
.counter
;
775 for_each_set_bit_from(idx
, c
->idxmsk
, INTEL_PMC_IDX_FIXED
) {
776 if (!__test_and_set_bit(idx
, sched
->state
.used
)) {
777 if (sched
->state
.nr_gp
++ >= sched
->max_gp
)
787 sched
->state
.counter
= idx
;
790 perf_sched_save_state(sched
);
795 static bool perf_sched_find_counter(struct perf_sched
*sched
)
797 while (!__perf_sched_find_counter(sched
)) {
798 if (!perf_sched_restore_state(sched
))
806 * Go through all unassigned events and find the next one to schedule.
807 * Take events with the least weight first. Return true on success.
809 static bool perf_sched_next_event(struct perf_sched
*sched
)
811 struct event_constraint
*c
;
813 if (!sched
->state
.unassigned
|| !--sched
->state
.unassigned
)
818 sched
->state
.event
++;
819 if (sched
->state
.event
>= sched
->max_events
) {
821 sched
->state
.event
= 0;
822 sched
->state
.weight
++;
823 if (sched
->state
.weight
> sched
->max_weight
)
826 c
= sched
->constraints
[sched
->state
.event
];
827 } while (c
->weight
!= sched
->state
.weight
);
829 sched
->state
.counter
= 0; /* start with first counter */
835 * Assign a counter for each event.
837 int perf_assign_events(struct event_constraint
**constraints
, int n
,
838 int wmin
, int wmax
, int gpmax
, int *assign
)
840 struct perf_sched sched
;
842 perf_sched_init(&sched
, constraints
, n
, wmin
, wmax
, gpmax
);
845 if (!perf_sched_find_counter(&sched
))
848 assign
[sched
.state
.event
] = sched
.state
.counter
;
849 } while (perf_sched_next_event(&sched
));
851 return sched
.state
.unassigned
;
853 EXPORT_SYMBOL_GPL(perf_assign_events
);
855 int x86_schedule_events(struct cpu_hw_events
*cpuc
, int n
, int *assign
)
857 struct event_constraint
*c
;
858 unsigned long used_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
859 struct perf_event
*e
;
860 int i
, wmin
, wmax
, unsched
= 0;
861 struct hw_perf_event
*hwc
;
863 bitmap_zero(used_mask
, X86_PMC_IDX_MAX
);
865 if (x86_pmu
.start_scheduling
)
866 x86_pmu
.start_scheduling(cpuc
);
868 for (i
= 0, wmin
= X86_PMC_IDX_MAX
, wmax
= 0; i
< n
; i
++) {
869 cpuc
->event_constraint
[i
] = NULL
;
870 c
= x86_pmu
.get_event_constraints(cpuc
, i
, cpuc
->event_list
[i
]);
871 cpuc
->event_constraint
[i
] = c
;
873 wmin
= min(wmin
, c
->weight
);
874 wmax
= max(wmax
, c
->weight
);
878 * fastpath, try to reuse previous register
880 for (i
= 0; i
< n
; i
++) {
881 hwc
= &cpuc
->event_list
[i
]->hw
;
882 c
= cpuc
->event_constraint
[i
];
888 /* constraint still honored */
889 if (!test_bit(hwc
->idx
, c
->idxmsk
))
892 /* not already used */
893 if (test_bit(hwc
->idx
, used_mask
))
896 __set_bit(hwc
->idx
, used_mask
);
898 assign
[i
] = hwc
->idx
;
903 int gpmax
= x86_pmu
.num_counters
;
906 * Do not allow scheduling of more than half the available
909 * This helps avoid counter starvation of sibling thread by
910 * ensuring at most half the counters cannot be in exclusive
911 * mode. There is no designated counters for the limits. Any
912 * N/2 counters can be used. This helps with events with
913 * specific counter constraints.
915 if (is_ht_workaround_enabled() && !cpuc
->is_fake
&&
916 READ_ONCE(cpuc
->excl_cntrs
->exclusive_present
))
919 unsched
= perf_assign_events(cpuc
->event_constraint
, n
, wmin
,
920 wmax
, gpmax
, assign
);
924 * In case of success (unsched = 0), mark events as committed,
925 * so we do not put_constraint() in case new events are added
926 * and fail to be scheduled
928 * We invoke the lower level commit callback to lock the resource
930 * We do not need to do all of this in case we are called to
931 * validate an event group (assign == NULL)
933 if (!unsched
&& assign
) {
934 for (i
= 0; i
< n
; i
++) {
935 e
= cpuc
->event_list
[i
];
936 e
->hw
.flags
|= PERF_X86_EVENT_COMMITTED
;
937 if (x86_pmu
.commit_scheduling
)
938 x86_pmu
.commit_scheduling(cpuc
, i
, assign
[i
]);
941 for (i
= 0; i
< n
; i
++) {
942 e
= cpuc
->event_list
[i
];
944 * do not put_constraint() on comitted events,
945 * because they are good to go
947 if ((e
->hw
.flags
& PERF_X86_EVENT_COMMITTED
))
951 * release events that failed scheduling
953 if (x86_pmu
.put_event_constraints
)
954 x86_pmu
.put_event_constraints(cpuc
, e
);
958 if (x86_pmu
.stop_scheduling
)
959 x86_pmu
.stop_scheduling(cpuc
);
961 return unsched
? -EINVAL
: 0;
965 * dogrp: true if must collect siblings events (group)
966 * returns total number of events and error code
968 static int collect_events(struct cpu_hw_events
*cpuc
, struct perf_event
*leader
, bool dogrp
)
970 struct perf_event
*event
;
973 max_count
= x86_pmu
.num_counters
+ x86_pmu
.num_counters_fixed
;
975 /* current number of events already accepted */
978 if (is_x86_event(leader
)) {
981 cpuc
->event_list
[n
] = leader
;
987 list_for_each_entry(event
, &leader
->sibling_list
, group_entry
) {
988 if (!is_x86_event(event
) ||
989 event
->state
<= PERF_EVENT_STATE_OFF
)
995 cpuc
->event_list
[n
] = event
;
1001 static inline void x86_assign_hw_event(struct perf_event
*event
,
1002 struct cpu_hw_events
*cpuc
, int i
)
1004 struct hw_perf_event
*hwc
= &event
->hw
;
1006 hwc
->idx
= cpuc
->assign
[i
];
1007 hwc
->last_cpu
= smp_processor_id();
1008 hwc
->last_tag
= ++cpuc
->tags
[i
];
1010 if (hwc
->idx
== INTEL_PMC_IDX_FIXED_BTS
) {
1011 hwc
->config_base
= 0;
1012 hwc
->event_base
= 0;
1013 } else if (hwc
->idx
>= INTEL_PMC_IDX_FIXED
) {
1014 hwc
->config_base
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
1015 hwc
->event_base
= MSR_ARCH_PERFMON_FIXED_CTR0
+ (hwc
->idx
- INTEL_PMC_IDX_FIXED
);
1016 hwc
->event_base_rdpmc
= (hwc
->idx
- INTEL_PMC_IDX_FIXED
) | 1<<30;
1018 hwc
->config_base
= x86_pmu_config_addr(hwc
->idx
);
1019 hwc
->event_base
= x86_pmu_event_addr(hwc
->idx
);
1020 hwc
->event_base_rdpmc
= x86_pmu_rdpmc_index(hwc
->idx
);
1024 static inline int match_prev_assignment(struct hw_perf_event
*hwc
,
1025 struct cpu_hw_events
*cpuc
,
1028 return hwc
->idx
== cpuc
->assign
[i
] &&
1029 hwc
->last_cpu
== smp_processor_id() &&
1030 hwc
->last_tag
== cpuc
->tags
[i
];
1033 static void x86_pmu_start(struct perf_event
*event
, int flags
);
1035 static void x86_pmu_enable(struct pmu
*pmu
)
1037 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1038 struct perf_event
*event
;
1039 struct hw_perf_event
*hwc
;
1040 int i
, added
= cpuc
->n_added
;
1042 if (!x86_pmu_initialized())
1048 if (cpuc
->n_added
) {
1049 int n_running
= cpuc
->n_events
- cpuc
->n_added
;
1051 * apply assignment obtained either from
1052 * hw_perf_group_sched_in() or x86_pmu_enable()
1054 * step1: save events moving to new counters
1056 for (i
= 0; i
< n_running
; i
++) {
1057 event
= cpuc
->event_list
[i
];
1061 * we can avoid reprogramming counter if:
1062 * - assigned same counter as last time
1063 * - running on same CPU as last time
1064 * - no other event has used the counter since
1066 if (hwc
->idx
== -1 ||
1067 match_prev_assignment(hwc
, cpuc
, i
))
1071 * Ensure we don't accidentally enable a stopped
1072 * counter simply because we rescheduled.
1074 if (hwc
->state
& PERF_HES_STOPPED
)
1075 hwc
->state
|= PERF_HES_ARCH
;
1077 x86_pmu_stop(event
, PERF_EF_UPDATE
);
1081 * step2: reprogram moved events into new counters
1083 for (i
= 0; i
< cpuc
->n_events
; i
++) {
1084 event
= cpuc
->event_list
[i
];
1087 if (!match_prev_assignment(hwc
, cpuc
, i
))
1088 x86_assign_hw_event(event
, cpuc
, i
);
1089 else if (i
< n_running
)
1092 if (hwc
->state
& PERF_HES_ARCH
)
1095 x86_pmu_start(event
, PERF_EF_RELOAD
);
1098 perf_events_lapic_init();
1104 x86_pmu
.enable_all(added
);
1107 static DEFINE_PER_CPU(u64
[X86_PMC_IDX_MAX
], pmc_prev_left
);
1110 * Set the next IRQ period, based on the hwc->period_left value.
1111 * To be called with the event disabled in hw:
1113 int x86_perf_event_set_period(struct perf_event
*event
)
1115 struct hw_perf_event
*hwc
= &event
->hw
;
1116 s64 left
= local64_read(&hwc
->period_left
);
1117 s64 period
= hwc
->sample_period
;
1118 int ret
= 0, idx
= hwc
->idx
;
1120 if (idx
== INTEL_PMC_IDX_FIXED_BTS
)
1124 * If we are way outside a reasonable range then just skip forward:
1126 if (unlikely(left
<= -period
)) {
1128 local64_set(&hwc
->period_left
, left
);
1129 hwc
->last_period
= period
;
1133 if (unlikely(left
<= 0)) {
1135 local64_set(&hwc
->period_left
, left
);
1136 hwc
->last_period
= period
;
1140 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1142 if (unlikely(left
< 2))
1145 if (left
> x86_pmu
.max_period
)
1146 left
= x86_pmu
.max_period
;
1148 if (x86_pmu
.limit_period
)
1149 left
= x86_pmu
.limit_period(event
, left
);
1151 per_cpu(pmc_prev_left
[idx
], smp_processor_id()) = left
;
1153 if (!(hwc
->flags
& PERF_X86_EVENT_AUTO_RELOAD
) ||
1154 local64_read(&hwc
->prev_count
) != (u64
)-left
) {
1156 * The hw event starts counting from this event offset,
1157 * mark it to be able to extra future deltas:
1159 local64_set(&hwc
->prev_count
, (u64
)-left
);
1161 wrmsrl(hwc
->event_base
, (u64
)(-left
) & x86_pmu
.cntval_mask
);
1165 * Due to erratum on certan cpu we need
1166 * a second write to be sure the register
1167 * is updated properly
1169 if (x86_pmu
.perfctr_second_write
) {
1170 wrmsrl(hwc
->event_base
,
1171 (u64
)(-left
) & x86_pmu
.cntval_mask
);
1174 perf_event_update_userpage(event
);
1179 void x86_pmu_enable_event(struct perf_event
*event
)
1181 if (__this_cpu_read(cpu_hw_events
.enabled
))
1182 __x86_pmu_enable_event(&event
->hw
,
1183 ARCH_PERFMON_EVENTSEL_ENABLE
);
1187 * Add a single event to the PMU.
1189 * The event is added to the group of enabled events
1190 * but only if it can be scehduled with existing events.
1192 static int x86_pmu_add(struct perf_event
*event
, int flags
)
1194 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1195 struct hw_perf_event
*hwc
;
1196 int assign
[X86_PMC_IDX_MAX
];
1201 n0
= cpuc
->n_events
;
1202 ret
= n
= collect_events(cpuc
, event
, false);
1206 hwc
->state
= PERF_HES_UPTODATE
| PERF_HES_STOPPED
;
1207 if (!(flags
& PERF_EF_START
))
1208 hwc
->state
|= PERF_HES_ARCH
;
1211 * If group events scheduling transaction was started,
1212 * skip the schedulability test here, it will be performed
1213 * at commit time (->commit_txn) as a whole.
1215 * If commit fails, we'll call ->del() on all events
1216 * for which ->add() was called.
1218 if (cpuc
->txn_flags
& PERF_PMU_TXN_ADD
)
1221 ret
= x86_pmu
.schedule_events(cpuc
, n
, assign
);
1225 * copy new assignment, now we know it is possible
1226 * will be used by hw_perf_enable()
1228 memcpy(cpuc
->assign
, assign
, n
*sizeof(int));
1232 * Commit the collect_events() state. See x86_pmu_del() and
1236 cpuc
->n_added
+= n
- n0
;
1237 cpuc
->n_txn
+= n
- n0
;
1241 * This is before x86_pmu_enable() will call x86_pmu_start(),
1242 * so we enable LBRs before an event needs them etc..
1252 static void x86_pmu_start(struct perf_event
*event
, int flags
)
1254 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1255 int idx
= event
->hw
.idx
;
1257 if (WARN_ON_ONCE(!(event
->hw
.state
& PERF_HES_STOPPED
)))
1260 if (WARN_ON_ONCE(idx
== -1))
1263 if (flags
& PERF_EF_RELOAD
) {
1264 WARN_ON_ONCE(!(event
->hw
.state
& PERF_HES_UPTODATE
));
1265 x86_perf_event_set_period(event
);
1268 event
->hw
.state
= 0;
1270 cpuc
->events
[idx
] = event
;
1271 __set_bit(idx
, cpuc
->active_mask
);
1272 __set_bit(idx
, cpuc
->running
);
1273 x86_pmu
.enable(event
);
1274 perf_event_update_userpage(event
);
1277 void perf_event_print_debug(void)
1279 u64 ctrl
, status
, overflow
, pmc_ctrl
, pmc_count
, prev_left
, fixed
;
1281 struct cpu_hw_events
*cpuc
;
1282 unsigned long flags
;
1285 if (!x86_pmu
.num_counters
)
1288 local_irq_save(flags
);
1290 cpu
= smp_processor_id();
1291 cpuc
= &per_cpu(cpu_hw_events
, cpu
);
1293 if (x86_pmu
.version
>= 2) {
1294 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
1295 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
1296 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, overflow
);
1297 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL
, fixed
);
1300 pr_info("CPU#%d: ctrl: %016llx\n", cpu
, ctrl
);
1301 pr_info("CPU#%d: status: %016llx\n", cpu
, status
);
1302 pr_info("CPU#%d: overflow: %016llx\n", cpu
, overflow
);
1303 pr_info("CPU#%d: fixed: %016llx\n", cpu
, fixed
);
1304 if (x86_pmu
.pebs_constraints
) {
1305 rdmsrl(MSR_IA32_PEBS_ENABLE
, pebs
);
1306 pr_info("CPU#%d: pebs: %016llx\n", cpu
, pebs
);
1308 if (x86_pmu
.lbr_nr
) {
1309 rdmsrl(MSR_IA32_DEBUGCTLMSR
, debugctl
);
1310 pr_info("CPU#%d: debugctl: %016llx\n", cpu
, debugctl
);
1313 pr_info("CPU#%d: active: %016llx\n", cpu
, *(u64
*)cpuc
->active_mask
);
1315 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1316 rdmsrl(x86_pmu_config_addr(idx
), pmc_ctrl
);
1317 rdmsrl(x86_pmu_event_addr(idx
), pmc_count
);
1319 prev_left
= per_cpu(pmc_prev_left
[idx
], cpu
);
1321 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1322 cpu
, idx
, pmc_ctrl
);
1323 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1324 cpu
, idx
, pmc_count
);
1325 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1326 cpu
, idx
, prev_left
);
1328 for (idx
= 0; idx
< x86_pmu
.num_counters_fixed
; idx
++) {
1329 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0
+ idx
, pmc_count
);
1331 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1332 cpu
, idx
, pmc_count
);
1334 local_irq_restore(flags
);
1337 void x86_pmu_stop(struct perf_event
*event
, int flags
)
1339 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1340 struct hw_perf_event
*hwc
= &event
->hw
;
1342 if (__test_and_clear_bit(hwc
->idx
, cpuc
->active_mask
)) {
1343 x86_pmu
.disable(event
);
1344 cpuc
->events
[hwc
->idx
] = NULL
;
1345 WARN_ON_ONCE(hwc
->state
& PERF_HES_STOPPED
);
1346 hwc
->state
|= PERF_HES_STOPPED
;
1349 if ((flags
& PERF_EF_UPDATE
) && !(hwc
->state
& PERF_HES_UPTODATE
)) {
1351 * Drain the remaining delta count out of a event
1352 * that we are disabling:
1354 x86_perf_event_update(event
);
1355 hwc
->state
|= PERF_HES_UPTODATE
;
1359 static void x86_pmu_del(struct perf_event
*event
, int flags
)
1361 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1365 * event is descheduled
1367 event
->hw
.flags
&= ~PERF_X86_EVENT_COMMITTED
;
1370 * If we're called during a txn, we only need to undo x86_pmu.add.
1371 * The events never got scheduled and ->cancel_txn will truncate
1374 * XXX assumes any ->del() called during a TXN will only be on
1375 * an event added during that same TXN.
1377 if (cpuc
->txn_flags
& PERF_PMU_TXN_ADD
)
1381 * Not a TXN, therefore cleanup properly.
1383 x86_pmu_stop(event
, PERF_EF_UPDATE
);
1385 for (i
= 0; i
< cpuc
->n_events
; i
++) {
1386 if (event
== cpuc
->event_list
[i
])
1390 if (WARN_ON_ONCE(i
== cpuc
->n_events
)) /* called ->del() without ->add() ? */
1393 /* If we have a newly added event; make sure to decrease n_added. */
1394 if (i
>= cpuc
->n_events
- cpuc
->n_added
)
1397 if (x86_pmu
.put_event_constraints
)
1398 x86_pmu
.put_event_constraints(cpuc
, event
);
1400 /* Delete the array entry. */
1401 while (++i
< cpuc
->n_events
) {
1402 cpuc
->event_list
[i
-1] = cpuc
->event_list
[i
];
1403 cpuc
->event_constraint
[i
-1] = cpuc
->event_constraint
[i
];
1407 perf_event_update_userpage(event
);
1412 * This is after x86_pmu_stop(); so we disable LBRs after any
1413 * event can need them etc..
1419 int x86_pmu_handle_irq(struct pt_regs
*regs
)
1421 struct perf_sample_data data
;
1422 struct cpu_hw_events
*cpuc
;
1423 struct perf_event
*event
;
1424 int idx
, handled
= 0;
1427 cpuc
= this_cpu_ptr(&cpu_hw_events
);
1430 * Some chipsets need to unmask the LVTPC in a particular spot
1431 * inside the nmi handler. As a result, the unmasking was pushed
1432 * into all the nmi handlers.
1434 * This generic handler doesn't seem to have any issues where the
1435 * unmasking occurs so it was left at the top.
1437 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1439 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1440 if (!test_bit(idx
, cpuc
->active_mask
)) {
1442 * Though we deactivated the counter some cpus
1443 * might still deliver spurious interrupts still
1444 * in flight. Catch them:
1446 if (__test_and_clear_bit(idx
, cpuc
->running
))
1451 event
= cpuc
->events
[idx
];
1453 val
= x86_perf_event_update(event
);
1454 if (val
& (1ULL << (x86_pmu
.cntval_bits
- 1)))
1461 perf_sample_data_init(&data
, 0, event
->hw
.last_period
);
1463 if (!x86_perf_event_set_period(event
))
1466 if (perf_event_overflow(event
, &data
, regs
))
1467 x86_pmu_stop(event
, 0);
1471 inc_irq_stat(apic_perf_irqs
);
1476 void perf_events_lapic_init(void)
1478 if (!x86_pmu
.apic
|| !x86_pmu_initialized())
1482 * Always use NMI for PMU
1484 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1488 perf_event_nmi_handler(unsigned int cmd
, struct pt_regs
*regs
)
1495 * All PMUs/events that share this PMI handler should make sure to
1496 * increment active_events for their events.
1498 if (!atomic_read(&active_events
))
1501 start_clock
= sched_clock();
1502 ret
= x86_pmu
.handle_irq(regs
);
1503 finish_clock
= sched_clock();
1505 perf_sample_event_took(finish_clock
- start_clock
);
1509 NOKPROBE_SYMBOL(perf_event_nmi_handler
);
1511 struct event_constraint emptyconstraint
;
1512 struct event_constraint unconstrained
;
1514 static int x86_pmu_prepare_cpu(unsigned int cpu
)
1516 struct cpu_hw_events
*cpuc
= &per_cpu(cpu_hw_events
, cpu
);
1519 for (i
= 0 ; i
< X86_PERF_KFREE_MAX
; i
++)
1520 cpuc
->kfree_on_online
[i
] = NULL
;
1521 if (x86_pmu
.cpu_prepare
)
1522 return x86_pmu
.cpu_prepare(cpu
);
1526 static int x86_pmu_dead_cpu(unsigned int cpu
)
1528 if (x86_pmu
.cpu_dead
)
1529 x86_pmu
.cpu_dead(cpu
);
1533 static int x86_pmu_online_cpu(unsigned int cpu
)
1535 struct cpu_hw_events
*cpuc
= &per_cpu(cpu_hw_events
, cpu
);
1538 for (i
= 0 ; i
< X86_PERF_KFREE_MAX
; i
++) {
1539 kfree(cpuc
->kfree_on_online
[i
]);
1540 cpuc
->kfree_on_online
[i
] = NULL
;
1545 static int x86_pmu_starting_cpu(unsigned int cpu
)
1547 if (x86_pmu
.cpu_starting
)
1548 x86_pmu
.cpu_starting(cpu
);
1552 static int x86_pmu_dying_cpu(unsigned int cpu
)
1554 if (x86_pmu
.cpu_dying
)
1555 x86_pmu
.cpu_dying(cpu
);
1559 static void __init
pmu_check_apic(void)
1561 if (boot_cpu_has(X86_FEATURE_APIC
))
1565 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1566 pr_info("no hardware sampling interrupt available.\n");
1569 * If we have a PMU initialized but no APIC
1570 * interrupts, we cannot sample hardware
1571 * events (user-space has to fall back and
1572 * sample via a hrtimer based software event):
1574 pmu
.capabilities
|= PERF_PMU_CAP_NO_INTERRUPT
;
1578 static struct attribute_group x86_pmu_format_group
= {
1584 * Remove all undefined events (x86_pmu.event_map(id) == 0)
1585 * out of events_attr attributes.
1587 static void __init
filter_events(struct attribute
**attrs
)
1589 struct device_attribute
*d
;
1590 struct perf_pmu_events_attr
*pmu_attr
;
1594 for (i
= 0; attrs
[i
]; i
++) {
1595 d
= (struct device_attribute
*)attrs
[i
];
1596 pmu_attr
= container_of(d
, struct perf_pmu_events_attr
, attr
);
1598 if (pmu_attr
->event_str
)
1600 if (x86_pmu
.event_map(i
+ offset
))
1603 for (j
= i
; attrs
[j
]; j
++)
1604 attrs
[j
] = attrs
[j
+ 1];
1606 /* Check the shifted attr. */
1610 * event_map() is index based, the attrs array is organized
1611 * by increasing event index. If we shift the events, then
1612 * we need to compensate for the event_map(), otherwise
1613 * we are looking up the wrong event in the map
1619 /* Merge two pointer arrays */
1620 __init
struct attribute
**merge_attr(struct attribute
**a
, struct attribute
**b
)
1622 struct attribute
**new;
1625 for (j
= 0; a
[j
]; j
++)
1627 for (i
= 0; b
[i
]; i
++)
1631 new = kmalloc(sizeof(struct attribute
*) * j
, GFP_KERNEL
);
1636 for (i
= 0; a
[i
]; i
++)
1638 for (i
= 0; b
[i
]; i
++)
1645 ssize_t
events_sysfs_show(struct device
*dev
, struct device_attribute
*attr
, char *page
)
1647 struct perf_pmu_events_attr
*pmu_attr
= \
1648 container_of(attr
, struct perf_pmu_events_attr
, attr
);
1649 u64 config
= x86_pmu
.event_map(pmu_attr
->id
);
1651 /* string trumps id */
1652 if (pmu_attr
->event_str
)
1653 return sprintf(page
, "%s", pmu_attr
->event_str
);
1655 return x86_pmu
.events_sysfs_show(page
, config
);
1657 EXPORT_SYMBOL_GPL(events_sysfs_show
);
1659 ssize_t
events_ht_sysfs_show(struct device
*dev
, struct device_attribute
*attr
,
1662 struct perf_pmu_events_ht_attr
*pmu_attr
=
1663 container_of(attr
, struct perf_pmu_events_ht_attr
, attr
);
1666 * Report conditional events depending on Hyper-Threading.
1668 * This is overly conservative as usually the HT special
1669 * handling is not needed if the other CPU thread is idle.
1671 * Note this does not (and cannot) handle the case when thread
1672 * siblings are invisible, for example with virtualization
1673 * if they are owned by some other guest. The user tool
1674 * has to re-read when a thread sibling gets onlined later.
1676 return sprintf(page
, "%s",
1677 topology_max_smt_threads() > 1 ?
1678 pmu_attr
->event_str_ht
:
1679 pmu_attr
->event_str_noht
);
1682 EVENT_ATTR(cpu
-cycles
, CPU_CYCLES
);
1683 EVENT_ATTR(instructions
, INSTRUCTIONS
);
1684 EVENT_ATTR(cache
-references
, CACHE_REFERENCES
);
1685 EVENT_ATTR(cache
-misses
, CACHE_MISSES
);
1686 EVENT_ATTR(branch
-instructions
, BRANCH_INSTRUCTIONS
);
1687 EVENT_ATTR(branch
-misses
, BRANCH_MISSES
);
1688 EVENT_ATTR(bus
-cycles
, BUS_CYCLES
);
1689 EVENT_ATTR(stalled
-cycles
-frontend
, STALLED_CYCLES_FRONTEND
);
1690 EVENT_ATTR(stalled
-cycles
-backend
, STALLED_CYCLES_BACKEND
);
1691 EVENT_ATTR(ref
-cycles
, REF_CPU_CYCLES
);
1693 static struct attribute
*empty_attrs
;
1695 static struct attribute
*events_attr
[] = {
1696 EVENT_PTR(CPU_CYCLES
),
1697 EVENT_PTR(INSTRUCTIONS
),
1698 EVENT_PTR(CACHE_REFERENCES
),
1699 EVENT_PTR(CACHE_MISSES
),
1700 EVENT_PTR(BRANCH_INSTRUCTIONS
),
1701 EVENT_PTR(BRANCH_MISSES
),
1702 EVENT_PTR(BUS_CYCLES
),
1703 EVENT_PTR(STALLED_CYCLES_FRONTEND
),
1704 EVENT_PTR(STALLED_CYCLES_BACKEND
),
1705 EVENT_PTR(REF_CPU_CYCLES
),
1709 static struct attribute_group x86_pmu_events_group
= {
1711 .attrs
= events_attr
,
1714 ssize_t
x86_event_sysfs_show(char *page
, u64 config
, u64 event
)
1716 u64 umask
= (config
& ARCH_PERFMON_EVENTSEL_UMASK
) >> 8;
1717 u64 cmask
= (config
& ARCH_PERFMON_EVENTSEL_CMASK
) >> 24;
1718 bool edge
= (config
& ARCH_PERFMON_EVENTSEL_EDGE
);
1719 bool pc
= (config
& ARCH_PERFMON_EVENTSEL_PIN_CONTROL
);
1720 bool any
= (config
& ARCH_PERFMON_EVENTSEL_ANY
);
1721 bool inv
= (config
& ARCH_PERFMON_EVENTSEL_INV
);
1725 * We have whole page size to spend and just little data
1726 * to write, so we can safely use sprintf.
1728 ret
= sprintf(page
, "event=0x%02llx", event
);
1731 ret
+= sprintf(page
+ ret
, ",umask=0x%02llx", umask
);
1734 ret
+= sprintf(page
+ ret
, ",edge");
1737 ret
+= sprintf(page
+ ret
, ",pc");
1740 ret
+= sprintf(page
+ ret
, ",any");
1743 ret
+= sprintf(page
+ ret
, ",inv");
1746 ret
+= sprintf(page
+ ret
, ",cmask=0x%02llx", cmask
);
1748 ret
+= sprintf(page
+ ret
, "\n");
1753 static int __init
init_hw_perf_events(void)
1755 struct x86_pmu_quirk
*quirk
;
1758 pr_info("Performance Events: ");
1760 switch (boot_cpu_data
.x86_vendor
) {
1761 case X86_VENDOR_INTEL
:
1762 err
= intel_pmu_init();
1764 case X86_VENDOR_AMD
:
1765 err
= amd_pmu_init();
1771 pr_cont("no PMU driver, software events only.\n");
1777 /* sanity check that the hardware exists or is emulated */
1778 if (!check_hw_exists())
1781 pr_cont("%s PMU driver.\n", x86_pmu
.name
);
1783 x86_pmu
.attr_rdpmc
= 1; /* enable userspace RDPMC usage by default */
1785 for (quirk
= x86_pmu
.quirks
; quirk
; quirk
= quirk
->next
)
1788 if (!x86_pmu
.intel_ctrl
)
1789 x86_pmu
.intel_ctrl
= (1 << x86_pmu
.num_counters
) - 1;
1791 perf_events_lapic_init();
1792 register_nmi_handler(NMI_LOCAL
, perf_event_nmi_handler
, 0, "PMI");
1794 unconstrained
= (struct event_constraint
)
1795 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu
.num_counters
) - 1,
1796 0, x86_pmu
.num_counters
, 0, 0);
1798 x86_pmu_format_group
.attrs
= x86_pmu
.format_attrs
;
1800 if (x86_pmu
.event_attrs
)
1801 x86_pmu_events_group
.attrs
= x86_pmu
.event_attrs
;
1803 if (!x86_pmu
.events_sysfs_show
)
1804 x86_pmu_events_group
.attrs
= &empty_attrs
;
1806 filter_events(x86_pmu_events_group
.attrs
);
1808 if (x86_pmu
.cpu_events
) {
1809 struct attribute
**tmp
;
1811 tmp
= merge_attr(x86_pmu_events_group
.attrs
, x86_pmu
.cpu_events
);
1813 x86_pmu_events_group
.attrs
= tmp
;
1816 pr_info("... version: %d\n", x86_pmu
.version
);
1817 pr_info("... bit width: %d\n", x86_pmu
.cntval_bits
);
1818 pr_info("... generic registers: %d\n", x86_pmu
.num_counters
);
1819 pr_info("... value mask: %016Lx\n", x86_pmu
.cntval_mask
);
1820 pr_info("... max period: %016Lx\n", x86_pmu
.max_period
);
1821 pr_info("... fixed-purpose events: %d\n", x86_pmu
.num_counters_fixed
);
1822 pr_info("... event mask: %016Lx\n", x86_pmu
.intel_ctrl
);
1825 * Install callbacks. Core will call them for each online
1828 err
= cpuhp_setup_state(CPUHP_PERF_X86_PREPARE
, "perf/x86:prepare",
1829 x86_pmu_prepare_cpu
, x86_pmu_dead_cpu
);
1833 err
= cpuhp_setup_state(CPUHP_AP_PERF_X86_STARTING
,
1834 "perf/x86:starting", x86_pmu_starting_cpu
,
1839 err
= cpuhp_setup_state(CPUHP_AP_PERF_X86_ONLINE
, "perf/x86:online",
1840 x86_pmu_online_cpu
, NULL
);
1844 err
= perf_pmu_register(&pmu
, "cpu", PERF_TYPE_RAW
);
1851 cpuhp_remove_state(CPUHP_AP_PERF_X86_ONLINE
);
1853 cpuhp_remove_state(CPUHP_AP_PERF_X86_STARTING
);
1855 cpuhp_remove_state(CPUHP_PERF_X86_PREPARE
);
1858 early_initcall(init_hw_perf_events
);
1860 static inline void x86_pmu_read(struct perf_event
*event
)
1862 x86_perf_event_update(event
);
1866 * Start group events scheduling transaction
1867 * Set the flag to make pmu::enable() not perform the
1868 * schedulability test, it will be performed at commit time
1870 * We only support PERF_PMU_TXN_ADD transactions. Save the
1871 * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
1874 static void x86_pmu_start_txn(struct pmu
*pmu
, unsigned int txn_flags
)
1876 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1878 WARN_ON_ONCE(cpuc
->txn_flags
); /* txn already in flight */
1880 cpuc
->txn_flags
= txn_flags
;
1881 if (txn_flags
& ~PERF_PMU_TXN_ADD
)
1884 perf_pmu_disable(pmu
);
1885 __this_cpu_write(cpu_hw_events
.n_txn
, 0);
1889 * Stop group events scheduling transaction
1890 * Clear the flag and pmu::enable() will perform the
1891 * schedulability test.
1893 static void x86_pmu_cancel_txn(struct pmu
*pmu
)
1895 unsigned int txn_flags
;
1896 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1898 WARN_ON_ONCE(!cpuc
->txn_flags
); /* no txn in flight */
1900 txn_flags
= cpuc
->txn_flags
;
1901 cpuc
->txn_flags
= 0;
1902 if (txn_flags
& ~PERF_PMU_TXN_ADD
)
1906 * Truncate collected array by the number of events added in this
1907 * transaction. See x86_pmu_add() and x86_pmu_*_txn().
1909 __this_cpu_sub(cpu_hw_events
.n_added
, __this_cpu_read(cpu_hw_events
.n_txn
));
1910 __this_cpu_sub(cpu_hw_events
.n_events
, __this_cpu_read(cpu_hw_events
.n_txn
));
1911 perf_pmu_enable(pmu
);
1915 * Commit group events scheduling transaction
1916 * Perform the group schedulability test as a whole
1917 * Return 0 if success
1919 * Does not cancel the transaction on failure; expects the caller to do this.
1921 static int x86_pmu_commit_txn(struct pmu
*pmu
)
1923 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1924 int assign
[X86_PMC_IDX_MAX
];
1927 WARN_ON_ONCE(!cpuc
->txn_flags
); /* no txn in flight */
1929 if (cpuc
->txn_flags
& ~PERF_PMU_TXN_ADD
) {
1930 cpuc
->txn_flags
= 0;
1936 if (!x86_pmu_initialized())
1939 ret
= x86_pmu
.schedule_events(cpuc
, n
, assign
);
1944 * copy new assignment, now we know it is possible
1945 * will be used by hw_perf_enable()
1947 memcpy(cpuc
->assign
, assign
, n
*sizeof(int));
1949 cpuc
->txn_flags
= 0;
1950 perf_pmu_enable(pmu
);
1954 * a fake_cpuc is used to validate event groups. Due to
1955 * the extra reg logic, we need to also allocate a fake
1956 * per_core and per_cpu structure. Otherwise, group events
1957 * using extra reg may conflict without the kernel being
1958 * able to catch this when the last event gets added to
1961 static void free_fake_cpuc(struct cpu_hw_events
*cpuc
)
1963 kfree(cpuc
->shared_regs
);
1967 static struct cpu_hw_events
*allocate_fake_cpuc(void)
1969 struct cpu_hw_events
*cpuc
;
1970 int cpu
= raw_smp_processor_id();
1972 cpuc
= kzalloc(sizeof(*cpuc
), GFP_KERNEL
);
1974 return ERR_PTR(-ENOMEM
);
1976 /* only needed, if we have extra_regs */
1977 if (x86_pmu
.extra_regs
) {
1978 cpuc
->shared_regs
= allocate_shared_regs(cpu
);
1979 if (!cpuc
->shared_regs
)
1985 free_fake_cpuc(cpuc
);
1986 return ERR_PTR(-ENOMEM
);
1990 * validate that we can schedule this event
1992 static int validate_event(struct perf_event
*event
)
1994 struct cpu_hw_events
*fake_cpuc
;
1995 struct event_constraint
*c
;
1998 fake_cpuc
= allocate_fake_cpuc();
1999 if (IS_ERR(fake_cpuc
))
2000 return PTR_ERR(fake_cpuc
);
2002 c
= x86_pmu
.get_event_constraints(fake_cpuc
, -1, event
);
2004 if (!c
|| !c
->weight
)
2007 if (x86_pmu
.put_event_constraints
)
2008 x86_pmu
.put_event_constraints(fake_cpuc
, event
);
2010 free_fake_cpuc(fake_cpuc
);
2016 * validate a single event group
2018 * validation include:
2019 * - check events are compatible which each other
2020 * - events do not compete for the same counter
2021 * - number of events <= number of counters
2023 * validation ensures the group can be loaded onto the
2024 * PMU if it was the only group available.
2026 static int validate_group(struct perf_event
*event
)
2028 struct perf_event
*leader
= event
->group_leader
;
2029 struct cpu_hw_events
*fake_cpuc
;
2030 int ret
= -EINVAL
, n
;
2032 fake_cpuc
= allocate_fake_cpuc();
2033 if (IS_ERR(fake_cpuc
))
2034 return PTR_ERR(fake_cpuc
);
2036 * the event is not yet connected with its
2037 * siblings therefore we must first collect
2038 * existing siblings, then add the new event
2039 * before we can simulate the scheduling
2041 n
= collect_events(fake_cpuc
, leader
, true);
2045 fake_cpuc
->n_events
= n
;
2046 n
= collect_events(fake_cpuc
, event
, false);
2050 fake_cpuc
->n_events
= n
;
2052 ret
= x86_pmu
.schedule_events(fake_cpuc
, n
, NULL
);
2055 free_fake_cpuc(fake_cpuc
);
2059 static int x86_pmu_event_init(struct perf_event
*event
)
2064 switch (event
->attr
.type
) {
2066 case PERF_TYPE_HARDWARE
:
2067 case PERF_TYPE_HW_CACHE
:
2074 err
= __x86_pmu_event_init(event
);
2077 * we temporarily connect event to its pmu
2078 * such that validate_group() can classify
2079 * it as an x86 event using is_x86_event()
2084 if (event
->group_leader
!= event
)
2085 err
= validate_group(event
);
2087 err
= validate_event(event
);
2093 event
->destroy(event
);
2096 if (ACCESS_ONCE(x86_pmu
.attr_rdpmc
))
2097 event
->hw
.flags
|= PERF_X86_EVENT_RDPMC_ALLOWED
;
2102 static void refresh_pce(void *ignored
)
2104 if (current
->active_mm
)
2105 load_mm_cr4(current
->active_mm
);
2108 static void x86_pmu_event_mapped(struct perf_event
*event
)
2110 if (!(event
->hw
.flags
& PERF_X86_EVENT_RDPMC_ALLOWED
))
2114 * This function relies on not being called concurrently in two
2115 * tasks in the same mm. Otherwise one task could observe
2116 * perf_rdpmc_allowed > 1 and return all the way back to
2117 * userspace with CR4.PCE clear while another task is still
2118 * doing on_each_cpu_mask() to propagate CR4.PCE.
2120 * For now, this can't happen because all callers hold mmap_sem
2121 * for write. If this changes, we'll need a different solution.
2123 lockdep_assert_held_exclusive(¤t
->mm
->mmap_sem
);
2125 if (atomic_inc_return(¤t
->mm
->context
.perf_rdpmc_allowed
) == 1)
2126 on_each_cpu_mask(mm_cpumask(current
->mm
), refresh_pce
, NULL
, 1);
2129 static void x86_pmu_event_unmapped(struct perf_event
*event
)
2134 if (!(event
->hw
.flags
& PERF_X86_EVENT_RDPMC_ALLOWED
))
2137 if (atomic_dec_and_test(¤t
->mm
->context
.perf_rdpmc_allowed
))
2138 on_each_cpu_mask(mm_cpumask(current
->mm
), refresh_pce
, NULL
, 1);
2141 static int x86_pmu_event_idx(struct perf_event
*event
)
2143 int idx
= event
->hw
.idx
;
2145 if (!(event
->hw
.flags
& PERF_X86_EVENT_RDPMC_ALLOWED
))
2148 if (x86_pmu
.num_counters_fixed
&& idx
>= INTEL_PMC_IDX_FIXED
) {
2149 idx
-= INTEL_PMC_IDX_FIXED
;
2156 static ssize_t
get_attr_rdpmc(struct device
*cdev
,
2157 struct device_attribute
*attr
,
2160 return snprintf(buf
, 40, "%d\n", x86_pmu
.attr_rdpmc
);
2163 static ssize_t
set_attr_rdpmc(struct device
*cdev
,
2164 struct device_attribute
*attr
,
2165 const char *buf
, size_t count
)
2170 ret
= kstrtoul(buf
, 0, &val
);
2177 if (x86_pmu
.attr_rdpmc_broken
)
2180 if ((val
== 2) != (x86_pmu
.attr_rdpmc
== 2)) {
2182 * Changing into or out of always available, aka
2183 * perf-event-bypassing mode. This path is extremely slow,
2184 * but only root can trigger it, so it's okay.
2187 static_key_slow_inc(&rdpmc_always_available
);
2189 static_key_slow_dec(&rdpmc_always_available
);
2190 on_each_cpu(refresh_pce
, NULL
, 1);
2193 x86_pmu
.attr_rdpmc
= val
;
2198 static DEVICE_ATTR(rdpmc
, S_IRUSR
| S_IWUSR
, get_attr_rdpmc
, set_attr_rdpmc
);
2200 static struct attribute
*x86_pmu_attrs
[] = {
2201 &dev_attr_rdpmc
.attr
,
2205 static struct attribute_group x86_pmu_attr_group
= {
2206 .attrs
= x86_pmu_attrs
,
2209 static const struct attribute_group
*x86_pmu_attr_groups
[] = {
2210 &x86_pmu_attr_group
,
2211 &x86_pmu_format_group
,
2212 &x86_pmu_events_group
,
2216 static void x86_pmu_sched_task(struct perf_event_context
*ctx
, bool sched_in
)
2218 if (x86_pmu
.sched_task
)
2219 x86_pmu
.sched_task(ctx
, sched_in
);
2222 void perf_check_microcode(void)
2224 if (x86_pmu
.check_microcode
)
2225 x86_pmu
.check_microcode();
2227 EXPORT_SYMBOL_GPL(perf_check_microcode
);
2229 static struct pmu pmu
= {
2230 .pmu_enable
= x86_pmu_enable
,
2231 .pmu_disable
= x86_pmu_disable
,
2233 .attr_groups
= x86_pmu_attr_groups
,
2235 .event_init
= x86_pmu_event_init
,
2237 .event_mapped
= x86_pmu_event_mapped
,
2238 .event_unmapped
= x86_pmu_event_unmapped
,
2242 .start
= x86_pmu_start
,
2243 .stop
= x86_pmu_stop
,
2244 .read
= x86_pmu_read
,
2246 .start_txn
= x86_pmu_start_txn
,
2247 .cancel_txn
= x86_pmu_cancel_txn
,
2248 .commit_txn
= x86_pmu_commit_txn
,
2250 .event_idx
= x86_pmu_event_idx
,
2251 .sched_task
= x86_pmu_sched_task
,
2252 .task_ctx_size
= sizeof(struct x86_perf_task_context
),
2255 void arch_perf_update_userpage(struct perf_event
*event
,
2256 struct perf_event_mmap_page
*userpg
, u64 now
)
2258 struct cyc2ns_data
*data
;
2260 userpg
->cap_user_time
= 0;
2261 userpg
->cap_user_time_zero
= 0;
2262 userpg
->cap_user_rdpmc
=
2263 !!(event
->hw
.flags
& PERF_X86_EVENT_RDPMC_ALLOWED
);
2264 userpg
->pmc_width
= x86_pmu
.cntval_bits
;
2266 if (!sched_clock_stable())
2269 data
= cyc2ns_read_begin();
2272 * Internal timekeeping for enabled/running/stopped times
2273 * is always in the local_clock domain.
2275 userpg
->cap_user_time
= 1;
2276 userpg
->time_mult
= data
->cyc2ns_mul
;
2277 userpg
->time_shift
= data
->cyc2ns_shift
;
2278 userpg
->time_offset
= data
->cyc2ns_offset
- now
;
2281 * cap_user_time_zero doesn't make sense when we're using a different
2282 * time base for the records.
2284 if (!event
->attr
.use_clockid
) {
2285 userpg
->cap_user_time_zero
= 1;
2286 userpg
->time_zero
= data
->cyc2ns_offset
;
2289 cyc2ns_read_end(data
);
2293 perf_callchain_kernel(struct perf_callchain_entry_ctx
*entry
, struct pt_regs
*regs
)
2295 struct unwind_state state
;
2298 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
2299 /* TODO: We don't support guest os callchain now */
2303 if (perf_callchain_store(entry
, regs
->ip
))
2306 for (unwind_start(&state
, current
, regs
, NULL
); !unwind_done(&state
);
2307 unwind_next_frame(&state
)) {
2308 addr
= unwind_get_return_address(&state
);
2309 if (!addr
|| perf_callchain_store(entry
, addr
))
2315 valid_user_frame(const void __user
*fp
, unsigned long size
)
2317 return (__range_not_ok(fp
, size
, TASK_SIZE
) == 0);
2320 static unsigned long get_segment_base(unsigned int segment
)
2322 struct desc_struct
*desc
;
2323 unsigned int idx
= segment
>> 3;
2325 if ((segment
& SEGMENT_TI_MASK
) == SEGMENT_LDT
) {
2326 #ifdef CONFIG_MODIFY_LDT_SYSCALL
2327 struct ldt_struct
*ldt
;
2329 if (idx
> LDT_ENTRIES
)
2332 /* IRQs are off, so this synchronizes with smp_store_release */
2333 ldt
= lockless_dereference(current
->active_mm
->context
.ldt
);
2334 if (!ldt
|| idx
> ldt
->size
)
2337 desc
= &ldt
->entries
[idx
];
2342 if (idx
> GDT_ENTRIES
)
2345 desc
= raw_cpu_ptr(gdt_page
.gdt
) + idx
;
2348 return get_desc_base(desc
);
2351 #ifdef CONFIG_IA32_EMULATION
2353 #include <asm/compat.h>
2356 perf_callchain_user32(struct pt_regs
*regs
, struct perf_callchain_entry_ctx
*entry
)
2358 /* 32-bit process in 64-bit kernel. */
2359 unsigned long ss_base
, cs_base
;
2360 struct stack_frame_ia32 frame
;
2361 const void __user
*fp
;
2363 if (!test_thread_flag(TIF_IA32
))
2366 cs_base
= get_segment_base(regs
->cs
);
2367 ss_base
= get_segment_base(regs
->ss
);
2369 fp
= compat_ptr(ss_base
+ regs
->bp
);
2370 pagefault_disable();
2371 while (entry
->nr
< entry
->max_stack
) {
2372 unsigned long bytes
;
2373 frame
.next_frame
= 0;
2374 frame
.return_address
= 0;
2376 if (!valid_user_frame(fp
, sizeof(frame
)))
2379 bytes
= __copy_from_user_nmi(&frame
.next_frame
, fp
, 4);
2382 bytes
= __copy_from_user_nmi(&frame
.return_address
, fp
+4, 4);
2386 perf_callchain_store(entry
, cs_base
+ frame
.return_address
);
2387 fp
= compat_ptr(ss_base
+ frame
.next_frame
);
2394 perf_callchain_user32(struct pt_regs
*regs
, struct perf_callchain_entry_ctx
*entry
)
2401 perf_callchain_user(struct perf_callchain_entry_ctx
*entry
, struct pt_regs
*regs
)
2403 struct stack_frame frame
;
2404 const unsigned long __user
*fp
;
2406 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
2407 /* TODO: We don't support guest os callchain now */
2412 * We don't know what to do with VM86 stacks.. ignore them for now.
2414 if (regs
->flags
& (X86_VM_MASK
| PERF_EFLAGS_VM
))
2417 fp
= (unsigned long __user
*)regs
->bp
;
2419 perf_callchain_store(entry
, regs
->ip
);
2424 if (perf_callchain_user32(regs
, entry
))
2427 pagefault_disable();
2428 while (entry
->nr
< entry
->max_stack
) {
2429 unsigned long bytes
;
2431 frame
.next_frame
= NULL
;
2432 frame
.return_address
= 0;
2434 if (!valid_user_frame(fp
, sizeof(frame
)))
2437 bytes
= __copy_from_user_nmi(&frame
.next_frame
, fp
, sizeof(*fp
));
2440 bytes
= __copy_from_user_nmi(&frame
.return_address
, fp
+ 1, sizeof(*fp
));
2444 perf_callchain_store(entry
, frame
.return_address
);
2445 fp
= (void __user
*)frame
.next_frame
;
2451 * Deal with code segment offsets for the various execution modes:
2453 * VM86 - the good olde 16 bit days, where the linear address is
2454 * 20 bits and we use regs->ip + 0x10 * regs->cs.
2456 * IA32 - Where we need to look at GDT/LDT segment descriptor tables
2457 * to figure out what the 32bit base address is.
2459 * X32 - has TIF_X32 set, but is running in x86_64
2461 * X86_64 - CS,DS,SS,ES are all zero based.
2463 static unsigned long code_segment_base(struct pt_regs
*regs
)
2466 * For IA32 we look at the GDT/LDT segment base to convert the
2467 * effective IP to a linear address.
2470 #ifdef CONFIG_X86_32
2472 * If we are in VM86 mode, add the segment offset to convert to a
2475 if (regs
->flags
& X86_VM_MASK
)
2476 return 0x10 * regs
->cs
;
2478 if (user_mode(regs
) && regs
->cs
!= __USER_CS
)
2479 return get_segment_base(regs
->cs
);
2481 if (user_mode(regs
) && !user_64bit_mode(regs
) &&
2482 regs
->cs
!= __USER32_CS
)
2483 return get_segment_base(regs
->cs
);
2488 unsigned long perf_instruction_pointer(struct pt_regs
*regs
)
2490 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest())
2491 return perf_guest_cbs
->get_guest_ip();
2493 return regs
->ip
+ code_segment_base(regs
);
2496 unsigned long perf_misc_flags(struct pt_regs
*regs
)
2500 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
2501 if (perf_guest_cbs
->is_user_mode())
2502 misc
|= PERF_RECORD_MISC_GUEST_USER
;
2504 misc
|= PERF_RECORD_MISC_GUEST_KERNEL
;
2506 if (user_mode(regs
))
2507 misc
|= PERF_RECORD_MISC_USER
;
2509 misc
|= PERF_RECORD_MISC_KERNEL
;
2512 if (regs
->flags
& PERF_EFLAGS_EXACT
)
2513 misc
|= PERF_RECORD_MISC_EXACT_IP
;
2518 void perf_get_x86_pmu_capability(struct x86_pmu_capability
*cap
)
2520 cap
->version
= x86_pmu
.version
;
2521 cap
->num_counters_gp
= x86_pmu
.num_counters
;
2522 cap
->num_counters_fixed
= x86_pmu
.num_counters_fixed
;
2523 cap
->bit_width_gp
= x86_pmu
.cntval_bits
;
2524 cap
->bit_width_fixed
= x86_pmu
.cntval_bits
;
2525 cap
->events_mask
= (unsigned int)x86_pmu
.events_maskl
;
2526 cap
->events_mask_len
= x86_pmu
.events_mask_len
;
2528 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability
);