2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/export.h>
21 #include <linux/init.h>
22 #include <linux/kdebug.h>
23 #include <linux/sched/mm.h>
24 #include <linux/sched/clock.h>
25 #include <linux/uaccess.h>
26 #include <linux/slab.h>
27 #include <linux/cpu.h>
28 #include <linux/bitops.h>
29 #include <linux/device.h>
30 #include <linux/nospec.h>
33 #include <asm/stacktrace.h>
36 #include <asm/alternative.h>
37 #include <asm/mmu_context.h>
38 #include <asm/tlbflush.h>
39 #include <asm/timer.h>
42 #include <asm/unwind.h>
44 #include "perf_event.h"
46 struct x86_pmu x86_pmu __read_mostly
;
48 DEFINE_PER_CPU(struct cpu_hw_events
, cpu_hw_events
) = {
52 DEFINE_STATIC_KEY_FALSE(rdpmc_always_available_key
);
54 u64 __read_mostly hw_cache_event_ids
55 [PERF_COUNT_HW_CACHE_MAX
]
56 [PERF_COUNT_HW_CACHE_OP_MAX
]
57 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
58 u64 __read_mostly hw_cache_extra_regs
59 [PERF_COUNT_HW_CACHE_MAX
]
60 [PERF_COUNT_HW_CACHE_OP_MAX
]
61 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
64 * Propagate event elapsed time into the generic event.
65 * Can only be executed on the CPU where the event is active.
66 * Returns the delta events processed.
68 u64
x86_perf_event_update(struct perf_event
*event
)
70 struct hw_perf_event
*hwc
= &event
->hw
;
71 int shift
= 64 - x86_pmu
.cntval_bits
;
72 u64 prev_raw_count
, new_raw_count
;
76 if (idx
== INTEL_PMC_IDX_FIXED_BTS
)
80 * Careful: an NMI might modify the previous event value.
82 * Our tactic to handle this is to first atomically read and
83 * exchange a new raw count - then add that new-prev delta
84 * count to the generic event atomically:
87 prev_raw_count
= local64_read(&hwc
->prev_count
);
88 rdpmcl(hwc
->event_base_rdpmc
, new_raw_count
);
90 if (local64_cmpxchg(&hwc
->prev_count
, prev_raw_count
,
91 new_raw_count
) != prev_raw_count
)
95 * Now we have the new raw value and have updated the prev
96 * timestamp already. We can now calculate the elapsed delta
97 * (event-)time and add that to the generic event.
99 * Careful, not all hw sign-extends above the physical width
102 delta
= (new_raw_count
<< shift
) - (prev_raw_count
<< shift
);
105 local64_add(delta
, &event
->count
);
106 local64_sub(delta
, &hwc
->period_left
);
108 return new_raw_count
;
112 * Find and validate any extra registers to set up.
114 static int x86_pmu_extra_regs(u64 config
, struct perf_event
*event
)
116 struct hw_perf_event_extra
*reg
;
117 struct extra_reg
*er
;
119 reg
= &event
->hw
.extra_reg
;
121 if (!x86_pmu
.extra_regs
)
124 for (er
= x86_pmu
.extra_regs
; er
->msr
; er
++) {
125 if (er
->event
!= (config
& er
->config_mask
))
127 if (event
->attr
.config1
& ~er
->valid_mask
)
129 /* Check if the extra msrs can be safely accessed*/
130 if (!er
->extra_msr_access
)
134 reg
->config
= event
->attr
.config1
;
141 static atomic_t active_events
;
142 static atomic_t pmc_refcount
;
143 static DEFINE_MUTEX(pmc_reserve_mutex
);
145 #ifdef CONFIG_X86_LOCAL_APIC
147 static bool reserve_pmc_hardware(void)
151 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
152 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i
)))
156 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
157 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i
)))
164 for (i
--; i
>= 0; i
--)
165 release_evntsel_nmi(x86_pmu_config_addr(i
));
167 i
= x86_pmu
.num_counters
;
170 for (i
--; i
>= 0; i
--)
171 release_perfctr_nmi(x86_pmu_event_addr(i
));
176 static void release_pmc_hardware(void)
180 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
181 release_perfctr_nmi(x86_pmu_event_addr(i
));
182 release_evntsel_nmi(x86_pmu_config_addr(i
));
188 static bool reserve_pmc_hardware(void) { return true; }
189 static void release_pmc_hardware(void) {}
193 static bool check_hw_exists(void)
195 u64 val
, val_fail
= -1, val_new
= ~0;
196 int i
, reg
, reg_fail
= -1, ret
= 0;
201 * Check to see if the BIOS enabled any of the counters, if so
204 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
205 reg
= x86_pmu_config_addr(i
);
206 ret
= rdmsrl_safe(reg
, &val
);
209 if (val
& ARCH_PERFMON_EVENTSEL_ENABLE
) {
218 if (x86_pmu
.num_counters_fixed
) {
219 reg
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
220 ret
= rdmsrl_safe(reg
, &val
);
223 for (i
= 0; i
< x86_pmu
.num_counters_fixed
; i
++) {
224 if (val
& (0x03 << i
*4)) {
233 * If all the counters are enabled, the below test will always
234 * fail. The tools will also become useless in this scenario.
235 * Just fail and disable the hardware counters.
238 if (reg_safe
== -1) {
244 * Read the current value, change it and read it back to see if it
245 * matches, this is needed to detect certain hardware emulators
246 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
248 reg
= x86_pmu_event_addr(reg_safe
);
249 if (rdmsrl_safe(reg
, &val
))
252 ret
= wrmsrl_safe(reg
, val
);
253 ret
|= rdmsrl_safe(reg
, &val_new
);
254 if (ret
|| val
!= val_new
)
258 * We still allow the PMU driver to operate:
261 pr_cont("Broken BIOS detected, complain to your hardware vendor.\n");
262 pr_err(FW_BUG
"the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n",
269 if (boot_cpu_has(X86_FEATURE_HYPERVISOR
)) {
270 pr_cont("PMU not available due to virtualization, using software events only.\n");
272 pr_cont("Broken PMU hardware detected, using software events only.\n");
273 pr_err("Failed to access perfctr msr (MSR %x is %Lx)\n",
280 static void hw_perf_event_destroy(struct perf_event
*event
)
282 x86_release_hardware();
283 atomic_dec(&active_events
);
286 void hw_perf_lbr_event_destroy(struct perf_event
*event
)
288 hw_perf_event_destroy(event
);
290 /* undo the lbr/bts event accounting */
291 x86_del_exclusive(x86_lbr_exclusive_lbr
);
294 static inline int x86_pmu_initialized(void)
296 return x86_pmu
.handle_irq
!= NULL
;
300 set_ext_hw_attr(struct hw_perf_event
*hwc
, struct perf_event
*event
)
302 struct perf_event_attr
*attr
= &event
->attr
;
303 unsigned int cache_type
, cache_op
, cache_result
;
306 config
= attr
->config
;
308 cache_type
= (config
>> 0) & 0xff;
309 if (cache_type
>= PERF_COUNT_HW_CACHE_MAX
)
311 cache_type
= array_index_nospec(cache_type
, PERF_COUNT_HW_CACHE_MAX
);
313 cache_op
= (config
>> 8) & 0xff;
314 if (cache_op
>= PERF_COUNT_HW_CACHE_OP_MAX
)
316 cache_op
= array_index_nospec(cache_op
, PERF_COUNT_HW_CACHE_OP_MAX
);
318 cache_result
= (config
>> 16) & 0xff;
319 if (cache_result
>= PERF_COUNT_HW_CACHE_RESULT_MAX
)
321 cache_result
= array_index_nospec(cache_result
, PERF_COUNT_HW_CACHE_RESULT_MAX
);
323 val
= hw_cache_event_ids
[cache_type
][cache_op
][cache_result
];
332 attr
->config1
= hw_cache_extra_regs
[cache_type
][cache_op
][cache_result
];
333 return x86_pmu_extra_regs(val
, event
);
336 int x86_reserve_hardware(void)
340 if (!atomic_inc_not_zero(&pmc_refcount
)) {
341 mutex_lock(&pmc_reserve_mutex
);
342 if (atomic_read(&pmc_refcount
) == 0) {
343 if (!reserve_pmc_hardware())
346 reserve_ds_buffers();
349 atomic_inc(&pmc_refcount
);
350 mutex_unlock(&pmc_reserve_mutex
);
356 void x86_release_hardware(void)
358 if (atomic_dec_and_mutex_lock(&pmc_refcount
, &pmc_reserve_mutex
)) {
359 release_pmc_hardware();
360 release_ds_buffers();
361 mutex_unlock(&pmc_reserve_mutex
);
366 * Check if we can create event of a certain type (that no conflicting events
369 int x86_add_exclusive(unsigned int what
)
374 * When lbr_pt_coexist we allow PT to coexist with either LBR or BTS.
375 * LBR and BTS are still mutually exclusive.
377 if (x86_pmu
.lbr_pt_coexist
&& what
== x86_lbr_exclusive_pt
)
380 if (!atomic_inc_not_zero(&x86_pmu
.lbr_exclusive
[what
])) {
381 mutex_lock(&pmc_reserve_mutex
);
382 for (i
= 0; i
< ARRAY_SIZE(x86_pmu
.lbr_exclusive
); i
++) {
383 if (i
!= what
&& atomic_read(&x86_pmu
.lbr_exclusive
[i
]))
386 atomic_inc(&x86_pmu
.lbr_exclusive
[what
]);
387 mutex_unlock(&pmc_reserve_mutex
);
390 atomic_inc(&active_events
);
394 mutex_unlock(&pmc_reserve_mutex
);
398 void x86_del_exclusive(unsigned int what
)
400 if (x86_pmu
.lbr_pt_coexist
&& what
== x86_lbr_exclusive_pt
)
403 atomic_dec(&x86_pmu
.lbr_exclusive
[what
]);
404 atomic_dec(&active_events
);
407 int x86_setup_perfctr(struct perf_event
*event
)
409 struct perf_event_attr
*attr
= &event
->attr
;
410 struct hw_perf_event
*hwc
= &event
->hw
;
413 if (!is_sampling_event(event
)) {
414 hwc
->sample_period
= x86_pmu
.max_period
;
415 hwc
->last_period
= hwc
->sample_period
;
416 local64_set(&hwc
->period_left
, hwc
->sample_period
);
419 if (attr
->type
== PERF_TYPE_RAW
)
420 return x86_pmu_extra_regs(event
->attr
.config
, event
);
422 if (attr
->type
== PERF_TYPE_HW_CACHE
)
423 return set_ext_hw_attr(hwc
, event
);
425 if (attr
->config
>= x86_pmu
.max_events
)
428 attr
->config
= array_index_nospec((unsigned long)attr
->config
, x86_pmu
.max_events
);
433 config
= x86_pmu
.event_map(attr
->config
);
441 hwc
->config
|= config
;
447 * check that branch_sample_type is compatible with
448 * settings needed for precise_ip > 1 which implies
449 * using the LBR to capture ALL taken branches at the
450 * priv levels of the measurement
452 static inline int precise_br_compat(struct perf_event
*event
)
454 u64 m
= event
->attr
.branch_sample_type
;
457 /* must capture all branches */
458 if (!(m
& PERF_SAMPLE_BRANCH_ANY
))
461 m
&= PERF_SAMPLE_BRANCH_KERNEL
| PERF_SAMPLE_BRANCH_USER
;
463 if (!event
->attr
.exclude_user
)
464 b
|= PERF_SAMPLE_BRANCH_USER
;
466 if (!event
->attr
.exclude_kernel
)
467 b
|= PERF_SAMPLE_BRANCH_KERNEL
;
470 * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
476 int x86_pmu_max_precise(void)
480 /* Support for constant skid */
481 if (x86_pmu
.pebs_active
&& !x86_pmu
.pebs_broken
) {
484 /* Support for IP fixup */
485 if (x86_pmu
.lbr_nr
|| x86_pmu
.intel_cap
.pebs_format
>= 2)
488 if (x86_pmu
.pebs_prec_dist
)
494 int x86_pmu_hw_config(struct perf_event
*event
)
496 if (event
->attr
.precise_ip
) {
497 int precise
= x86_pmu_max_precise();
499 if (event
->attr
.precise_ip
> precise
)
502 /* There's no sense in having PEBS for non sampling events: */
503 if (!is_sampling_event(event
))
507 * check that PEBS LBR correction does not conflict with
508 * whatever the user is asking with attr->branch_sample_type
510 if (event
->attr
.precise_ip
> 1 && x86_pmu
.intel_cap
.pebs_format
< 2) {
511 u64
*br_type
= &event
->attr
.branch_sample_type
;
513 if (has_branch_stack(event
)) {
514 if (!precise_br_compat(event
))
517 /* branch_sample_type is compatible */
521 * user did not specify branch_sample_type
523 * For PEBS fixups, we capture all
524 * the branches at the priv level of the
527 *br_type
= PERF_SAMPLE_BRANCH_ANY
;
529 if (!event
->attr
.exclude_user
)
530 *br_type
|= PERF_SAMPLE_BRANCH_USER
;
532 if (!event
->attr
.exclude_kernel
)
533 *br_type
|= PERF_SAMPLE_BRANCH_KERNEL
;
537 if (event
->attr
.branch_sample_type
& PERF_SAMPLE_BRANCH_CALL_STACK
)
538 event
->attach_state
|= PERF_ATTACH_TASK_DATA
;
542 * (keep 'enabled' bit clear for now)
544 event
->hw
.config
= ARCH_PERFMON_EVENTSEL_INT
;
547 * Count user and OS events unless requested not to
549 if (!event
->attr
.exclude_user
)
550 event
->hw
.config
|= ARCH_PERFMON_EVENTSEL_USR
;
551 if (!event
->attr
.exclude_kernel
)
552 event
->hw
.config
|= ARCH_PERFMON_EVENTSEL_OS
;
554 if (event
->attr
.type
== PERF_TYPE_RAW
)
555 event
->hw
.config
|= event
->attr
.config
& X86_RAW_EVENT_MASK
;
557 if (event
->attr
.sample_period
&& x86_pmu
.limit_period
) {
558 if (x86_pmu
.limit_period(event
, event
->attr
.sample_period
) >
559 event
->attr
.sample_period
)
563 return x86_setup_perfctr(event
);
567 * Setup the hardware configuration for a given attr_type
569 static int __x86_pmu_event_init(struct perf_event
*event
)
573 if (!x86_pmu_initialized())
576 err
= x86_reserve_hardware();
580 atomic_inc(&active_events
);
581 event
->destroy
= hw_perf_event_destroy
;
584 event
->hw
.last_cpu
= -1;
585 event
->hw
.last_tag
= ~0ULL;
588 event
->hw
.extra_reg
.idx
= EXTRA_REG_NONE
;
589 event
->hw
.branch_reg
.idx
= EXTRA_REG_NONE
;
591 return x86_pmu
.hw_config(event
);
594 void x86_pmu_disable_all(void)
596 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
599 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
602 if (!test_bit(idx
, cpuc
->active_mask
))
604 rdmsrl(x86_pmu_config_addr(idx
), val
);
605 if (!(val
& ARCH_PERFMON_EVENTSEL_ENABLE
))
607 val
&= ~ARCH_PERFMON_EVENTSEL_ENABLE
;
608 wrmsrl(x86_pmu_config_addr(idx
), val
);
613 * There may be PMI landing after enabled=0. The PMI hitting could be before or
616 * If PMI hits before disable_all, the PMU will be disabled in the NMI handler.
617 * It will not be re-enabled in the NMI handler again, because enabled=0. After
618 * handling the NMI, disable_all will be called, which will not change the
619 * state either. If PMI hits after disable_all, the PMU is already disabled
620 * before entering NMI handler. The NMI handler will not change the state
623 * So either situation is harmless.
625 static void x86_pmu_disable(struct pmu
*pmu
)
627 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
629 if (!x86_pmu_initialized())
639 x86_pmu
.disable_all();
642 void x86_pmu_enable_all(int added
)
644 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
647 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
648 struct hw_perf_event
*hwc
= &cpuc
->events
[idx
]->hw
;
650 if (!test_bit(idx
, cpuc
->active_mask
))
653 __x86_pmu_enable_event(hwc
, ARCH_PERFMON_EVENTSEL_ENABLE
);
657 static struct pmu pmu
;
659 static inline int is_x86_event(struct perf_event
*event
)
661 return event
->pmu
== &pmu
;
665 * Event scheduler state:
667 * Assign events iterating over all events and counters, beginning
668 * with events with least weights first. Keep the current iterator
669 * state in struct sched_state.
673 int event
; /* event index */
674 int counter
; /* counter index */
675 int unassigned
; /* number of events to be assigned left */
676 int nr_gp
; /* number of GP counters used */
677 unsigned long used
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
680 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
681 #define SCHED_STATES_MAX 2
688 struct event_constraint
**constraints
;
689 struct sched_state state
;
690 struct sched_state saved
[SCHED_STATES_MAX
];
694 * Initialize interator that runs through all events and counters.
696 static void perf_sched_init(struct perf_sched
*sched
, struct event_constraint
**constraints
,
697 int num
, int wmin
, int wmax
, int gpmax
)
701 memset(sched
, 0, sizeof(*sched
));
702 sched
->max_events
= num
;
703 sched
->max_weight
= wmax
;
704 sched
->max_gp
= gpmax
;
705 sched
->constraints
= constraints
;
707 for (idx
= 0; idx
< num
; idx
++) {
708 if (constraints
[idx
]->weight
== wmin
)
712 sched
->state
.event
= idx
; /* start with min weight */
713 sched
->state
.weight
= wmin
;
714 sched
->state
.unassigned
= num
;
717 static void perf_sched_save_state(struct perf_sched
*sched
)
719 if (WARN_ON_ONCE(sched
->saved_states
>= SCHED_STATES_MAX
))
722 sched
->saved
[sched
->saved_states
] = sched
->state
;
723 sched
->saved_states
++;
726 static bool perf_sched_restore_state(struct perf_sched
*sched
)
728 if (!sched
->saved_states
)
731 sched
->saved_states
--;
732 sched
->state
= sched
->saved
[sched
->saved_states
];
734 /* continue with next counter: */
735 clear_bit(sched
->state
.counter
++, sched
->state
.used
);
741 * Select a counter for the current event to schedule. Return true on
744 static bool __perf_sched_find_counter(struct perf_sched
*sched
)
746 struct event_constraint
*c
;
749 if (!sched
->state
.unassigned
)
752 if (sched
->state
.event
>= sched
->max_events
)
755 c
= sched
->constraints
[sched
->state
.event
];
756 /* Prefer fixed purpose counters */
757 if (c
->idxmsk64
& (~0ULL << INTEL_PMC_IDX_FIXED
)) {
758 idx
= INTEL_PMC_IDX_FIXED
;
759 for_each_set_bit_from(idx
, c
->idxmsk
, X86_PMC_IDX_MAX
) {
760 if (!__test_and_set_bit(idx
, sched
->state
.used
))
765 /* Grab the first unused counter starting with idx */
766 idx
= sched
->state
.counter
;
767 for_each_set_bit_from(idx
, c
->idxmsk
, INTEL_PMC_IDX_FIXED
) {
768 if (!__test_and_set_bit(idx
, sched
->state
.used
)) {
769 if (sched
->state
.nr_gp
++ >= sched
->max_gp
)
779 sched
->state
.counter
= idx
;
782 perf_sched_save_state(sched
);
787 static bool perf_sched_find_counter(struct perf_sched
*sched
)
789 while (!__perf_sched_find_counter(sched
)) {
790 if (!perf_sched_restore_state(sched
))
798 * Go through all unassigned events and find the next one to schedule.
799 * Take events with the least weight first. Return true on success.
801 static bool perf_sched_next_event(struct perf_sched
*sched
)
803 struct event_constraint
*c
;
805 if (!sched
->state
.unassigned
|| !--sched
->state
.unassigned
)
810 sched
->state
.event
++;
811 if (sched
->state
.event
>= sched
->max_events
) {
813 sched
->state
.event
= 0;
814 sched
->state
.weight
++;
815 if (sched
->state
.weight
> sched
->max_weight
)
818 c
= sched
->constraints
[sched
->state
.event
];
819 } while (c
->weight
!= sched
->state
.weight
);
821 sched
->state
.counter
= 0; /* start with first counter */
827 * Assign a counter for each event.
829 int perf_assign_events(struct event_constraint
**constraints
, int n
,
830 int wmin
, int wmax
, int gpmax
, int *assign
)
832 struct perf_sched sched
;
834 perf_sched_init(&sched
, constraints
, n
, wmin
, wmax
, gpmax
);
837 if (!perf_sched_find_counter(&sched
))
840 assign
[sched
.state
.event
] = sched
.state
.counter
;
841 } while (perf_sched_next_event(&sched
));
843 return sched
.state
.unassigned
;
845 EXPORT_SYMBOL_GPL(perf_assign_events
);
847 int x86_schedule_events(struct cpu_hw_events
*cpuc
, int n
, int *assign
)
849 struct event_constraint
*c
;
850 unsigned long used_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
851 struct perf_event
*e
;
852 int i
, wmin
, wmax
, unsched
= 0;
853 struct hw_perf_event
*hwc
;
855 bitmap_zero(used_mask
, X86_PMC_IDX_MAX
);
857 if (x86_pmu
.start_scheduling
)
858 x86_pmu
.start_scheduling(cpuc
);
860 for (i
= 0, wmin
= X86_PMC_IDX_MAX
, wmax
= 0; i
< n
; i
++) {
861 cpuc
->event_constraint
[i
] = NULL
;
862 c
= x86_pmu
.get_event_constraints(cpuc
, i
, cpuc
->event_list
[i
]);
863 cpuc
->event_constraint
[i
] = c
;
865 wmin
= min(wmin
, c
->weight
);
866 wmax
= max(wmax
, c
->weight
);
870 * fastpath, try to reuse previous register
872 for (i
= 0; i
< n
; i
++) {
873 hwc
= &cpuc
->event_list
[i
]->hw
;
874 c
= cpuc
->event_constraint
[i
];
880 /* constraint still honored */
881 if (!test_bit(hwc
->idx
, c
->idxmsk
))
884 /* not already used */
885 if (test_bit(hwc
->idx
, used_mask
))
888 __set_bit(hwc
->idx
, used_mask
);
890 assign
[i
] = hwc
->idx
;
895 int gpmax
= x86_pmu
.num_counters
;
898 * Do not allow scheduling of more than half the available
901 * This helps avoid counter starvation of sibling thread by
902 * ensuring at most half the counters cannot be in exclusive
903 * mode. There is no designated counters for the limits. Any
904 * N/2 counters can be used. This helps with events with
905 * specific counter constraints.
907 if (is_ht_workaround_enabled() && !cpuc
->is_fake
&&
908 READ_ONCE(cpuc
->excl_cntrs
->exclusive_present
))
911 unsched
= perf_assign_events(cpuc
->event_constraint
, n
, wmin
,
912 wmax
, gpmax
, assign
);
916 * In case of success (unsched = 0), mark events as committed,
917 * so we do not put_constraint() in case new events are added
918 * and fail to be scheduled
920 * We invoke the lower level commit callback to lock the resource
922 * We do not need to do all of this in case we are called to
923 * validate an event group (assign == NULL)
925 if (!unsched
&& assign
) {
926 for (i
= 0; i
< n
; i
++) {
927 e
= cpuc
->event_list
[i
];
928 e
->hw
.flags
|= PERF_X86_EVENT_COMMITTED
;
929 if (x86_pmu
.commit_scheduling
)
930 x86_pmu
.commit_scheduling(cpuc
, i
, assign
[i
]);
933 for (i
= 0; i
< n
; i
++) {
934 e
= cpuc
->event_list
[i
];
936 * do not put_constraint() on comitted events,
937 * because they are good to go
939 if ((e
->hw
.flags
& PERF_X86_EVENT_COMMITTED
))
943 * release events that failed scheduling
945 if (x86_pmu
.put_event_constraints
)
946 x86_pmu
.put_event_constraints(cpuc
, e
);
950 if (x86_pmu
.stop_scheduling
)
951 x86_pmu
.stop_scheduling(cpuc
);
953 return unsched
? -EINVAL
: 0;
957 * dogrp: true if must collect siblings events (group)
958 * returns total number of events and error code
960 static int collect_events(struct cpu_hw_events
*cpuc
, struct perf_event
*leader
, bool dogrp
)
962 struct perf_event
*event
;
965 max_count
= x86_pmu
.num_counters
+ x86_pmu
.num_counters_fixed
;
967 /* current number of events already accepted */
970 if (is_x86_event(leader
)) {
973 cpuc
->event_list
[n
] = leader
;
979 for_each_sibling_event(event
, leader
) {
980 if (!is_x86_event(event
) ||
981 event
->state
<= PERF_EVENT_STATE_OFF
)
987 cpuc
->event_list
[n
] = event
;
993 static inline void x86_assign_hw_event(struct perf_event
*event
,
994 struct cpu_hw_events
*cpuc
, int i
)
996 struct hw_perf_event
*hwc
= &event
->hw
;
998 hwc
->idx
= cpuc
->assign
[i
];
999 hwc
->last_cpu
= smp_processor_id();
1000 hwc
->last_tag
= ++cpuc
->tags
[i
];
1002 if (hwc
->idx
== INTEL_PMC_IDX_FIXED_BTS
) {
1003 hwc
->config_base
= 0;
1004 hwc
->event_base
= 0;
1005 } else if (hwc
->idx
>= INTEL_PMC_IDX_FIXED
) {
1006 hwc
->config_base
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
1007 hwc
->event_base
= MSR_ARCH_PERFMON_FIXED_CTR0
+ (hwc
->idx
- INTEL_PMC_IDX_FIXED
);
1008 hwc
->event_base_rdpmc
= (hwc
->idx
- INTEL_PMC_IDX_FIXED
) | 1<<30;
1010 hwc
->config_base
= x86_pmu_config_addr(hwc
->idx
);
1011 hwc
->event_base
= x86_pmu_event_addr(hwc
->idx
);
1012 hwc
->event_base_rdpmc
= x86_pmu_rdpmc_index(hwc
->idx
);
1017 * x86_perf_rdpmc_index - Return PMC counter used for event
1018 * @event: the perf_event to which the PMC counter was assigned
1020 * The counter assigned to this performance event may change if interrupts
1021 * are enabled. This counter should thus never be used while interrupts are
1022 * enabled. Before this function is used to obtain the assigned counter the
1023 * event should be checked for validity using, for example,
1024 * perf_event_read_local(), within the same interrupt disabled section in
1025 * which this counter is planned to be used.
1027 * Return: The index of the performance monitoring counter assigned to
1030 int x86_perf_rdpmc_index(struct perf_event
*event
)
1032 lockdep_assert_irqs_disabled();
1034 return event
->hw
.event_base_rdpmc
;
1037 static inline int match_prev_assignment(struct hw_perf_event
*hwc
,
1038 struct cpu_hw_events
*cpuc
,
1041 return hwc
->idx
== cpuc
->assign
[i
] &&
1042 hwc
->last_cpu
== smp_processor_id() &&
1043 hwc
->last_tag
== cpuc
->tags
[i
];
1046 static void x86_pmu_start(struct perf_event
*event
, int flags
);
1048 static void x86_pmu_enable(struct pmu
*pmu
)
1050 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1051 struct perf_event
*event
;
1052 struct hw_perf_event
*hwc
;
1053 int i
, added
= cpuc
->n_added
;
1055 if (!x86_pmu_initialized())
1061 if (cpuc
->n_added
) {
1062 int n_running
= cpuc
->n_events
- cpuc
->n_added
;
1064 * apply assignment obtained either from
1065 * hw_perf_group_sched_in() or x86_pmu_enable()
1067 * step1: save events moving to new counters
1069 for (i
= 0; i
< n_running
; i
++) {
1070 event
= cpuc
->event_list
[i
];
1074 * we can avoid reprogramming counter if:
1075 * - assigned same counter as last time
1076 * - running on same CPU as last time
1077 * - no other event has used the counter since
1079 if (hwc
->idx
== -1 ||
1080 match_prev_assignment(hwc
, cpuc
, i
))
1084 * Ensure we don't accidentally enable a stopped
1085 * counter simply because we rescheduled.
1087 if (hwc
->state
& PERF_HES_STOPPED
)
1088 hwc
->state
|= PERF_HES_ARCH
;
1090 x86_pmu_stop(event
, PERF_EF_UPDATE
);
1094 * step2: reprogram moved events into new counters
1096 for (i
= 0; i
< cpuc
->n_events
; i
++) {
1097 event
= cpuc
->event_list
[i
];
1100 if (!match_prev_assignment(hwc
, cpuc
, i
))
1101 x86_assign_hw_event(event
, cpuc
, i
);
1102 else if (i
< n_running
)
1105 if (hwc
->state
& PERF_HES_ARCH
)
1108 x86_pmu_start(event
, PERF_EF_RELOAD
);
1111 perf_events_lapic_init();
1117 x86_pmu
.enable_all(added
);
1120 static DEFINE_PER_CPU(u64
[X86_PMC_IDX_MAX
], pmc_prev_left
);
1123 * Set the next IRQ period, based on the hwc->period_left value.
1124 * To be called with the event disabled in hw:
1126 int x86_perf_event_set_period(struct perf_event
*event
)
1128 struct hw_perf_event
*hwc
= &event
->hw
;
1129 s64 left
= local64_read(&hwc
->period_left
);
1130 s64 period
= hwc
->sample_period
;
1131 int ret
= 0, idx
= hwc
->idx
;
1133 if (idx
== INTEL_PMC_IDX_FIXED_BTS
)
1137 * If we are way outside a reasonable range then just skip forward:
1139 if (unlikely(left
<= -period
)) {
1141 local64_set(&hwc
->period_left
, left
);
1142 hwc
->last_period
= period
;
1146 if (unlikely(left
<= 0)) {
1148 local64_set(&hwc
->period_left
, left
);
1149 hwc
->last_period
= period
;
1153 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1155 if (unlikely(left
< 2))
1158 if (left
> x86_pmu
.max_period
)
1159 left
= x86_pmu
.max_period
;
1161 if (x86_pmu
.limit_period
)
1162 left
= x86_pmu
.limit_period(event
, left
);
1164 per_cpu(pmc_prev_left
[idx
], smp_processor_id()) = left
;
1167 * The hw event starts counting from this event offset,
1168 * mark it to be able to extra future deltas:
1170 local64_set(&hwc
->prev_count
, (u64
)-left
);
1172 wrmsrl(hwc
->event_base
, (u64
)(-left
) & x86_pmu
.cntval_mask
);
1175 * Due to erratum on certan cpu we need
1176 * a second write to be sure the register
1177 * is updated properly
1179 if (x86_pmu
.perfctr_second_write
) {
1180 wrmsrl(hwc
->event_base
,
1181 (u64
)(-left
) & x86_pmu
.cntval_mask
);
1184 perf_event_update_userpage(event
);
1189 void x86_pmu_enable_event(struct perf_event
*event
)
1191 if (__this_cpu_read(cpu_hw_events
.enabled
))
1192 __x86_pmu_enable_event(&event
->hw
,
1193 ARCH_PERFMON_EVENTSEL_ENABLE
);
1197 * Add a single event to the PMU.
1199 * The event is added to the group of enabled events
1200 * but only if it can be scehduled with existing events.
1202 static int x86_pmu_add(struct perf_event
*event
, int flags
)
1204 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1205 struct hw_perf_event
*hwc
;
1206 int assign
[X86_PMC_IDX_MAX
];
1211 n0
= cpuc
->n_events
;
1212 ret
= n
= collect_events(cpuc
, event
, false);
1216 hwc
->state
= PERF_HES_UPTODATE
| PERF_HES_STOPPED
;
1217 if (!(flags
& PERF_EF_START
))
1218 hwc
->state
|= PERF_HES_ARCH
;
1221 * If group events scheduling transaction was started,
1222 * skip the schedulability test here, it will be performed
1223 * at commit time (->commit_txn) as a whole.
1225 * If commit fails, we'll call ->del() on all events
1226 * for which ->add() was called.
1228 if (cpuc
->txn_flags
& PERF_PMU_TXN_ADD
)
1231 ret
= x86_pmu
.schedule_events(cpuc
, n
, assign
);
1235 * copy new assignment, now we know it is possible
1236 * will be used by hw_perf_enable()
1238 memcpy(cpuc
->assign
, assign
, n
*sizeof(int));
1242 * Commit the collect_events() state. See x86_pmu_del() and
1246 cpuc
->n_added
+= n
- n0
;
1247 cpuc
->n_txn
+= n
- n0
;
1251 * This is before x86_pmu_enable() will call x86_pmu_start(),
1252 * so we enable LBRs before an event needs them etc..
1262 static void x86_pmu_start(struct perf_event
*event
, int flags
)
1264 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1265 int idx
= event
->hw
.idx
;
1267 if (WARN_ON_ONCE(!(event
->hw
.state
& PERF_HES_STOPPED
)))
1270 if (WARN_ON_ONCE(idx
== -1))
1273 if (flags
& PERF_EF_RELOAD
) {
1274 WARN_ON_ONCE(!(event
->hw
.state
& PERF_HES_UPTODATE
));
1275 x86_perf_event_set_period(event
);
1278 event
->hw
.state
= 0;
1280 cpuc
->events
[idx
] = event
;
1281 __set_bit(idx
, cpuc
->active_mask
);
1282 __set_bit(idx
, cpuc
->running
);
1283 x86_pmu
.enable(event
);
1284 perf_event_update_userpage(event
);
1287 void perf_event_print_debug(void)
1289 u64 ctrl
, status
, overflow
, pmc_ctrl
, pmc_count
, prev_left
, fixed
;
1291 struct cpu_hw_events
*cpuc
;
1292 unsigned long flags
;
1295 if (!x86_pmu
.num_counters
)
1298 local_irq_save(flags
);
1300 cpu
= smp_processor_id();
1301 cpuc
= &per_cpu(cpu_hw_events
, cpu
);
1303 if (x86_pmu
.version
>= 2) {
1304 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
1305 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
1306 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, overflow
);
1307 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL
, fixed
);
1310 pr_info("CPU#%d: ctrl: %016llx\n", cpu
, ctrl
);
1311 pr_info("CPU#%d: status: %016llx\n", cpu
, status
);
1312 pr_info("CPU#%d: overflow: %016llx\n", cpu
, overflow
);
1313 pr_info("CPU#%d: fixed: %016llx\n", cpu
, fixed
);
1314 if (x86_pmu
.pebs_constraints
) {
1315 rdmsrl(MSR_IA32_PEBS_ENABLE
, pebs
);
1316 pr_info("CPU#%d: pebs: %016llx\n", cpu
, pebs
);
1318 if (x86_pmu
.lbr_nr
) {
1319 rdmsrl(MSR_IA32_DEBUGCTLMSR
, debugctl
);
1320 pr_info("CPU#%d: debugctl: %016llx\n", cpu
, debugctl
);
1323 pr_info("CPU#%d: active: %016llx\n", cpu
, *(u64
*)cpuc
->active_mask
);
1325 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1326 rdmsrl(x86_pmu_config_addr(idx
), pmc_ctrl
);
1327 rdmsrl(x86_pmu_event_addr(idx
), pmc_count
);
1329 prev_left
= per_cpu(pmc_prev_left
[idx
], cpu
);
1331 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1332 cpu
, idx
, pmc_ctrl
);
1333 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1334 cpu
, idx
, pmc_count
);
1335 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1336 cpu
, idx
, prev_left
);
1338 for (idx
= 0; idx
< x86_pmu
.num_counters_fixed
; idx
++) {
1339 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0
+ idx
, pmc_count
);
1341 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1342 cpu
, idx
, pmc_count
);
1344 local_irq_restore(flags
);
1347 void x86_pmu_stop(struct perf_event
*event
, int flags
)
1349 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1350 struct hw_perf_event
*hwc
= &event
->hw
;
1352 if (__test_and_clear_bit(hwc
->idx
, cpuc
->active_mask
)) {
1353 x86_pmu
.disable(event
);
1354 cpuc
->events
[hwc
->idx
] = NULL
;
1355 WARN_ON_ONCE(hwc
->state
& PERF_HES_STOPPED
);
1356 hwc
->state
|= PERF_HES_STOPPED
;
1359 if ((flags
& PERF_EF_UPDATE
) && !(hwc
->state
& PERF_HES_UPTODATE
)) {
1361 * Drain the remaining delta count out of a event
1362 * that we are disabling:
1364 x86_perf_event_update(event
);
1365 hwc
->state
|= PERF_HES_UPTODATE
;
1369 static void x86_pmu_del(struct perf_event
*event
, int flags
)
1371 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1375 * event is descheduled
1377 event
->hw
.flags
&= ~PERF_X86_EVENT_COMMITTED
;
1380 * If we're called during a txn, we only need to undo x86_pmu.add.
1381 * The events never got scheduled and ->cancel_txn will truncate
1384 * XXX assumes any ->del() called during a TXN will only be on
1385 * an event added during that same TXN.
1387 if (cpuc
->txn_flags
& PERF_PMU_TXN_ADD
)
1391 * Not a TXN, therefore cleanup properly.
1393 x86_pmu_stop(event
, PERF_EF_UPDATE
);
1395 for (i
= 0; i
< cpuc
->n_events
; i
++) {
1396 if (event
== cpuc
->event_list
[i
])
1400 if (WARN_ON_ONCE(i
== cpuc
->n_events
)) /* called ->del() without ->add() ? */
1403 /* If we have a newly added event; make sure to decrease n_added. */
1404 if (i
>= cpuc
->n_events
- cpuc
->n_added
)
1407 if (x86_pmu
.put_event_constraints
)
1408 x86_pmu
.put_event_constraints(cpuc
, event
);
1410 /* Delete the array entry. */
1411 while (++i
< cpuc
->n_events
) {
1412 cpuc
->event_list
[i
-1] = cpuc
->event_list
[i
];
1413 cpuc
->event_constraint
[i
-1] = cpuc
->event_constraint
[i
];
1417 perf_event_update_userpage(event
);
1422 * This is after x86_pmu_stop(); so we disable LBRs after any
1423 * event can need them etc..
1429 int x86_pmu_handle_irq(struct pt_regs
*regs
)
1431 struct perf_sample_data data
;
1432 struct cpu_hw_events
*cpuc
;
1433 struct perf_event
*event
;
1434 int idx
, handled
= 0;
1437 cpuc
= this_cpu_ptr(&cpu_hw_events
);
1440 * Some chipsets need to unmask the LVTPC in a particular spot
1441 * inside the nmi handler. As a result, the unmasking was pushed
1442 * into all the nmi handlers.
1444 * This generic handler doesn't seem to have any issues where the
1445 * unmasking occurs so it was left at the top.
1447 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1449 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1450 if (!test_bit(idx
, cpuc
->active_mask
)) {
1452 * Though we deactivated the counter some cpus
1453 * might still deliver spurious interrupts still
1454 * in flight. Catch them:
1456 if (__test_and_clear_bit(idx
, cpuc
->running
))
1461 event
= cpuc
->events
[idx
];
1463 val
= x86_perf_event_update(event
);
1464 if (val
& (1ULL << (x86_pmu
.cntval_bits
- 1)))
1471 perf_sample_data_init(&data
, 0, event
->hw
.last_period
);
1473 if (!x86_perf_event_set_period(event
))
1476 if (perf_event_overflow(event
, &data
, regs
))
1477 x86_pmu_stop(event
, 0);
1481 inc_irq_stat(apic_perf_irqs
);
1486 void perf_events_lapic_init(void)
1488 if (!x86_pmu
.apic
|| !x86_pmu_initialized())
1492 * Always use NMI for PMU
1494 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1498 perf_event_nmi_handler(unsigned int cmd
, struct pt_regs
*regs
)
1505 * All PMUs/events that share this PMI handler should make sure to
1506 * increment active_events for their events.
1508 if (!atomic_read(&active_events
))
1511 start_clock
= sched_clock();
1512 ret
= x86_pmu
.handle_irq(regs
);
1513 finish_clock
= sched_clock();
1515 perf_sample_event_took(finish_clock
- start_clock
);
1519 NOKPROBE_SYMBOL(perf_event_nmi_handler
);
1521 struct event_constraint emptyconstraint
;
1522 struct event_constraint unconstrained
;
1524 static int x86_pmu_prepare_cpu(unsigned int cpu
)
1526 struct cpu_hw_events
*cpuc
= &per_cpu(cpu_hw_events
, cpu
);
1529 for (i
= 0 ; i
< X86_PERF_KFREE_MAX
; i
++)
1530 cpuc
->kfree_on_online
[i
] = NULL
;
1531 if (x86_pmu
.cpu_prepare
)
1532 return x86_pmu
.cpu_prepare(cpu
);
1536 static int x86_pmu_dead_cpu(unsigned int cpu
)
1538 if (x86_pmu
.cpu_dead
)
1539 x86_pmu
.cpu_dead(cpu
);
1543 static int x86_pmu_online_cpu(unsigned int cpu
)
1545 struct cpu_hw_events
*cpuc
= &per_cpu(cpu_hw_events
, cpu
);
1548 for (i
= 0 ; i
< X86_PERF_KFREE_MAX
; i
++) {
1549 kfree(cpuc
->kfree_on_online
[i
]);
1550 cpuc
->kfree_on_online
[i
] = NULL
;
1555 static int x86_pmu_starting_cpu(unsigned int cpu
)
1557 if (x86_pmu
.cpu_starting
)
1558 x86_pmu
.cpu_starting(cpu
);
1562 static int x86_pmu_dying_cpu(unsigned int cpu
)
1564 if (x86_pmu
.cpu_dying
)
1565 x86_pmu
.cpu_dying(cpu
);
1569 static void __init
pmu_check_apic(void)
1571 if (boot_cpu_has(X86_FEATURE_APIC
))
1575 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1576 pr_info("no hardware sampling interrupt available.\n");
1579 * If we have a PMU initialized but no APIC
1580 * interrupts, we cannot sample hardware
1581 * events (user-space has to fall back and
1582 * sample via a hrtimer based software event):
1584 pmu
.capabilities
|= PERF_PMU_CAP_NO_INTERRUPT
;
1588 static struct attribute_group x86_pmu_format_group __ro_after_init
= {
1594 * Remove all undefined events (x86_pmu.event_map(id) == 0)
1595 * out of events_attr attributes.
1597 static void __init
filter_events(struct attribute
**attrs
)
1599 struct device_attribute
*d
;
1600 struct perf_pmu_events_attr
*pmu_attr
;
1604 for (i
= 0; attrs
[i
]; i
++) {
1605 d
= (struct device_attribute
*)attrs
[i
];
1606 pmu_attr
= container_of(d
, struct perf_pmu_events_attr
, attr
);
1608 if (pmu_attr
->event_str
)
1610 if (x86_pmu
.event_map(i
+ offset
))
1613 for (j
= i
; attrs
[j
]; j
++)
1614 attrs
[j
] = attrs
[j
+ 1];
1616 /* Check the shifted attr. */
1620 * event_map() is index based, the attrs array is organized
1621 * by increasing event index. If we shift the events, then
1622 * we need to compensate for the event_map(), otherwise
1623 * we are looking up the wrong event in the map
1629 /* Merge two pointer arrays */
1630 __init
struct attribute
**merge_attr(struct attribute
**a
, struct attribute
**b
)
1632 struct attribute
**new;
1635 for (j
= 0; a
&& a
[j
]; j
++)
1637 for (i
= 0; b
&& b
[i
]; i
++)
1641 new = kmalloc_array(j
, sizeof(struct attribute
*), GFP_KERNEL
);
1646 for (i
= 0; a
&& a
[i
]; i
++)
1648 for (i
= 0; b
&& b
[i
]; i
++)
1655 ssize_t
events_sysfs_show(struct device
*dev
, struct device_attribute
*attr
, char *page
)
1657 struct perf_pmu_events_attr
*pmu_attr
= \
1658 container_of(attr
, struct perf_pmu_events_attr
, attr
);
1659 u64 config
= x86_pmu
.event_map(pmu_attr
->id
);
1661 /* string trumps id */
1662 if (pmu_attr
->event_str
)
1663 return sprintf(page
, "%s", pmu_attr
->event_str
);
1665 return x86_pmu
.events_sysfs_show(page
, config
);
1667 EXPORT_SYMBOL_GPL(events_sysfs_show
);
1669 ssize_t
events_ht_sysfs_show(struct device
*dev
, struct device_attribute
*attr
,
1672 struct perf_pmu_events_ht_attr
*pmu_attr
=
1673 container_of(attr
, struct perf_pmu_events_ht_attr
, attr
);
1676 * Report conditional events depending on Hyper-Threading.
1678 * This is overly conservative as usually the HT special
1679 * handling is not needed if the other CPU thread is idle.
1681 * Note this does not (and cannot) handle the case when thread
1682 * siblings are invisible, for example with virtualization
1683 * if they are owned by some other guest. The user tool
1684 * has to re-read when a thread sibling gets onlined later.
1686 return sprintf(page
, "%s",
1687 topology_max_smt_threads() > 1 ?
1688 pmu_attr
->event_str_ht
:
1689 pmu_attr
->event_str_noht
);
1692 EVENT_ATTR(cpu
-cycles
, CPU_CYCLES
);
1693 EVENT_ATTR(instructions
, INSTRUCTIONS
);
1694 EVENT_ATTR(cache
-references
, CACHE_REFERENCES
);
1695 EVENT_ATTR(cache
-misses
, CACHE_MISSES
);
1696 EVENT_ATTR(branch
-instructions
, BRANCH_INSTRUCTIONS
);
1697 EVENT_ATTR(branch
-misses
, BRANCH_MISSES
);
1698 EVENT_ATTR(bus
-cycles
, BUS_CYCLES
);
1699 EVENT_ATTR(stalled
-cycles
-frontend
, STALLED_CYCLES_FRONTEND
);
1700 EVENT_ATTR(stalled
-cycles
-backend
, STALLED_CYCLES_BACKEND
);
1701 EVENT_ATTR(ref
-cycles
, REF_CPU_CYCLES
);
1703 static struct attribute
*empty_attrs
;
1705 static struct attribute
*events_attr
[] = {
1706 EVENT_PTR(CPU_CYCLES
),
1707 EVENT_PTR(INSTRUCTIONS
),
1708 EVENT_PTR(CACHE_REFERENCES
),
1709 EVENT_PTR(CACHE_MISSES
),
1710 EVENT_PTR(BRANCH_INSTRUCTIONS
),
1711 EVENT_PTR(BRANCH_MISSES
),
1712 EVENT_PTR(BUS_CYCLES
),
1713 EVENT_PTR(STALLED_CYCLES_FRONTEND
),
1714 EVENT_PTR(STALLED_CYCLES_BACKEND
),
1715 EVENT_PTR(REF_CPU_CYCLES
),
1719 static struct attribute_group x86_pmu_events_group __ro_after_init
= {
1721 .attrs
= events_attr
,
1724 ssize_t
x86_event_sysfs_show(char *page
, u64 config
, u64 event
)
1726 u64 umask
= (config
& ARCH_PERFMON_EVENTSEL_UMASK
) >> 8;
1727 u64 cmask
= (config
& ARCH_PERFMON_EVENTSEL_CMASK
) >> 24;
1728 bool edge
= (config
& ARCH_PERFMON_EVENTSEL_EDGE
);
1729 bool pc
= (config
& ARCH_PERFMON_EVENTSEL_PIN_CONTROL
);
1730 bool any
= (config
& ARCH_PERFMON_EVENTSEL_ANY
);
1731 bool inv
= (config
& ARCH_PERFMON_EVENTSEL_INV
);
1735 * We have whole page size to spend and just little data
1736 * to write, so we can safely use sprintf.
1738 ret
= sprintf(page
, "event=0x%02llx", event
);
1741 ret
+= sprintf(page
+ ret
, ",umask=0x%02llx", umask
);
1744 ret
+= sprintf(page
+ ret
, ",edge");
1747 ret
+= sprintf(page
+ ret
, ",pc");
1750 ret
+= sprintf(page
+ ret
, ",any");
1753 ret
+= sprintf(page
+ ret
, ",inv");
1756 ret
+= sprintf(page
+ ret
, ",cmask=0x%02llx", cmask
);
1758 ret
+= sprintf(page
+ ret
, "\n");
1763 static struct attribute_group x86_pmu_attr_group
;
1764 static struct attribute_group x86_pmu_caps_group
;
1766 static int __init
init_hw_perf_events(void)
1768 struct x86_pmu_quirk
*quirk
;
1771 pr_info("Performance Events: ");
1773 switch (boot_cpu_data
.x86_vendor
) {
1774 case X86_VENDOR_INTEL
:
1775 err
= intel_pmu_init();
1777 case X86_VENDOR_AMD
:
1778 err
= amd_pmu_init();
1780 case X86_VENDOR_HYGON
:
1781 err
= amd_pmu_init();
1782 x86_pmu
.name
= "HYGON";
1788 pr_cont("no PMU driver, software events only.\n");
1794 /* sanity check that the hardware exists or is emulated */
1795 if (!check_hw_exists())
1798 pr_cont("%s PMU driver.\n", x86_pmu
.name
);
1800 x86_pmu
.attr_rdpmc
= 1; /* enable userspace RDPMC usage by default */
1802 for (quirk
= x86_pmu
.quirks
; quirk
; quirk
= quirk
->next
)
1805 if (!x86_pmu
.intel_ctrl
)
1806 x86_pmu
.intel_ctrl
= (1 << x86_pmu
.num_counters
) - 1;
1808 perf_events_lapic_init();
1809 register_nmi_handler(NMI_LOCAL
, perf_event_nmi_handler
, 0, "PMI");
1811 unconstrained
= (struct event_constraint
)
1812 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu
.num_counters
) - 1,
1813 0, x86_pmu
.num_counters
, 0, 0);
1815 x86_pmu_format_group
.attrs
= x86_pmu
.format_attrs
;
1817 if (x86_pmu
.caps_attrs
) {
1818 struct attribute
**tmp
;
1820 tmp
= merge_attr(x86_pmu_caps_group
.attrs
, x86_pmu
.caps_attrs
);
1822 x86_pmu_caps_group
.attrs
= tmp
;
1825 if (x86_pmu
.event_attrs
)
1826 x86_pmu_events_group
.attrs
= x86_pmu
.event_attrs
;
1828 if (!x86_pmu
.events_sysfs_show
)
1829 x86_pmu_events_group
.attrs
= &empty_attrs
;
1831 filter_events(x86_pmu_events_group
.attrs
);
1833 if (x86_pmu
.cpu_events
) {
1834 struct attribute
**tmp
;
1836 tmp
= merge_attr(x86_pmu_events_group
.attrs
, x86_pmu
.cpu_events
);
1838 x86_pmu_events_group
.attrs
= tmp
;
1841 if (x86_pmu
.attrs
) {
1842 struct attribute
**tmp
;
1844 tmp
= merge_attr(x86_pmu_attr_group
.attrs
, x86_pmu
.attrs
);
1846 x86_pmu_attr_group
.attrs
= tmp
;
1849 pr_info("... version: %d\n", x86_pmu
.version
);
1850 pr_info("... bit width: %d\n", x86_pmu
.cntval_bits
);
1851 pr_info("... generic registers: %d\n", x86_pmu
.num_counters
);
1852 pr_info("... value mask: %016Lx\n", x86_pmu
.cntval_mask
);
1853 pr_info("... max period: %016Lx\n", x86_pmu
.max_period
);
1854 pr_info("... fixed-purpose events: %d\n", x86_pmu
.num_counters_fixed
);
1855 pr_info("... event mask: %016Lx\n", x86_pmu
.intel_ctrl
);
1858 * Install callbacks. Core will call them for each online
1861 err
= cpuhp_setup_state(CPUHP_PERF_X86_PREPARE
, "perf/x86:prepare",
1862 x86_pmu_prepare_cpu
, x86_pmu_dead_cpu
);
1866 err
= cpuhp_setup_state(CPUHP_AP_PERF_X86_STARTING
,
1867 "perf/x86:starting", x86_pmu_starting_cpu
,
1872 err
= cpuhp_setup_state(CPUHP_AP_PERF_X86_ONLINE
, "perf/x86:online",
1873 x86_pmu_online_cpu
, NULL
);
1877 err
= perf_pmu_register(&pmu
, "cpu", PERF_TYPE_RAW
);
1884 cpuhp_remove_state(CPUHP_AP_PERF_X86_ONLINE
);
1886 cpuhp_remove_state(CPUHP_AP_PERF_X86_STARTING
);
1888 cpuhp_remove_state(CPUHP_PERF_X86_PREPARE
);
1891 early_initcall(init_hw_perf_events
);
1893 static inline void x86_pmu_read(struct perf_event
*event
)
1896 return x86_pmu
.read(event
);
1897 x86_perf_event_update(event
);
1901 * Start group events scheduling transaction
1902 * Set the flag to make pmu::enable() not perform the
1903 * schedulability test, it will be performed at commit time
1905 * We only support PERF_PMU_TXN_ADD transactions. Save the
1906 * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
1909 static void x86_pmu_start_txn(struct pmu
*pmu
, unsigned int txn_flags
)
1911 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1913 WARN_ON_ONCE(cpuc
->txn_flags
); /* txn already in flight */
1915 cpuc
->txn_flags
= txn_flags
;
1916 if (txn_flags
& ~PERF_PMU_TXN_ADD
)
1919 perf_pmu_disable(pmu
);
1920 __this_cpu_write(cpu_hw_events
.n_txn
, 0);
1924 * Stop group events scheduling transaction
1925 * Clear the flag and pmu::enable() will perform the
1926 * schedulability test.
1928 static void x86_pmu_cancel_txn(struct pmu
*pmu
)
1930 unsigned int txn_flags
;
1931 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1933 WARN_ON_ONCE(!cpuc
->txn_flags
); /* no txn in flight */
1935 txn_flags
= cpuc
->txn_flags
;
1936 cpuc
->txn_flags
= 0;
1937 if (txn_flags
& ~PERF_PMU_TXN_ADD
)
1941 * Truncate collected array by the number of events added in this
1942 * transaction. See x86_pmu_add() and x86_pmu_*_txn().
1944 __this_cpu_sub(cpu_hw_events
.n_added
, __this_cpu_read(cpu_hw_events
.n_txn
));
1945 __this_cpu_sub(cpu_hw_events
.n_events
, __this_cpu_read(cpu_hw_events
.n_txn
));
1946 perf_pmu_enable(pmu
);
1950 * Commit group events scheduling transaction
1951 * Perform the group schedulability test as a whole
1952 * Return 0 if success
1954 * Does not cancel the transaction on failure; expects the caller to do this.
1956 static int x86_pmu_commit_txn(struct pmu
*pmu
)
1958 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1959 int assign
[X86_PMC_IDX_MAX
];
1962 WARN_ON_ONCE(!cpuc
->txn_flags
); /* no txn in flight */
1964 if (cpuc
->txn_flags
& ~PERF_PMU_TXN_ADD
) {
1965 cpuc
->txn_flags
= 0;
1971 if (!x86_pmu_initialized())
1974 ret
= x86_pmu
.schedule_events(cpuc
, n
, assign
);
1979 * copy new assignment, now we know it is possible
1980 * will be used by hw_perf_enable()
1982 memcpy(cpuc
->assign
, assign
, n
*sizeof(int));
1984 cpuc
->txn_flags
= 0;
1985 perf_pmu_enable(pmu
);
1989 * a fake_cpuc is used to validate event groups. Due to
1990 * the extra reg logic, we need to also allocate a fake
1991 * per_core and per_cpu structure. Otherwise, group events
1992 * using extra reg may conflict without the kernel being
1993 * able to catch this when the last event gets added to
1996 static void free_fake_cpuc(struct cpu_hw_events
*cpuc
)
1998 intel_cpuc_finish(cpuc
);
2002 static struct cpu_hw_events
*allocate_fake_cpuc(void)
2004 struct cpu_hw_events
*cpuc
;
2005 int cpu
= raw_smp_processor_id();
2007 cpuc
= kzalloc(sizeof(*cpuc
), GFP_KERNEL
);
2009 return ERR_PTR(-ENOMEM
);
2012 if (intel_cpuc_prepare(cpuc
, cpu
))
2017 free_fake_cpuc(cpuc
);
2018 return ERR_PTR(-ENOMEM
);
2022 * validate that we can schedule this event
2024 static int validate_event(struct perf_event
*event
)
2026 struct cpu_hw_events
*fake_cpuc
;
2027 struct event_constraint
*c
;
2030 fake_cpuc
= allocate_fake_cpuc();
2031 if (IS_ERR(fake_cpuc
))
2032 return PTR_ERR(fake_cpuc
);
2034 c
= x86_pmu
.get_event_constraints(fake_cpuc
, -1, event
);
2036 if (!c
|| !c
->weight
)
2039 if (x86_pmu
.put_event_constraints
)
2040 x86_pmu
.put_event_constraints(fake_cpuc
, event
);
2042 free_fake_cpuc(fake_cpuc
);
2048 * validate a single event group
2050 * validation include:
2051 * - check events are compatible which each other
2052 * - events do not compete for the same counter
2053 * - number of events <= number of counters
2055 * validation ensures the group can be loaded onto the
2056 * PMU if it was the only group available.
2058 static int validate_group(struct perf_event
*event
)
2060 struct perf_event
*leader
= event
->group_leader
;
2061 struct cpu_hw_events
*fake_cpuc
;
2062 int ret
= -EINVAL
, n
;
2064 fake_cpuc
= allocate_fake_cpuc();
2065 if (IS_ERR(fake_cpuc
))
2066 return PTR_ERR(fake_cpuc
);
2068 * the event is not yet connected with its
2069 * siblings therefore we must first collect
2070 * existing siblings, then add the new event
2071 * before we can simulate the scheduling
2073 n
= collect_events(fake_cpuc
, leader
, true);
2077 fake_cpuc
->n_events
= n
;
2078 n
= collect_events(fake_cpuc
, event
, false);
2082 fake_cpuc
->n_events
= n
;
2084 ret
= x86_pmu
.schedule_events(fake_cpuc
, n
, NULL
);
2087 free_fake_cpuc(fake_cpuc
);
2091 static int x86_pmu_event_init(struct perf_event
*event
)
2096 switch (event
->attr
.type
) {
2098 case PERF_TYPE_HARDWARE
:
2099 case PERF_TYPE_HW_CACHE
:
2106 err
= __x86_pmu_event_init(event
);
2109 * we temporarily connect event to its pmu
2110 * such that validate_group() can classify
2111 * it as an x86 event using is_x86_event()
2116 if (event
->group_leader
!= event
)
2117 err
= validate_group(event
);
2119 err
= validate_event(event
);
2125 event
->destroy(event
);
2128 if (READ_ONCE(x86_pmu
.attr_rdpmc
) &&
2129 !(event
->hw
.flags
& PERF_X86_EVENT_LARGE_PEBS
))
2130 event
->hw
.flags
|= PERF_X86_EVENT_RDPMC_ALLOWED
;
2135 static void refresh_pce(void *ignored
)
2137 load_mm_cr4(this_cpu_read(cpu_tlbstate
.loaded_mm
));
2140 static void x86_pmu_event_mapped(struct perf_event
*event
, struct mm_struct
*mm
)
2142 if (!(event
->hw
.flags
& PERF_X86_EVENT_RDPMC_ALLOWED
))
2146 * This function relies on not being called concurrently in two
2147 * tasks in the same mm. Otherwise one task could observe
2148 * perf_rdpmc_allowed > 1 and return all the way back to
2149 * userspace with CR4.PCE clear while another task is still
2150 * doing on_each_cpu_mask() to propagate CR4.PCE.
2152 * For now, this can't happen because all callers hold mmap_sem
2153 * for write. If this changes, we'll need a different solution.
2155 lockdep_assert_held_exclusive(&mm
->mmap_sem
);
2157 if (atomic_inc_return(&mm
->context
.perf_rdpmc_allowed
) == 1)
2158 on_each_cpu_mask(mm_cpumask(mm
), refresh_pce
, NULL
, 1);
2161 static void x86_pmu_event_unmapped(struct perf_event
*event
, struct mm_struct
*mm
)
2164 if (!(event
->hw
.flags
& PERF_X86_EVENT_RDPMC_ALLOWED
))
2167 if (atomic_dec_and_test(&mm
->context
.perf_rdpmc_allowed
))
2168 on_each_cpu_mask(mm_cpumask(mm
), refresh_pce
, NULL
, 1);
2171 static int x86_pmu_event_idx(struct perf_event
*event
)
2173 int idx
= event
->hw
.idx
;
2175 if (!(event
->hw
.flags
& PERF_X86_EVENT_RDPMC_ALLOWED
))
2178 if (x86_pmu
.num_counters_fixed
&& idx
>= INTEL_PMC_IDX_FIXED
) {
2179 idx
-= INTEL_PMC_IDX_FIXED
;
2186 static ssize_t
get_attr_rdpmc(struct device
*cdev
,
2187 struct device_attribute
*attr
,
2190 return snprintf(buf
, 40, "%d\n", x86_pmu
.attr_rdpmc
);
2193 static ssize_t
set_attr_rdpmc(struct device
*cdev
,
2194 struct device_attribute
*attr
,
2195 const char *buf
, size_t count
)
2200 ret
= kstrtoul(buf
, 0, &val
);
2207 if (x86_pmu
.attr_rdpmc_broken
)
2210 if ((val
== 2) != (x86_pmu
.attr_rdpmc
== 2)) {
2212 * Changing into or out of always available, aka
2213 * perf-event-bypassing mode. This path is extremely slow,
2214 * but only root can trigger it, so it's okay.
2217 static_branch_inc(&rdpmc_always_available_key
);
2219 static_branch_dec(&rdpmc_always_available_key
);
2220 on_each_cpu(refresh_pce
, NULL
, 1);
2223 x86_pmu
.attr_rdpmc
= val
;
2228 static DEVICE_ATTR(rdpmc
, S_IRUSR
| S_IWUSR
, get_attr_rdpmc
, set_attr_rdpmc
);
2230 static struct attribute
*x86_pmu_attrs
[] = {
2231 &dev_attr_rdpmc
.attr
,
2235 static struct attribute_group x86_pmu_attr_group __ro_after_init
= {
2236 .attrs
= x86_pmu_attrs
,
2239 static ssize_t
max_precise_show(struct device
*cdev
,
2240 struct device_attribute
*attr
,
2243 return snprintf(buf
, PAGE_SIZE
, "%d\n", x86_pmu_max_precise());
2246 static DEVICE_ATTR_RO(max_precise
);
2248 static struct attribute
*x86_pmu_caps_attrs
[] = {
2249 &dev_attr_max_precise
.attr
,
2253 static struct attribute_group x86_pmu_caps_group __ro_after_init
= {
2255 .attrs
= x86_pmu_caps_attrs
,
2258 static const struct attribute_group
*x86_pmu_attr_groups
[] = {
2259 &x86_pmu_attr_group
,
2260 &x86_pmu_format_group
,
2261 &x86_pmu_events_group
,
2262 &x86_pmu_caps_group
,
2266 static void x86_pmu_sched_task(struct perf_event_context
*ctx
, bool sched_in
)
2268 if (x86_pmu
.sched_task
)
2269 x86_pmu
.sched_task(ctx
, sched_in
);
2272 void perf_check_microcode(void)
2274 if (x86_pmu
.check_microcode
)
2275 x86_pmu
.check_microcode();
2278 static int x86_pmu_check_period(struct perf_event
*event
, u64 value
)
2280 if (x86_pmu
.check_period
&& x86_pmu
.check_period(event
, value
))
2283 if (value
&& x86_pmu
.limit_period
) {
2284 if (x86_pmu
.limit_period(event
, value
) > value
)
2291 static struct pmu pmu
= {
2292 .pmu_enable
= x86_pmu_enable
,
2293 .pmu_disable
= x86_pmu_disable
,
2295 .attr_groups
= x86_pmu_attr_groups
,
2297 .event_init
= x86_pmu_event_init
,
2299 .event_mapped
= x86_pmu_event_mapped
,
2300 .event_unmapped
= x86_pmu_event_unmapped
,
2304 .start
= x86_pmu_start
,
2305 .stop
= x86_pmu_stop
,
2306 .read
= x86_pmu_read
,
2308 .start_txn
= x86_pmu_start_txn
,
2309 .cancel_txn
= x86_pmu_cancel_txn
,
2310 .commit_txn
= x86_pmu_commit_txn
,
2312 .event_idx
= x86_pmu_event_idx
,
2313 .sched_task
= x86_pmu_sched_task
,
2314 .task_ctx_size
= sizeof(struct x86_perf_task_context
),
2315 .check_period
= x86_pmu_check_period
,
2318 void arch_perf_update_userpage(struct perf_event
*event
,
2319 struct perf_event_mmap_page
*userpg
, u64 now
)
2321 struct cyc2ns_data data
;
2324 userpg
->cap_user_time
= 0;
2325 userpg
->cap_user_time_zero
= 0;
2326 userpg
->cap_user_rdpmc
=
2327 !!(event
->hw
.flags
& PERF_X86_EVENT_RDPMC_ALLOWED
);
2328 userpg
->pmc_width
= x86_pmu
.cntval_bits
;
2330 if (!using_native_sched_clock() || !sched_clock_stable())
2333 cyc2ns_read_begin(&data
);
2335 offset
= data
.cyc2ns_offset
+ __sched_clock_offset
;
2338 * Internal timekeeping for enabled/running/stopped times
2339 * is always in the local_clock domain.
2341 userpg
->cap_user_time
= 1;
2342 userpg
->time_mult
= data
.cyc2ns_mul
;
2343 userpg
->time_shift
= data
.cyc2ns_shift
;
2344 userpg
->time_offset
= offset
- now
;
2347 * cap_user_time_zero doesn't make sense when we're using a different
2348 * time base for the records.
2350 if (!event
->attr
.use_clockid
) {
2351 userpg
->cap_user_time_zero
= 1;
2352 userpg
->time_zero
= offset
;
2359 perf_callchain_kernel(struct perf_callchain_entry_ctx
*entry
, struct pt_regs
*regs
)
2361 struct unwind_state state
;
2364 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
2365 /* TODO: We don't support guest os callchain now */
2369 if (perf_callchain_store(entry
, regs
->ip
))
2372 for (unwind_start(&state
, current
, regs
, NULL
); !unwind_done(&state
);
2373 unwind_next_frame(&state
)) {
2374 addr
= unwind_get_return_address(&state
);
2375 if (!addr
|| perf_callchain_store(entry
, addr
))
2381 valid_user_frame(const void __user
*fp
, unsigned long size
)
2383 return (__range_not_ok(fp
, size
, TASK_SIZE
) == 0);
2386 static unsigned long get_segment_base(unsigned int segment
)
2388 struct desc_struct
*desc
;
2389 unsigned int idx
= segment
>> 3;
2391 if ((segment
& SEGMENT_TI_MASK
) == SEGMENT_LDT
) {
2392 #ifdef CONFIG_MODIFY_LDT_SYSCALL
2393 struct ldt_struct
*ldt
;
2395 /* IRQs are off, so this synchronizes with smp_store_release */
2396 ldt
= READ_ONCE(current
->active_mm
->context
.ldt
);
2397 if (!ldt
|| idx
>= ldt
->nr_entries
)
2400 desc
= &ldt
->entries
[idx
];
2405 if (idx
>= GDT_ENTRIES
)
2408 desc
= raw_cpu_ptr(gdt_page
.gdt
) + idx
;
2411 return get_desc_base(desc
);
2414 #ifdef CONFIG_IA32_EMULATION
2416 #include <linux/compat.h>
2419 perf_callchain_user32(struct pt_regs
*regs
, struct perf_callchain_entry_ctx
*entry
)
2421 /* 32-bit process in 64-bit kernel. */
2422 unsigned long ss_base
, cs_base
;
2423 struct stack_frame_ia32 frame
;
2424 const void __user
*fp
;
2426 if (!test_thread_flag(TIF_IA32
))
2429 cs_base
= get_segment_base(regs
->cs
);
2430 ss_base
= get_segment_base(regs
->ss
);
2432 fp
= compat_ptr(ss_base
+ regs
->bp
);
2433 pagefault_disable();
2434 while (entry
->nr
< entry
->max_stack
) {
2435 unsigned long bytes
;
2436 frame
.next_frame
= 0;
2437 frame
.return_address
= 0;
2439 if (!valid_user_frame(fp
, sizeof(frame
)))
2442 bytes
= __copy_from_user_nmi(&frame
.next_frame
, fp
, 4);
2445 bytes
= __copy_from_user_nmi(&frame
.return_address
, fp
+4, 4);
2449 perf_callchain_store(entry
, cs_base
+ frame
.return_address
);
2450 fp
= compat_ptr(ss_base
+ frame
.next_frame
);
2457 perf_callchain_user32(struct pt_regs
*regs
, struct perf_callchain_entry_ctx
*entry
)
2464 perf_callchain_user(struct perf_callchain_entry_ctx
*entry
, struct pt_regs
*regs
)
2466 struct stack_frame frame
;
2467 const unsigned long __user
*fp
;
2469 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
2470 /* TODO: We don't support guest os callchain now */
2475 * We don't know what to do with VM86 stacks.. ignore them for now.
2477 if (regs
->flags
& (X86_VM_MASK
| PERF_EFLAGS_VM
))
2480 fp
= (unsigned long __user
*)regs
->bp
;
2482 perf_callchain_store(entry
, regs
->ip
);
2484 if (!nmi_uaccess_okay())
2487 if (perf_callchain_user32(regs
, entry
))
2490 pagefault_disable();
2491 while (entry
->nr
< entry
->max_stack
) {
2492 unsigned long bytes
;
2494 frame
.next_frame
= NULL
;
2495 frame
.return_address
= 0;
2497 if (!valid_user_frame(fp
, sizeof(frame
)))
2500 bytes
= __copy_from_user_nmi(&frame
.next_frame
, fp
, sizeof(*fp
));
2503 bytes
= __copy_from_user_nmi(&frame
.return_address
, fp
+ 1, sizeof(*fp
));
2507 perf_callchain_store(entry
, frame
.return_address
);
2508 fp
= (void __user
*)frame
.next_frame
;
2514 * Deal with code segment offsets for the various execution modes:
2516 * VM86 - the good olde 16 bit days, where the linear address is
2517 * 20 bits and we use regs->ip + 0x10 * regs->cs.
2519 * IA32 - Where we need to look at GDT/LDT segment descriptor tables
2520 * to figure out what the 32bit base address is.
2522 * X32 - has TIF_X32 set, but is running in x86_64
2524 * X86_64 - CS,DS,SS,ES are all zero based.
2526 static unsigned long code_segment_base(struct pt_regs
*regs
)
2529 * For IA32 we look at the GDT/LDT segment base to convert the
2530 * effective IP to a linear address.
2533 #ifdef CONFIG_X86_32
2535 * If we are in VM86 mode, add the segment offset to convert to a
2538 if (regs
->flags
& X86_VM_MASK
)
2539 return 0x10 * regs
->cs
;
2541 if (user_mode(regs
) && regs
->cs
!= __USER_CS
)
2542 return get_segment_base(regs
->cs
);
2544 if (user_mode(regs
) && !user_64bit_mode(regs
) &&
2545 regs
->cs
!= __USER32_CS
)
2546 return get_segment_base(regs
->cs
);
2551 unsigned long perf_instruction_pointer(struct pt_regs
*regs
)
2553 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest())
2554 return perf_guest_cbs
->get_guest_ip();
2556 return regs
->ip
+ code_segment_base(regs
);
2559 unsigned long perf_misc_flags(struct pt_regs
*regs
)
2563 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
2564 if (perf_guest_cbs
->is_user_mode())
2565 misc
|= PERF_RECORD_MISC_GUEST_USER
;
2567 misc
|= PERF_RECORD_MISC_GUEST_KERNEL
;
2569 if (user_mode(regs
))
2570 misc
|= PERF_RECORD_MISC_USER
;
2572 misc
|= PERF_RECORD_MISC_KERNEL
;
2575 if (regs
->flags
& PERF_EFLAGS_EXACT
)
2576 misc
|= PERF_RECORD_MISC_EXACT_IP
;
2581 void perf_get_x86_pmu_capability(struct x86_pmu_capability
*cap
)
2583 cap
->version
= x86_pmu
.version
;
2584 cap
->num_counters_gp
= x86_pmu
.num_counters
;
2585 cap
->num_counters_fixed
= x86_pmu
.num_counters_fixed
;
2586 cap
->bit_width_gp
= x86_pmu
.cntval_bits
;
2587 cap
->bit_width_fixed
= x86_pmu
.cntval_bits
;
2588 cap
->events_mask
= (unsigned int)x86_pmu
.events_maskl
;
2589 cap
->events_mask_len
= x86_pmu
.events_mask_len
;
2591 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability
);