1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/bitops.h>
3 #include <linux/types.h>
4 #include <linux/slab.h>
6 #include <asm/cpu_entry_area.h>
7 #include <asm/perf_event.h>
8 #include <asm/tlbflush.h>
11 #include "../perf_event.h"
13 /* Waste a full page so it can be mapped into the cpu_entry_area */
14 DEFINE_PER_CPU_PAGE_ALIGNED(struct debug_store
, cpu_debug_store
);
16 /* The size of a BTS record in bytes: */
17 #define BTS_RECORD_SIZE 24
19 #define PEBS_FIXUP_SIZE PAGE_SIZE
22 * pebs_record_32 for p4 and core not supported
24 struct pebs_record_32 {
32 union intel_x86_pebs_dse
{
35 unsigned int ld_dse
:4;
36 unsigned int ld_stlb_miss
:1;
37 unsigned int ld_locked
:1;
38 unsigned int ld_reserved
:26;
41 unsigned int st_l1d_hit
:1;
42 unsigned int st_reserved1
:3;
43 unsigned int st_stlb_miss
:1;
44 unsigned int st_locked
:1;
45 unsigned int st_reserved2
:26;
51 * Map PEBS Load Latency Data Source encodings to generic
52 * memory data source information
54 #define P(a, b) PERF_MEM_S(a, b)
55 #define OP_LH (P(OP, LOAD) | P(LVL, HIT))
56 #define LEVEL(x) P(LVLNUM, x)
57 #define REM P(REMOTE, REMOTE)
58 #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS))
60 /* Version for Sandy Bridge and later */
61 static u64 pebs_data_source
[] = {
62 P(OP
, LOAD
) | P(LVL
, MISS
) | LEVEL(L3
) | P(SNOOP
, NA
),/* 0x00:ukn L3 */
63 OP_LH
| P(LVL
, L1
) | LEVEL(L1
) | P(SNOOP
, NONE
), /* 0x01: L1 local */
64 OP_LH
| P(LVL
, LFB
) | LEVEL(LFB
) | P(SNOOP
, NONE
), /* 0x02: LFB hit */
65 OP_LH
| P(LVL
, L2
) | LEVEL(L2
) | P(SNOOP
, NONE
), /* 0x03: L2 hit */
66 OP_LH
| P(LVL
, L3
) | LEVEL(L3
) | P(SNOOP
, NONE
), /* 0x04: L3 hit */
67 OP_LH
| P(LVL
, L3
) | LEVEL(L3
) | P(SNOOP
, MISS
), /* 0x05: L3 hit, snoop miss */
68 OP_LH
| P(LVL
, L3
) | LEVEL(L3
) | P(SNOOP
, HIT
), /* 0x06: L3 hit, snoop hit */
69 OP_LH
| P(LVL
, L3
) | LEVEL(L3
) | P(SNOOP
, HITM
), /* 0x07: L3 hit, snoop hitm */
70 OP_LH
| P(LVL
, REM_CCE1
) | REM
| LEVEL(L3
) | P(SNOOP
, HIT
), /* 0x08: L3 miss snoop hit */
71 OP_LH
| P(LVL
, REM_CCE1
) | REM
| LEVEL(L3
) | P(SNOOP
, HITM
), /* 0x09: L3 miss snoop hitm*/
72 OP_LH
| P(LVL
, LOC_RAM
) | LEVEL(RAM
) | P(SNOOP
, HIT
), /* 0x0a: L3 miss, shared */
73 OP_LH
| P(LVL
, REM_RAM1
) | REM
| LEVEL(L3
) | P(SNOOP
, HIT
), /* 0x0b: L3 miss, shared */
74 OP_LH
| P(LVL
, LOC_RAM
) | LEVEL(RAM
) | SNOOP_NONE_MISS
, /* 0x0c: L3 miss, excl */
75 OP_LH
| P(LVL
, REM_RAM1
) | LEVEL(RAM
) | REM
| SNOOP_NONE_MISS
, /* 0x0d: L3 miss, excl */
76 OP_LH
| P(LVL
, IO
) | LEVEL(NA
) | P(SNOOP
, NONE
), /* 0x0e: I/O */
77 OP_LH
| P(LVL
, UNC
) | LEVEL(NA
) | P(SNOOP
, NONE
), /* 0x0f: uncached */
80 /* Patch up minor differences in the bits */
81 void __init
intel_pmu_pebs_data_source_nhm(void)
83 pebs_data_source
[0x05] = OP_LH
| P(LVL
, L3
) | LEVEL(L3
) | P(SNOOP
, HIT
);
84 pebs_data_source
[0x06] = OP_LH
| P(LVL
, L3
) | LEVEL(L3
) | P(SNOOP
, HITM
);
85 pebs_data_source
[0x07] = OP_LH
| P(LVL
, L3
) | LEVEL(L3
) | P(SNOOP
, HITM
);
88 void __init
intel_pmu_pebs_data_source_skl(bool pmem
)
90 u64 pmem_or_l4
= pmem
? LEVEL(PMEM
) : LEVEL(L4
);
92 pebs_data_source
[0x08] = OP_LH
| pmem_or_l4
| P(SNOOP
, HIT
);
93 pebs_data_source
[0x09] = OP_LH
| pmem_or_l4
| REM
| P(SNOOP
, HIT
);
94 pebs_data_source
[0x0b] = OP_LH
| LEVEL(RAM
) | REM
| P(SNOOP
, NONE
);
95 pebs_data_source
[0x0c] = OP_LH
| LEVEL(ANY_CACHE
) | REM
| P(SNOOPX
, FWD
);
96 pebs_data_source
[0x0d] = OP_LH
| LEVEL(ANY_CACHE
) | REM
| P(SNOOP
, HITM
);
99 static u64
precise_store_data(u64 status
)
101 union intel_x86_pebs_dse dse
;
102 u64 val
= P(OP
, STORE
) | P(SNOOP
, NA
) | P(LVL
, L1
) | P(TLB
, L2
);
108 * 1 = stored missed 2nd level TLB
110 * so it either hit the walker or the OS
111 * otherwise hit 2nd level TLB
113 if (dse
.st_stlb_miss
)
119 * bit 0: hit L1 data cache
120 * if not set, then all we know is that
129 * bit 5: Locked prefix
132 val
|= P(LOCK
, LOCKED
);
137 static u64
precise_datala_hsw(struct perf_event
*event
, u64 status
)
139 union perf_mem_data_src dse
;
141 dse
.val
= PERF_MEM_NA
;
143 if (event
->hw
.flags
& PERF_X86_EVENT_PEBS_ST_HSW
)
144 dse
.mem_op
= PERF_MEM_OP_STORE
;
145 else if (event
->hw
.flags
& PERF_X86_EVENT_PEBS_LD_HSW
)
146 dse
.mem_op
= PERF_MEM_OP_LOAD
;
149 * L1 info only valid for following events:
151 * MEM_UOPS_RETIRED.STLB_MISS_STORES
152 * MEM_UOPS_RETIRED.LOCK_STORES
153 * MEM_UOPS_RETIRED.SPLIT_STORES
154 * MEM_UOPS_RETIRED.ALL_STORES
156 if (event
->hw
.flags
& PERF_X86_EVENT_PEBS_ST_HSW
) {
158 dse
.mem_lvl
= PERF_MEM_LVL_L1
| PERF_MEM_LVL_HIT
;
160 dse
.mem_lvl
= PERF_MEM_LVL_L1
| PERF_MEM_LVL_MISS
;
165 static u64
load_latency_data(u64 status
)
167 union intel_x86_pebs_dse dse
;
173 * use the mapping table for bit 0-3
175 val
= pebs_data_source
[dse
.ld_dse
];
178 * Nehalem models do not support TLB, Lock infos
180 if (x86_pmu
.pebs_no_tlb
) {
181 val
|= P(TLB
, NA
) | P(LOCK
, NA
);
186 * 0 = did not miss 2nd level TLB
187 * 1 = missed 2nd level TLB
189 if (dse
.ld_stlb_miss
)
190 val
|= P(TLB
, MISS
) | P(TLB
, L2
);
192 val
|= P(TLB
, HIT
) | P(TLB
, L1
) | P(TLB
, L2
);
195 * bit 5: locked prefix
198 val
|= P(LOCK
, LOCKED
);
203 struct pebs_record_core
{
207 u64 r8
, r9
, r10
, r11
;
208 u64 r12
, r13
, r14
, r15
;
211 struct pebs_record_nhm
{
215 u64 r8
, r9
, r10
, r11
;
216 u64 r12
, r13
, r14
, r15
;
217 u64 status
, dla
, dse
, lat
;
221 * Same as pebs_record_nhm, with two additional fields.
223 struct pebs_record_hsw
{
227 u64 r8
, r9
, r10
, r11
;
228 u64 r12
, r13
, r14
, r15
;
229 u64 status
, dla
, dse
, lat
;
230 u64 real_ip
, tsx_tuning
;
233 union hsw_tsx_tuning
{
235 u32 cycles_last_block
: 32,
238 instruction_abort
: 1,
239 non_instruction_abort
: 1,
248 #define PEBS_HSW_TSX_FLAGS 0xff00000000ULL
250 /* Same as HSW, plus TSC */
252 struct pebs_record_skl
{
256 u64 r8
, r9
, r10
, r11
;
257 u64 r12
, r13
, r14
, r15
;
258 u64 status
, dla
, dse
, lat
;
259 u64 real_ip
, tsx_tuning
;
263 void init_debug_store_on_cpu(int cpu
)
265 struct debug_store
*ds
= per_cpu(cpu_hw_events
, cpu
).ds
;
270 wrmsr_on_cpu(cpu
, MSR_IA32_DS_AREA
,
271 (u32
)((u64
)(unsigned long)ds
),
272 (u32
)((u64
)(unsigned long)ds
>> 32));
275 void fini_debug_store_on_cpu(int cpu
)
277 if (!per_cpu(cpu_hw_events
, cpu
).ds
)
280 wrmsr_on_cpu(cpu
, MSR_IA32_DS_AREA
, 0, 0);
283 static DEFINE_PER_CPU(void *, insn_buffer
);
285 static void ds_update_cea(void *cea
, void *addr
, size_t size
, pgprot_t prot
)
287 unsigned long start
= (unsigned long)cea
;
291 pa
= virt_to_phys(addr
);
294 for (; msz
< size
; msz
+= PAGE_SIZE
, pa
+= PAGE_SIZE
, cea
+= PAGE_SIZE
)
295 cea_set_pte(cea
, pa
, prot
);
298 * This is a cross-CPU update of the cpu_entry_area, we must shoot down
299 * all TLB entries for it.
301 flush_tlb_kernel_range(start
, start
+ size
);
305 static void ds_clear_cea(void *cea
, size_t size
)
307 unsigned long start
= (unsigned long)cea
;
311 for (; msz
< size
; msz
+= PAGE_SIZE
, cea
+= PAGE_SIZE
)
312 cea_set_pte(cea
, 0, PAGE_NONE
);
314 flush_tlb_kernel_range(start
, start
+ size
);
318 static void *dsalloc_pages(size_t size
, gfp_t flags
, int cpu
)
320 unsigned int order
= get_order(size
);
321 int node
= cpu_to_node(cpu
);
324 page
= __alloc_pages_node(node
, flags
| __GFP_ZERO
, order
);
325 return page
? page_address(page
) : NULL
;
328 static void dsfree_pages(const void *buffer
, size_t size
)
331 free_pages((unsigned long)buffer
, get_order(size
));
334 static int alloc_pebs_buffer(int cpu
)
336 struct cpu_hw_events
*hwev
= per_cpu_ptr(&cpu_hw_events
, cpu
);
337 struct debug_store
*ds
= hwev
->ds
;
338 size_t bsiz
= x86_pmu
.pebs_buffer_size
;
339 int max
, node
= cpu_to_node(cpu
);
340 void *buffer
, *ibuffer
, *cea
;
345 buffer
= dsalloc_pages(bsiz
, GFP_KERNEL
, cpu
);
346 if (unlikely(!buffer
))
350 * HSW+ already provides us the eventing ip; no need to allocate this
353 if (x86_pmu
.intel_cap
.pebs_format
< 2) {
354 ibuffer
= kzalloc_node(PEBS_FIXUP_SIZE
, GFP_KERNEL
, node
);
356 dsfree_pages(buffer
, bsiz
);
359 per_cpu(insn_buffer
, cpu
) = ibuffer
;
361 hwev
->ds_pebs_vaddr
= buffer
;
362 /* Update the cpu entry area mapping */
363 cea
= &get_cpu_entry_area(cpu
)->cpu_debug_buffers
.pebs_buffer
;
364 ds
->pebs_buffer_base
= (unsigned long) cea
;
365 ds_update_cea(cea
, buffer
, bsiz
, PAGE_KERNEL
);
366 ds
->pebs_index
= ds
->pebs_buffer_base
;
367 max
= x86_pmu
.pebs_record_size
* (bsiz
/ x86_pmu
.pebs_record_size
);
368 ds
->pebs_absolute_maximum
= ds
->pebs_buffer_base
+ max
;
372 static void release_pebs_buffer(int cpu
)
374 struct cpu_hw_events
*hwev
= per_cpu_ptr(&cpu_hw_events
, cpu
);
375 struct debug_store
*ds
= hwev
->ds
;
378 if (!ds
|| !x86_pmu
.pebs
)
381 kfree(per_cpu(insn_buffer
, cpu
));
382 per_cpu(insn_buffer
, cpu
) = NULL
;
384 /* Clear the fixmap */
385 cea
= &get_cpu_entry_area(cpu
)->cpu_debug_buffers
.pebs_buffer
;
386 ds_clear_cea(cea
, x86_pmu
.pebs_buffer_size
);
387 ds
->pebs_buffer_base
= 0;
388 dsfree_pages(hwev
->ds_pebs_vaddr
, x86_pmu
.pebs_buffer_size
);
389 hwev
->ds_pebs_vaddr
= NULL
;
392 static int alloc_bts_buffer(int cpu
)
394 struct cpu_hw_events
*hwev
= per_cpu_ptr(&cpu_hw_events
, cpu
);
395 struct debug_store
*ds
= hwev
->ds
;
402 buffer
= dsalloc_pages(BTS_BUFFER_SIZE
, GFP_KERNEL
| __GFP_NOWARN
, cpu
);
403 if (unlikely(!buffer
)) {
404 WARN_ONCE(1, "%s: BTS buffer allocation failure\n", __func__
);
407 hwev
->ds_bts_vaddr
= buffer
;
408 /* Update the fixmap */
409 cea
= &get_cpu_entry_area(cpu
)->cpu_debug_buffers
.bts_buffer
;
410 ds
->bts_buffer_base
= (unsigned long) cea
;
411 ds_update_cea(cea
, buffer
, BTS_BUFFER_SIZE
, PAGE_KERNEL
);
412 ds
->bts_index
= ds
->bts_buffer_base
;
413 max
= BTS_RECORD_SIZE
* (BTS_BUFFER_SIZE
/ BTS_RECORD_SIZE
);
414 ds
->bts_absolute_maximum
= ds
->bts_buffer_base
+ max
;
415 ds
->bts_interrupt_threshold
= ds
->bts_absolute_maximum
- (max
/ 16);
419 static void release_bts_buffer(int cpu
)
421 struct cpu_hw_events
*hwev
= per_cpu_ptr(&cpu_hw_events
, cpu
);
422 struct debug_store
*ds
= hwev
->ds
;
425 if (!ds
|| !x86_pmu
.bts
)
428 /* Clear the fixmap */
429 cea
= &get_cpu_entry_area(cpu
)->cpu_debug_buffers
.bts_buffer
;
430 ds_clear_cea(cea
, BTS_BUFFER_SIZE
);
431 ds
->bts_buffer_base
= 0;
432 dsfree_pages(hwev
->ds_bts_vaddr
, BTS_BUFFER_SIZE
);
433 hwev
->ds_bts_vaddr
= NULL
;
436 static int alloc_ds_buffer(int cpu
)
438 struct debug_store
*ds
= &get_cpu_entry_area(cpu
)->cpu_debug_store
;
440 memset(ds
, 0, sizeof(*ds
));
441 per_cpu(cpu_hw_events
, cpu
).ds
= ds
;
445 static void release_ds_buffer(int cpu
)
447 per_cpu(cpu_hw_events
, cpu
).ds
= NULL
;
450 void release_ds_buffers(void)
454 if (!x86_pmu
.bts
&& !x86_pmu
.pebs
)
458 for_each_online_cpu(cpu
)
459 fini_debug_store_on_cpu(cpu
);
461 for_each_possible_cpu(cpu
) {
462 release_pebs_buffer(cpu
);
463 release_bts_buffer(cpu
);
464 release_ds_buffer(cpu
);
469 void reserve_ds_buffers(void)
471 int bts_err
= 0, pebs_err
= 0;
474 x86_pmu
.bts_active
= 0;
475 x86_pmu
.pebs_active
= 0;
477 if (!x86_pmu
.bts
&& !x86_pmu
.pebs
)
488 for_each_possible_cpu(cpu
) {
489 if (alloc_ds_buffer(cpu
)) {
494 if (!bts_err
&& alloc_bts_buffer(cpu
))
497 if (!pebs_err
&& alloc_pebs_buffer(cpu
))
500 if (bts_err
&& pebs_err
)
505 for_each_possible_cpu(cpu
)
506 release_bts_buffer(cpu
);
510 for_each_possible_cpu(cpu
)
511 release_pebs_buffer(cpu
);
514 if (bts_err
&& pebs_err
) {
515 for_each_possible_cpu(cpu
)
516 release_ds_buffer(cpu
);
518 if (x86_pmu
.bts
&& !bts_err
)
519 x86_pmu
.bts_active
= 1;
521 if (x86_pmu
.pebs
&& !pebs_err
)
522 x86_pmu
.pebs_active
= 1;
524 for_each_online_cpu(cpu
)
525 init_debug_store_on_cpu(cpu
);
535 struct event_constraint bts_constraint
=
536 EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS
, 0);
538 void intel_pmu_enable_bts(u64 config
)
540 unsigned long debugctlmsr
;
542 debugctlmsr
= get_debugctlmsr();
544 debugctlmsr
|= DEBUGCTLMSR_TR
;
545 debugctlmsr
|= DEBUGCTLMSR_BTS
;
546 if (config
& ARCH_PERFMON_EVENTSEL_INT
)
547 debugctlmsr
|= DEBUGCTLMSR_BTINT
;
549 if (!(config
& ARCH_PERFMON_EVENTSEL_OS
))
550 debugctlmsr
|= DEBUGCTLMSR_BTS_OFF_OS
;
552 if (!(config
& ARCH_PERFMON_EVENTSEL_USR
))
553 debugctlmsr
|= DEBUGCTLMSR_BTS_OFF_USR
;
555 update_debugctlmsr(debugctlmsr
);
558 void intel_pmu_disable_bts(void)
560 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
561 unsigned long debugctlmsr
;
566 debugctlmsr
= get_debugctlmsr();
569 ~(DEBUGCTLMSR_TR
| DEBUGCTLMSR_BTS
| DEBUGCTLMSR_BTINT
|
570 DEBUGCTLMSR_BTS_OFF_OS
| DEBUGCTLMSR_BTS_OFF_USR
);
572 update_debugctlmsr(debugctlmsr
);
575 int intel_pmu_drain_bts_buffer(void)
577 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
578 struct debug_store
*ds
= cpuc
->ds
;
584 struct perf_event
*event
= cpuc
->events
[INTEL_PMC_IDX_FIXED_BTS
];
585 struct bts_record
*at
, *base
, *top
;
586 struct perf_output_handle handle
;
587 struct perf_event_header header
;
588 struct perf_sample_data data
;
589 unsigned long skip
= 0;
595 if (!x86_pmu
.bts_active
)
598 base
= (struct bts_record
*)(unsigned long)ds
->bts_buffer_base
;
599 top
= (struct bts_record
*)(unsigned long)ds
->bts_index
;
604 memset(®s
, 0, sizeof(regs
));
606 ds
->bts_index
= ds
->bts_buffer_base
;
608 perf_sample_data_init(&data
, 0, event
->hw
.last_period
);
611 * BTS leaks kernel addresses in branches across the cpl boundary,
612 * such as traps or system calls, so unless the user is asking for
613 * kernel tracing (and right now it's not possible), we'd need to
614 * filter them out. But first we need to count how many of those we
615 * have in the current batch. This is an extra O(n) pass, however,
616 * it's much faster than the other one especially considering that
617 * n <= 2560 (BTS_BUFFER_SIZE / BTS_RECORD_SIZE * 15/16; see the
618 * alloc_bts_buffer()).
620 for (at
= base
; at
< top
; at
++) {
622 * Note that right now *this* BTS code only works if
623 * attr::exclude_kernel is set, but let's keep this extra
624 * check here in case that changes.
626 if (event
->attr
.exclude_kernel
&&
627 (kernel_ip(at
->from
) || kernel_ip(at
->to
)))
632 * Prepare a generic sample, i.e. fill in the invariant fields.
633 * We will overwrite the from and to address before we output
637 perf_prepare_sample(&header
, &data
, event
, ®s
);
639 if (perf_output_begin(&handle
, event
, header
.size
*
640 (top
- base
- skip
)))
643 for (at
= base
; at
< top
; at
++) {
644 /* Filter out any records that contain kernel addresses. */
645 if (event
->attr
.exclude_kernel
&&
646 (kernel_ip(at
->from
) || kernel_ip(at
->to
)))
652 perf_output_sample(&handle
, &header
, &data
, event
);
655 perf_output_end(&handle
);
657 /* There's new data available. */
658 event
->hw
.interrupts
++;
659 event
->pending_kill
= POLL_IN
;
665 static inline void intel_pmu_drain_pebs_buffer(void)
669 x86_pmu
.drain_pebs(®s
);
675 struct event_constraint intel_core2_pebs_event_constraints
[] = {
676 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
677 INTEL_FLAGS_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
678 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
679 INTEL_FLAGS_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
680 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
681 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
682 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01),
686 struct event_constraint intel_atom_pebs_event_constraints
[] = {
687 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
688 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
689 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
690 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
691 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01),
692 /* Allow all events as PEBS with no flags */
693 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
697 struct event_constraint intel_slm_pebs_event_constraints
[] = {
698 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
699 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x1),
700 /* Allow all events as PEBS with no flags */
701 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
705 struct event_constraint intel_glm_pebs_event_constraints
[] = {
706 /* Allow all events as PEBS with no flags */
707 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
711 struct event_constraint intel_glp_pebs_event_constraints
[] = {
712 /* Allow all events as PEBS with no flags */
713 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
717 struct event_constraint intel_nehalem_pebs_event_constraints
[] = {
718 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
719 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
720 INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
721 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INST_RETIRED.ANY */
722 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
723 INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
724 INTEL_FLAGS_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
725 INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
726 INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
727 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
728 INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
729 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
730 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
734 struct event_constraint intel_westmere_pebs_event_constraints
[] = {
735 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
736 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
737 INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
738 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INSTR_RETIRED.* */
739 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
740 INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
741 INTEL_FLAGS_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */
742 INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
743 INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
744 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
745 INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
746 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
747 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
751 struct event_constraint intel_snb_pebs_event_constraints
[] = {
752 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
753 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
754 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
755 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
756 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
757 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
758 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
759 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
760 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
761 /* Allow all events as PEBS with no flags */
762 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
766 struct event_constraint intel_ivb_pebs_event_constraints
[] = {
767 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
768 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
769 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
770 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
771 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
772 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
773 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2),
774 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
775 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
776 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
777 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
778 /* Allow all events as PEBS with no flags */
779 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
783 struct event_constraint intel_hsw_pebs_event_constraints
[] = {
784 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
785 INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */
786 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
787 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
788 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
789 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2),
790 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
791 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
792 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
793 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
794 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
795 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
796 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
797 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
798 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
799 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
800 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
801 /* Allow all events as PEBS with no flags */
802 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
806 struct event_constraint intel_bdw_pebs_event_constraints
[] = {
807 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
808 INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */
809 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
810 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
811 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
812 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2),
813 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
814 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
815 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
816 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
817 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
818 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
819 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
820 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
821 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
822 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
823 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
824 /* Allow all events as PEBS with no flags */
825 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
830 struct event_constraint intel_skl_pebs_event_constraints
[] = {
831 INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
832 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
833 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2),
834 /* INST_RETIRED.TOTAL_CYCLES_PS (inv=1, cmask=16) (cycles:p). */
835 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
836 INTEL_PLD_CONSTRAINT(0x1cd, 0xf), /* MEM_TRANS_RETIRED.* */
837 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */
838 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */
839 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */
840 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x22d0, 0xf), /* MEM_INST_RETIRED.LOCK_STORES */
841 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */
842 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */
843 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */
844 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */
845 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
846 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
847 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_L3_MISS_RETIRED.* */
848 /* Allow all events as PEBS with no flags */
849 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
853 struct event_constraint
*intel_pebs_constraints(struct perf_event
*event
)
855 struct event_constraint
*c
;
857 if (!event
->attr
.precise_ip
)
860 if (x86_pmu
.pebs_constraints
) {
861 for_each_event_constraint(c
, x86_pmu
.pebs_constraints
) {
862 if ((event
->hw
.config
& c
->cmask
) == c
->code
) {
863 event
->hw
.flags
|= c
->flags
;
869 return &emptyconstraint
;
873 * We need the sched_task callback even for per-cpu events when we use
874 * the large interrupt threshold, such that we can provide PID and TID
877 static inline bool pebs_needs_sched_cb(struct cpu_hw_events
*cpuc
)
879 return cpuc
->n_pebs
&& (cpuc
->n_pebs
== cpuc
->n_large_pebs
);
882 void intel_pmu_pebs_sched_task(struct perf_event_context
*ctx
, bool sched_in
)
884 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
886 if (!sched_in
&& pebs_needs_sched_cb(cpuc
))
887 intel_pmu_drain_pebs_buffer();
890 static inline void pebs_update_threshold(struct cpu_hw_events
*cpuc
)
892 struct debug_store
*ds
= cpuc
->ds
;
895 if (cpuc
->n_pebs
== cpuc
->n_large_pebs
) {
896 threshold
= ds
->pebs_absolute_maximum
-
897 x86_pmu
.max_pebs_events
* x86_pmu
.pebs_record_size
;
899 threshold
= ds
->pebs_buffer_base
+ x86_pmu
.pebs_record_size
;
902 ds
->pebs_interrupt_threshold
= threshold
;
906 pebs_update_state(bool needed_cb
, struct cpu_hw_events
*cpuc
, struct pmu
*pmu
)
909 * Make sure we get updated with the first PEBS
910 * event. It will trigger also during removal, but
911 * that does not hurt:
913 bool update
= cpuc
->n_pebs
== 1;
915 if (needed_cb
!= pebs_needs_sched_cb(cpuc
)) {
917 perf_sched_cb_inc(pmu
);
919 perf_sched_cb_dec(pmu
);
925 pebs_update_threshold(cpuc
);
928 void intel_pmu_pebs_add(struct perf_event
*event
)
930 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
931 struct hw_perf_event
*hwc
= &event
->hw
;
932 bool needed_cb
= pebs_needs_sched_cb(cpuc
);
935 if (hwc
->flags
& PERF_X86_EVENT_FREERUNNING
)
936 cpuc
->n_large_pebs
++;
938 pebs_update_state(needed_cb
, cpuc
, event
->ctx
->pmu
);
941 void intel_pmu_pebs_enable(struct perf_event
*event
)
943 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
944 struct hw_perf_event
*hwc
= &event
->hw
;
945 struct debug_store
*ds
= cpuc
->ds
;
947 hwc
->config
&= ~ARCH_PERFMON_EVENTSEL_INT
;
949 cpuc
->pebs_enabled
|= 1ULL << hwc
->idx
;
951 if (event
->hw
.flags
& PERF_X86_EVENT_PEBS_LDLAT
)
952 cpuc
->pebs_enabled
|= 1ULL << (hwc
->idx
+ 32);
953 else if (event
->hw
.flags
& PERF_X86_EVENT_PEBS_ST
)
954 cpuc
->pebs_enabled
|= 1ULL << 63;
957 * Use auto-reload if possible to save a MSR write in the PMI.
958 * This must be done in pmu::start(), because PERF_EVENT_IOC_PERIOD.
960 if (hwc
->flags
& PERF_X86_EVENT_AUTO_RELOAD
) {
961 ds
->pebs_event_reset
[hwc
->idx
] =
962 (u64
)(-hwc
->sample_period
) & x86_pmu
.cntval_mask
;
964 ds
->pebs_event_reset
[hwc
->idx
] = 0;
968 void intel_pmu_pebs_del(struct perf_event
*event
)
970 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
971 struct hw_perf_event
*hwc
= &event
->hw
;
972 bool needed_cb
= pebs_needs_sched_cb(cpuc
);
975 if (hwc
->flags
& PERF_X86_EVENT_FREERUNNING
)
976 cpuc
->n_large_pebs
--;
978 pebs_update_state(needed_cb
, cpuc
, event
->ctx
->pmu
);
981 void intel_pmu_pebs_disable(struct perf_event
*event
)
983 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
984 struct hw_perf_event
*hwc
= &event
->hw
;
986 if (cpuc
->n_pebs
== cpuc
->n_large_pebs
)
987 intel_pmu_drain_pebs_buffer();
989 cpuc
->pebs_enabled
&= ~(1ULL << hwc
->idx
);
991 if (event
->hw
.flags
& PERF_X86_EVENT_PEBS_LDLAT
)
992 cpuc
->pebs_enabled
&= ~(1ULL << (hwc
->idx
+ 32));
993 else if (event
->hw
.flags
& PERF_X86_EVENT_PEBS_ST
)
994 cpuc
->pebs_enabled
&= ~(1ULL << 63);
997 wrmsrl(MSR_IA32_PEBS_ENABLE
, cpuc
->pebs_enabled
);
999 hwc
->config
|= ARCH_PERFMON_EVENTSEL_INT
;
1002 void intel_pmu_pebs_enable_all(void)
1004 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1006 if (cpuc
->pebs_enabled
)
1007 wrmsrl(MSR_IA32_PEBS_ENABLE
, cpuc
->pebs_enabled
);
1010 void intel_pmu_pebs_disable_all(void)
1012 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1014 if (cpuc
->pebs_enabled
)
1015 wrmsrl(MSR_IA32_PEBS_ENABLE
, 0);
1018 static int intel_pmu_pebs_fixup_ip(struct pt_regs
*regs
)
1020 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1021 unsigned long from
= cpuc
->lbr_entries
[0].from
;
1022 unsigned long old_to
, to
= cpuc
->lbr_entries
[0].to
;
1023 unsigned long ip
= regs
->ip
;
1029 * We don't need to fixup if the PEBS assist is fault like
1031 if (!x86_pmu
.intel_cap
.pebs_trap
)
1035 * No LBR entry, no basic block, no rewinding
1037 if (!cpuc
->lbr_stack
.nr
|| !from
|| !to
)
1041 * Basic blocks should never cross user/kernel boundaries
1043 if (kernel_ip(ip
) != kernel_ip(to
))
1047 * unsigned math, either ip is before the start (impossible) or
1048 * the basic block is larger than 1 page (sanity)
1050 if ((ip
- to
) > PEBS_FIXUP_SIZE
)
1054 * We sampled a branch insn, rewind using the LBR stack
1057 set_linear_ip(regs
, from
);
1062 if (!kernel_ip(ip
)) {
1064 u8
*buf
= this_cpu_read(insn_buffer
);
1066 /* 'size' must fit our buffer, see above */
1067 bytes
= copy_from_user_nmi(buf
, (void __user
*)to
, size
);
1081 #ifdef CONFIG_X86_64
1082 is_64bit
= kernel_ip(to
) || !test_thread_flag(TIF_IA32
);
1084 insn_init(&insn
, kaddr
, size
, is_64bit
);
1085 insn_get_length(&insn
);
1087 * Make sure there was not a problem decoding the
1088 * instruction and getting the length. This is
1089 * doubly important because we have an infinite
1090 * loop if insn.length=0.
1096 kaddr
+= insn
.length
;
1097 size
-= insn
.length
;
1101 set_linear_ip(regs
, old_to
);
1106 * Even though we decoded the basic block, the instruction stream
1107 * never matched the given IP, either the TO or the IP got corrupted.
1112 static inline u64
intel_hsw_weight(struct pebs_record_skl
*pebs
)
1114 if (pebs
->tsx_tuning
) {
1115 union hsw_tsx_tuning tsx
= { .value
= pebs
->tsx_tuning
};
1116 return tsx
.cycles_last_block
;
1121 static inline u64
intel_hsw_transaction(struct pebs_record_skl
*pebs
)
1123 u64 txn
= (pebs
->tsx_tuning
& PEBS_HSW_TSX_FLAGS
) >> 32;
1125 /* For RTM XABORTs also log the abort code from AX */
1126 if ((txn
& PERF_TXN_TRANSACTION
) && (pebs
->ax
& 1))
1127 txn
|= ((pebs
->ax
>> 24) & 0xff) << PERF_TXN_ABORT_SHIFT
;
1131 static void setup_pebs_sample_data(struct perf_event
*event
,
1132 struct pt_regs
*iregs
, void *__pebs
,
1133 struct perf_sample_data
*data
,
1134 struct pt_regs
*regs
)
1136 #define PERF_X86_EVENT_PEBS_HSW_PREC \
1137 (PERF_X86_EVENT_PEBS_ST_HSW | \
1138 PERF_X86_EVENT_PEBS_LD_HSW | \
1139 PERF_X86_EVENT_PEBS_NA_HSW)
1141 * We cast to the biggest pebs_record but are careful not to
1142 * unconditionally access the 'extra' entries.
1144 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1145 struct pebs_record_skl
*pebs
= __pebs
;
1148 int fl
= event
->hw
.flags
;
1153 sample_type
= event
->attr
.sample_type
;
1154 dsrc
= sample_type
& PERF_SAMPLE_DATA_SRC
;
1156 fll
= fl
& PERF_X86_EVENT_PEBS_LDLAT
;
1157 fst
= fl
& (PERF_X86_EVENT_PEBS_ST
| PERF_X86_EVENT_PEBS_HSW_PREC
);
1159 perf_sample_data_init(data
, 0, event
->hw
.last_period
);
1161 data
->period
= event
->hw
.last_period
;
1164 * Use latency for weight (only avail with PEBS-LL)
1166 if (fll
&& (sample_type
& PERF_SAMPLE_WEIGHT
))
1167 data
->weight
= pebs
->lat
;
1170 * data.data_src encodes the data source
1173 u64 val
= PERF_MEM_NA
;
1175 val
= load_latency_data(pebs
->dse
);
1176 else if (fst
&& (fl
& PERF_X86_EVENT_PEBS_HSW_PREC
))
1177 val
= precise_datala_hsw(event
, pebs
->dse
);
1179 val
= precise_store_data(pebs
->dse
);
1180 data
->data_src
.val
= val
;
1184 * We use the interrupt regs as a base because the PEBS record does not
1185 * contain a full regs set, specifically it seems to lack segment
1186 * descriptors, which get used by things like user_mode().
1188 * In the simple case fix up only the IP for PERF_SAMPLE_IP.
1190 * We must however always use BP,SP from iregs for the unwinder to stay
1191 * sane; the record BP,SP can point into thin air when the record is
1192 * from a previous PMI context or an (I)RET happend between the record
1196 regs
->flags
= pebs
->flags
;
1197 set_linear_ip(regs
, pebs
->ip
);
1199 if (sample_type
& PERF_SAMPLE_REGS_INTR
) {
1200 regs
->ax
= pebs
->ax
;
1201 regs
->bx
= pebs
->bx
;
1202 regs
->cx
= pebs
->cx
;
1203 regs
->dx
= pebs
->dx
;
1204 regs
->si
= pebs
->si
;
1205 regs
->di
= pebs
->di
;
1208 * Per the above; only set BP,SP if we don't need callchains.
1210 * XXX: does this make sense?
1212 if (!(sample_type
& PERF_SAMPLE_CALLCHAIN
)) {
1213 regs
->bp
= pebs
->bp
;
1214 regs
->sp
= pebs
->sp
;
1218 * Preserve PERF_EFLAGS_VM from set_linear_ip().
1220 regs
->flags
= pebs
->flags
| (regs
->flags
& PERF_EFLAGS_VM
);
1221 #ifndef CONFIG_X86_32
1222 regs
->r8
= pebs
->r8
;
1223 regs
->r9
= pebs
->r9
;
1224 regs
->r10
= pebs
->r10
;
1225 regs
->r11
= pebs
->r11
;
1226 regs
->r12
= pebs
->r12
;
1227 regs
->r13
= pebs
->r13
;
1228 regs
->r14
= pebs
->r14
;
1229 regs
->r15
= pebs
->r15
;
1233 if (event
->attr
.precise_ip
> 1 && x86_pmu
.intel_cap
.pebs_format
>= 2) {
1234 regs
->ip
= pebs
->real_ip
;
1235 regs
->flags
|= PERF_EFLAGS_EXACT
;
1236 } else if (event
->attr
.precise_ip
> 1 && intel_pmu_pebs_fixup_ip(regs
))
1237 regs
->flags
|= PERF_EFLAGS_EXACT
;
1239 regs
->flags
&= ~PERF_EFLAGS_EXACT
;
1241 if ((sample_type
& (PERF_SAMPLE_ADDR
| PERF_SAMPLE_PHYS_ADDR
)) &&
1242 x86_pmu
.intel_cap
.pebs_format
>= 1)
1243 data
->addr
= pebs
->dla
;
1245 if (x86_pmu
.intel_cap
.pebs_format
>= 2) {
1246 /* Only set the TSX weight when no memory weight. */
1247 if ((sample_type
& PERF_SAMPLE_WEIGHT
) && !fll
)
1248 data
->weight
= intel_hsw_weight(pebs
);
1250 if (sample_type
& PERF_SAMPLE_TRANSACTION
)
1251 data
->txn
= intel_hsw_transaction(pebs
);
1255 * v3 supplies an accurate time stamp, so we use that
1256 * for the time stamp.
1258 * We can only do this for the default trace clock.
1260 if (x86_pmu
.intel_cap
.pebs_format
>= 3 &&
1261 event
->attr
.use_clockid
== 0)
1262 data
->time
= native_sched_clock_from_tsc(pebs
->tsc
);
1264 if (has_branch_stack(event
))
1265 data
->br_stack
= &cpuc
->lbr_stack
;
1268 static inline void *
1269 get_next_pebs_record_by_bit(void *base
, void *top
, int bit
)
1271 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1276 * fmt0 does not have a status bitfield (does not use
1277 * perf_record_nhm format)
1279 if (x86_pmu
.intel_cap
.pebs_format
< 1)
1285 for (at
= base
; at
< top
; at
+= x86_pmu
.pebs_record_size
) {
1286 struct pebs_record_nhm
*p
= at
;
1288 if (test_bit(bit
, (unsigned long *)&p
->status
)) {
1289 /* PEBS v3 has accurate status bits */
1290 if (x86_pmu
.intel_cap
.pebs_format
>= 3)
1293 if (p
->status
== (1 << bit
))
1296 /* clear non-PEBS bit and re-check */
1297 pebs_status
= p
->status
& cpuc
->pebs_enabled
;
1298 pebs_status
&= PEBS_COUNTER_MASK
;
1299 if (pebs_status
== (1 << bit
))
1306 static void __intel_pmu_pebs_event(struct perf_event
*event
,
1307 struct pt_regs
*iregs
,
1308 void *base
, void *top
,
1311 struct perf_sample_data data
;
1312 struct pt_regs regs
;
1313 void *at
= get_next_pebs_record_by_bit(base
, top
, bit
);
1315 if (!intel_pmu_save_and_restart(event
) &&
1316 !(event
->hw
.flags
& PERF_X86_EVENT_AUTO_RELOAD
))
1320 setup_pebs_sample_data(event
, iregs
, at
, &data
, ®s
);
1321 perf_event_output(event
, &data
, ®s
);
1322 at
+= x86_pmu
.pebs_record_size
;
1323 at
= get_next_pebs_record_by_bit(at
, top
, bit
);
1327 setup_pebs_sample_data(event
, iregs
, at
, &data
, ®s
);
1330 * All but the last records are processed.
1331 * The last one is left to be able to call the overflow handler.
1333 if (perf_event_overflow(event
, &data
, ®s
)) {
1334 x86_pmu_stop(event
, 0);
1340 static void intel_pmu_drain_pebs_core(struct pt_regs
*iregs
)
1342 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1343 struct debug_store
*ds
= cpuc
->ds
;
1344 struct perf_event
*event
= cpuc
->events
[0]; /* PMC0 only */
1345 struct pebs_record_core
*at
, *top
;
1348 if (!x86_pmu
.pebs_active
)
1351 at
= (struct pebs_record_core
*)(unsigned long)ds
->pebs_buffer_base
;
1352 top
= (struct pebs_record_core
*)(unsigned long)ds
->pebs_index
;
1355 * Whatever else happens, drain the thing
1357 ds
->pebs_index
= ds
->pebs_buffer_base
;
1359 if (!test_bit(0, cpuc
->active_mask
))
1362 WARN_ON_ONCE(!event
);
1364 if (!event
->attr
.precise_ip
)
1371 __intel_pmu_pebs_event(event
, iregs
, at
, top
, 0, n
);
1374 static void intel_pmu_drain_pebs_nhm(struct pt_regs
*iregs
)
1376 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1377 struct debug_store
*ds
= cpuc
->ds
;
1378 struct perf_event
*event
;
1379 void *base
, *at
, *top
;
1380 short counts
[MAX_PEBS_EVENTS
] = {};
1381 short error
[MAX_PEBS_EVENTS
] = {};
1384 if (!x86_pmu
.pebs_active
)
1387 base
= (struct pebs_record_nhm
*)(unsigned long)ds
->pebs_buffer_base
;
1388 top
= (struct pebs_record_nhm
*)(unsigned long)ds
->pebs_index
;
1390 ds
->pebs_index
= ds
->pebs_buffer_base
;
1392 if (unlikely(base
>= top
))
1395 for (at
= base
; at
< top
; at
+= x86_pmu
.pebs_record_size
) {
1396 struct pebs_record_nhm
*p
= at
;
1399 pebs_status
= p
->status
& cpuc
->pebs_enabled
;
1400 pebs_status
&= (1ULL << x86_pmu
.max_pebs_events
) - 1;
1402 /* PEBS v3 has more accurate status bits */
1403 if (x86_pmu
.intel_cap
.pebs_format
>= 3) {
1404 for_each_set_bit(bit
, (unsigned long *)&pebs_status
,
1405 x86_pmu
.max_pebs_events
)
1412 * On some CPUs the PEBS status can be zero when PEBS is
1413 * racing with clearing of GLOBAL_STATUS.
1415 * Normally we would drop that record, but in the
1416 * case when there is only a single active PEBS event
1417 * we can assume it's for that event.
1419 if (!pebs_status
&& cpuc
->pebs_enabled
&&
1420 !(cpuc
->pebs_enabled
& (cpuc
->pebs_enabled
-1)))
1421 pebs_status
= cpuc
->pebs_enabled
;
1423 bit
= find_first_bit((unsigned long *)&pebs_status
,
1424 x86_pmu
.max_pebs_events
);
1425 if (bit
>= x86_pmu
.max_pebs_events
)
1429 * The PEBS hardware does not deal well with the situation
1430 * when events happen near to each other and multiple bits
1431 * are set. But it should happen rarely.
1433 * If these events include one PEBS and multiple non-PEBS
1434 * events, it doesn't impact PEBS record. The record will
1435 * be handled normally. (slow path)
1437 * If these events include two or more PEBS events, the
1438 * records for the events can be collapsed into a single
1439 * one, and it's not possible to reconstruct all events
1440 * that caused the PEBS record. It's called collision.
1441 * If collision happened, the record will be dropped.
1443 if (p
->status
!= (1ULL << bit
)) {
1444 for_each_set_bit(i
, (unsigned long *)&pebs_status
,
1445 x86_pmu
.max_pebs_events
)
1453 for (bit
= 0; bit
< x86_pmu
.max_pebs_events
; bit
++) {
1454 if ((counts
[bit
] == 0) && (error
[bit
] == 0))
1457 event
= cpuc
->events
[bit
];
1458 if (WARN_ON_ONCE(!event
))
1461 if (WARN_ON_ONCE(!event
->attr
.precise_ip
))
1464 /* log dropped samples number */
1466 perf_log_lost_samples(event
, error
[bit
]);
1468 if (perf_event_account_interrupt(event
))
1469 x86_pmu_stop(event
, 0);
1473 __intel_pmu_pebs_event(event
, iregs
, base
,
1474 top
, bit
, counts
[bit
]);
1480 * BTS, PEBS probe and setup
1483 void __init
intel_ds_init(void)
1486 * No support for 32bit formats
1488 if (!boot_cpu_has(X86_FEATURE_DTES64
))
1491 x86_pmu
.bts
= boot_cpu_has(X86_FEATURE_BTS
);
1492 x86_pmu
.pebs
= boot_cpu_has(X86_FEATURE_PEBS
);
1493 x86_pmu
.pebs_buffer_size
= PEBS_BUFFER_SIZE
;
1495 char pebs_type
= x86_pmu
.intel_cap
.pebs_trap
? '+' : '-';
1496 int format
= x86_pmu
.intel_cap
.pebs_format
;
1500 pr_cont("PEBS fmt0%c, ", pebs_type
);
1501 x86_pmu
.pebs_record_size
= sizeof(struct pebs_record_core
);
1503 * Using >PAGE_SIZE buffers makes the WRMSR to
1504 * PERF_GLOBAL_CTRL in intel_pmu_enable_all()
1505 * mysteriously hang on Core2.
1507 * As a workaround, we don't do this.
1509 x86_pmu
.pebs_buffer_size
= PAGE_SIZE
;
1510 x86_pmu
.drain_pebs
= intel_pmu_drain_pebs_core
;
1514 pr_cont("PEBS fmt1%c, ", pebs_type
);
1515 x86_pmu
.pebs_record_size
= sizeof(struct pebs_record_nhm
);
1516 x86_pmu
.drain_pebs
= intel_pmu_drain_pebs_nhm
;
1520 pr_cont("PEBS fmt2%c, ", pebs_type
);
1521 x86_pmu
.pebs_record_size
= sizeof(struct pebs_record_hsw
);
1522 x86_pmu
.drain_pebs
= intel_pmu_drain_pebs_nhm
;
1526 pr_cont("PEBS fmt3%c, ", pebs_type
);
1527 x86_pmu
.pebs_record_size
=
1528 sizeof(struct pebs_record_skl
);
1529 x86_pmu
.drain_pebs
= intel_pmu_drain_pebs_nhm
;
1530 x86_pmu
.free_running_flags
|= PERF_SAMPLE_TIME
;
1534 pr_cont("no PEBS fmt%d%c, ", format
, pebs_type
);
1540 void perf_restore_debug_store(void)
1542 struct debug_store
*ds
= __this_cpu_read(cpu_hw_events
.ds
);
1544 if (!x86_pmu
.bts
&& !x86_pmu
.pebs
)
1547 wrmsrl(MSR_IA32_DS_AREA
, (unsigned long)ds
);