1 #include <linux/perf_event.h>
2 #include <linux/types.h>
4 #include <asm/perf_event.h>
8 #include "../perf_event.h"
12 LBR_FORMAT_LIP
= 0x01,
13 LBR_FORMAT_EIP
= 0x02,
14 LBR_FORMAT_EIP_FLAGS
= 0x03,
15 LBR_FORMAT_EIP_FLAGS2
= 0x04,
16 LBR_FORMAT_INFO
= 0x05,
17 LBR_FORMAT_TIME
= 0x06,
18 LBR_FORMAT_MAX_KNOWN
= LBR_FORMAT_TIME
,
24 } lbr_desc
[LBR_FORMAT_MAX_KNOWN
+ 1] = {
25 [LBR_FORMAT_EIP_FLAGS
] = LBR_EIP_FLAGS
,
26 [LBR_FORMAT_EIP_FLAGS2
] = LBR_EIP_FLAGS
| LBR_TSX
,
30 * Intel LBR_SELECT bits
31 * Intel Vol3a, April 2011, Section 16.7 Table 16-10
33 * Hardware branch filter (not available on all CPUs)
35 #define LBR_KERNEL_BIT 0 /* do not capture at ring0 */
36 #define LBR_USER_BIT 1 /* do not capture at ring > 0 */
37 #define LBR_JCC_BIT 2 /* do not capture conditional branches */
38 #define LBR_REL_CALL_BIT 3 /* do not capture relative calls */
39 #define LBR_IND_CALL_BIT 4 /* do not capture indirect calls */
40 #define LBR_RETURN_BIT 5 /* do not capture near returns */
41 #define LBR_IND_JMP_BIT 6 /* do not capture indirect jumps */
42 #define LBR_REL_JMP_BIT 7 /* do not capture relative jumps */
43 #define LBR_FAR_BIT 8 /* do not capture far branches */
44 #define LBR_CALL_STACK_BIT 9 /* enable call stack */
47 * Following bit only exists in Linux; we mask it out before writing it to
48 * the actual MSR. But it helps the constraint perf code to understand
49 * that this is a separate configuration.
51 #define LBR_NO_INFO_BIT 63 /* don't read LBR_INFO. */
53 #define LBR_KERNEL (1 << LBR_KERNEL_BIT)
54 #define LBR_USER (1 << LBR_USER_BIT)
55 #define LBR_JCC (1 << LBR_JCC_BIT)
56 #define LBR_REL_CALL (1 << LBR_REL_CALL_BIT)
57 #define LBR_IND_CALL (1 << LBR_IND_CALL_BIT)
58 #define LBR_RETURN (1 << LBR_RETURN_BIT)
59 #define LBR_REL_JMP (1 << LBR_REL_JMP_BIT)
60 #define LBR_IND_JMP (1 << LBR_IND_JMP_BIT)
61 #define LBR_FAR (1 << LBR_FAR_BIT)
62 #define LBR_CALL_STACK (1 << LBR_CALL_STACK_BIT)
63 #define LBR_NO_INFO (1ULL << LBR_NO_INFO_BIT)
65 #define LBR_PLM (LBR_KERNEL | LBR_USER)
67 #define LBR_SEL_MASK 0x3ff /* valid bits in LBR_SELECT */
68 #define LBR_NOT_SUPP -1 /* LBR filter not supported */
69 #define LBR_IGN 0 /* ignored */
80 #define LBR_FROM_FLAG_MISPRED BIT_ULL(63)
81 #define LBR_FROM_FLAG_IN_TX BIT_ULL(62)
82 #define LBR_FROM_FLAG_ABORT BIT_ULL(61)
84 #define LBR_FROM_SIGNEXT_2MSB (BIT_ULL(60) | BIT_ULL(59))
87 * x86control flow change classification
88 * x86control flow changes include branches, interrupts, traps, faults
91 X86_BR_NONE
= 0, /* unknown */
93 X86_BR_USER
= 1 << 0, /* branch target is user */
94 X86_BR_KERNEL
= 1 << 1, /* branch target is kernel */
96 X86_BR_CALL
= 1 << 2, /* call */
97 X86_BR_RET
= 1 << 3, /* return */
98 X86_BR_SYSCALL
= 1 << 4, /* syscall */
99 X86_BR_SYSRET
= 1 << 5, /* syscall return */
100 X86_BR_INT
= 1 << 6, /* sw interrupt */
101 X86_BR_IRET
= 1 << 7, /* return from interrupt */
102 X86_BR_JCC
= 1 << 8, /* conditional */
103 X86_BR_JMP
= 1 << 9, /* jump */
104 X86_BR_IRQ
= 1 << 10,/* hw interrupt or trap or fault */
105 X86_BR_IND_CALL
= 1 << 11,/* indirect calls */
106 X86_BR_ABORT
= 1 << 12,/* transaction abort */
107 X86_BR_IN_TX
= 1 << 13,/* in transaction */
108 X86_BR_NO_TX
= 1 << 14,/* not in transaction */
109 X86_BR_ZERO_CALL
= 1 << 15,/* zero length call */
110 X86_BR_CALL_STACK
= 1 << 16,/* call stack */
111 X86_BR_IND_JMP
= 1 << 17,/* indirect jump */
114 #define X86_BR_PLM (X86_BR_USER | X86_BR_KERNEL)
115 #define X86_BR_ANYTX (X86_BR_NO_TX | X86_BR_IN_TX)
132 #define X86_BR_ALL (X86_BR_PLM | X86_BR_ANY)
134 #define X86_BR_ANY_CALL \
142 static void intel_pmu_lbr_filter(struct cpu_hw_events
*cpuc
);
145 * We only support LBR implementations that have FREEZE_LBRS_ON_PMI
146 * otherwise it becomes near impossible to get a reliable stack.
149 static void __intel_pmu_lbr_enable(bool pmi
)
151 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
152 u64 debugctl
, lbr_select
= 0, orig_debugctl
;
155 * No need to unfreeze manually, as v4 can do that as part
156 * of the GLOBAL_STATUS ack.
158 if (pmi
&& x86_pmu
.version
>= 4)
162 * No need to reprogram LBR_SELECT in a PMI, as it
166 lbr_select
= cpuc
->lbr_sel
->config
& x86_pmu
.lbr_sel_mask
;
167 if (!pmi
&& cpuc
->lbr_sel
)
168 wrmsrl(MSR_LBR_SELECT
, lbr_select
);
170 rdmsrl(MSR_IA32_DEBUGCTLMSR
, debugctl
);
171 orig_debugctl
= debugctl
;
172 debugctl
|= DEBUGCTLMSR_LBR
;
174 * LBR callstack does not work well with FREEZE_LBRS_ON_PMI.
175 * If FREEZE_LBRS_ON_PMI is set, PMI near call/return instructions
176 * may cause superfluous increase/decrease of LBR_TOS.
178 if (!(lbr_select
& LBR_CALL_STACK
))
179 debugctl
|= DEBUGCTLMSR_FREEZE_LBRS_ON_PMI
;
180 if (orig_debugctl
!= debugctl
)
181 wrmsrl(MSR_IA32_DEBUGCTLMSR
, debugctl
);
184 static void __intel_pmu_lbr_disable(void)
188 rdmsrl(MSR_IA32_DEBUGCTLMSR
, debugctl
);
189 debugctl
&= ~(DEBUGCTLMSR_LBR
| DEBUGCTLMSR_FREEZE_LBRS_ON_PMI
);
190 wrmsrl(MSR_IA32_DEBUGCTLMSR
, debugctl
);
193 static void intel_pmu_lbr_reset_32(void)
197 for (i
= 0; i
< x86_pmu
.lbr_nr
; i
++)
198 wrmsrl(x86_pmu
.lbr_from
+ i
, 0);
201 static void intel_pmu_lbr_reset_64(void)
205 for (i
= 0; i
< x86_pmu
.lbr_nr
; i
++) {
206 wrmsrl(x86_pmu
.lbr_from
+ i
, 0);
207 wrmsrl(x86_pmu
.lbr_to
+ i
, 0);
208 if (x86_pmu
.intel_cap
.lbr_format
== LBR_FORMAT_INFO
)
209 wrmsrl(MSR_LBR_INFO_0
+ i
, 0);
213 void intel_pmu_lbr_reset(void)
218 if (x86_pmu
.intel_cap
.lbr_format
== LBR_FORMAT_32
)
219 intel_pmu_lbr_reset_32();
221 intel_pmu_lbr_reset_64();
225 * TOS = most recently recorded branch
227 static inline u64
intel_pmu_lbr_tos(void)
231 rdmsrl(x86_pmu
.lbr_tos
, tos
);
241 * For formats with LBR_TSX flags (e.g. LBR_FORMAT_EIP_FLAGS2), bits 61:62 in
242 * MSR_LAST_BRANCH_FROM_x are the TSX flags when TSX is supported, but when
243 * TSX is not supported they have no consistent behavior:
245 * - For wrmsr(), bits 61:62 are considered part of the sign extension.
246 * - For HW updates (branch captures) bits 61:62 are always OFF and are not
247 * part of the sign extension.
251 * 1) LBR has TSX format
252 * 2) CPU has no TSX support enabled
254 * ... then any value passed to wrmsr() must be sign extended to 63 bits and any
255 * value from rdmsr() must be converted to have a 61 bits sign extension,
256 * ignoring the TSX flags.
258 static inline bool lbr_from_signext_quirk_needed(void)
260 int lbr_format
= x86_pmu
.intel_cap
.lbr_format
;
261 bool tsx_support
= boot_cpu_has(X86_FEATURE_HLE
) ||
262 boot_cpu_has(X86_FEATURE_RTM
);
264 return !tsx_support
&& (lbr_desc
[lbr_format
] & LBR_TSX
);
267 DEFINE_STATIC_KEY_FALSE(lbr_from_quirk_key
);
269 /* If quirk is enabled, ensure sign extension is 63 bits: */
270 inline u64
lbr_from_signext_quirk_wr(u64 val
)
272 if (static_branch_unlikely(&lbr_from_quirk_key
)) {
274 * Sign extend into bits 61:62 while preserving bit 63.
276 * Quirk is enabled when TSX is disabled. Therefore TSX bits
277 * in val are always OFF and must be changed to be sign
278 * extension bits. Since bits 59:60 are guaranteed to be
279 * part of the sign extension bits, we can just copy them
282 val
|= (LBR_FROM_SIGNEXT_2MSB
& val
) << 2;
288 * If quirk is needed, ensure sign extension is 61 bits:
290 static u64
lbr_from_signext_quirk_rd(u64 val
)
292 if (static_branch_unlikely(&lbr_from_quirk_key
)) {
294 * Quirk is on when TSX is not enabled. Therefore TSX
295 * flags must be read as OFF.
297 val
&= ~(LBR_FROM_FLAG_IN_TX
| LBR_FROM_FLAG_ABORT
);
302 static inline void wrlbr_from(unsigned int idx
, u64 val
)
304 val
= lbr_from_signext_quirk_wr(val
);
305 wrmsrl(x86_pmu
.lbr_from
+ idx
, val
);
308 static inline void wrlbr_to(unsigned int idx
, u64 val
)
310 wrmsrl(x86_pmu
.lbr_to
+ idx
, val
);
313 static inline u64
rdlbr_from(unsigned int idx
)
317 rdmsrl(x86_pmu
.lbr_from
+ idx
, val
);
319 return lbr_from_signext_quirk_rd(val
);
322 static inline u64
rdlbr_to(unsigned int idx
)
326 rdmsrl(x86_pmu
.lbr_to
+ idx
, val
);
331 static void __intel_pmu_lbr_restore(struct x86_perf_task_context
*task_ctx
)
334 unsigned lbr_idx
, mask
;
337 if (task_ctx
->lbr_callstack_users
== 0 ||
338 task_ctx
->lbr_stack_state
== LBR_NONE
) {
339 intel_pmu_lbr_reset();
343 mask
= x86_pmu
.lbr_nr
- 1;
345 for (i
= 0; i
< tos
; i
++) {
346 lbr_idx
= (tos
- i
) & mask
;
347 wrlbr_from(lbr_idx
, task_ctx
->lbr_from
[i
]);
348 wrlbr_to (lbr_idx
, task_ctx
->lbr_to
[i
]);
350 if (x86_pmu
.intel_cap
.lbr_format
== LBR_FORMAT_INFO
)
351 wrmsrl(MSR_LBR_INFO_0
+ lbr_idx
, task_ctx
->lbr_info
[i
]);
353 wrmsrl(x86_pmu
.lbr_tos
, tos
);
354 task_ctx
->lbr_stack_state
= LBR_NONE
;
357 static void __intel_pmu_lbr_save(struct x86_perf_task_context
*task_ctx
)
359 unsigned lbr_idx
, mask
;
363 if (task_ctx
->lbr_callstack_users
== 0) {
364 task_ctx
->lbr_stack_state
= LBR_NONE
;
368 mask
= x86_pmu
.lbr_nr
- 1;
369 tos
= intel_pmu_lbr_tos();
370 for (i
= 0; i
< tos
; i
++) {
371 lbr_idx
= (tos
- i
) & mask
;
372 task_ctx
->lbr_from
[i
] = rdlbr_from(lbr_idx
);
373 task_ctx
->lbr_to
[i
] = rdlbr_to(lbr_idx
);
374 if (x86_pmu
.intel_cap
.lbr_format
== LBR_FORMAT_INFO
)
375 rdmsrl(MSR_LBR_INFO_0
+ lbr_idx
, task_ctx
->lbr_info
[i
]);
378 task_ctx
->lbr_stack_state
= LBR_VALID
;
381 void intel_pmu_lbr_sched_task(struct perf_event_context
*ctx
, bool sched_in
)
383 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
384 struct x86_perf_task_context
*task_ctx
;
386 if (!cpuc
->lbr_users
)
390 * If LBR callstack feature is enabled and the stack was saved when
391 * the task was scheduled out, restore the stack. Otherwise flush
394 task_ctx
= ctx
? ctx
->task_ctx_data
: NULL
;
397 __intel_pmu_lbr_restore(task_ctx
);
399 __intel_pmu_lbr_save(task_ctx
);
404 * Since a context switch can flip the address space and LBR entries
405 * are not tagged with an identifier, we need to wipe the LBR, even for
406 * per-cpu events. You simply cannot resolve the branches from the old
410 intel_pmu_lbr_reset();
413 static inline bool branch_user_callstack(unsigned br_sel
)
415 return (br_sel
& X86_BR_USER
) && (br_sel
& X86_BR_CALL_STACK
);
418 void intel_pmu_lbr_add(struct perf_event
*event
)
420 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
421 struct x86_perf_task_context
*task_ctx
;
426 cpuc
->br_sel
= event
->hw
.branch_reg
.reg
;
428 if (branch_user_callstack(cpuc
->br_sel
) && event
->ctx
->task_ctx_data
) {
429 task_ctx
= event
->ctx
->task_ctx_data
;
430 task_ctx
->lbr_callstack_users
++;
434 * Request pmu::sched_task() callback, which will fire inside the
435 * regular perf event scheduling, so that call will:
437 * - restore or wipe; when LBR-callstack,
440 * when this is from __perf_event_task_sched_in().
442 * However, if this is from perf_install_in_context(), no such callback
443 * will follow and we'll need to reset the LBR here if this is the
446 * The problem is, we cannot tell these cases apart... but we can
447 * exclude the biggest chunk of cases by looking at
448 * event->total_time_running. An event that has accrued runtime cannot
449 * be 'new'. Conversely, a new event can get installed through the
450 * context switch path for the first time.
452 perf_sched_cb_inc(event
->ctx
->pmu
);
453 if (!cpuc
->lbr_users
++ && !event
->total_time_running
)
454 intel_pmu_lbr_reset();
457 void intel_pmu_lbr_del(struct perf_event
*event
)
459 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
460 struct x86_perf_task_context
*task_ctx
;
465 if (branch_user_callstack(cpuc
->br_sel
) &&
466 event
->ctx
->task_ctx_data
) {
467 task_ctx
= event
->ctx
->task_ctx_data
;
468 task_ctx
->lbr_callstack_users
--;
472 WARN_ON_ONCE(cpuc
->lbr_users
< 0);
473 perf_sched_cb_dec(event
->ctx
->pmu
);
476 void intel_pmu_lbr_enable_all(bool pmi
)
478 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
481 __intel_pmu_lbr_enable(pmi
);
484 void intel_pmu_lbr_disable_all(void)
486 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
489 __intel_pmu_lbr_disable();
492 static void intel_pmu_lbr_read_32(struct cpu_hw_events
*cpuc
)
494 unsigned long mask
= x86_pmu
.lbr_nr
- 1;
495 u64 tos
= intel_pmu_lbr_tos();
498 for (i
= 0; i
< x86_pmu
.lbr_nr
; i
++) {
499 unsigned long lbr_idx
= (tos
- i
) & mask
;
508 rdmsrl(x86_pmu
.lbr_from
+ lbr_idx
, msr_lastbranch
.lbr
);
510 cpuc
->lbr_entries
[i
].from
= msr_lastbranch
.from
;
511 cpuc
->lbr_entries
[i
].to
= msr_lastbranch
.to
;
512 cpuc
->lbr_entries
[i
].mispred
= 0;
513 cpuc
->lbr_entries
[i
].predicted
= 0;
514 cpuc
->lbr_entries
[i
].in_tx
= 0;
515 cpuc
->lbr_entries
[i
].abort
= 0;
516 cpuc
->lbr_entries
[i
].cycles
= 0;
517 cpuc
->lbr_entries
[i
].reserved
= 0;
519 cpuc
->lbr_stack
.nr
= i
;
523 * Due to lack of segmentation in Linux the effective address (offset)
524 * is the same as the linear address, allowing us to merge the LIP and EIP
527 static void intel_pmu_lbr_read_64(struct cpu_hw_events
*cpuc
)
529 bool need_info
= false;
530 unsigned long mask
= x86_pmu
.lbr_nr
- 1;
531 int lbr_format
= x86_pmu
.intel_cap
.lbr_format
;
532 u64 tos
= intel_pmu_lbr_tos();
535 int num
= x86_pmu
.lbr_nr
;
538 need_info
= !(cpuc
->lbr_sel
->config
& LBR_NO_INFO
);
539 if (cpuc
->lbr_sel
->config
& LBR_CALL_STACK
)
543 for (i
= 0; i
< num
; i
++) {
544 unsigned long lbr_idx
= (tos
- i
) & mask
;
545 u64 from
, to
, mis
= 0, pred
= 0, in_tx
= 0, abort
= 0;
548 int lbr_flags
= lbr_desc
[lbr_format
];
550 from
= rdlbr_from(lbr_idx
);
551 to
= rdlbr_to(lbr_idx
);
553 if (lbr_format
== LBR_FORMAT_INFO
&& need_info
) {
556 rdmsrl(MSR_LBR_INFO_0
+ lbr_idx
, info
);
557 mis
= !!(info
& LBR_INFO_MISPRED
);
559 in_tx
= !!(info
& LBR_INFO_IN_TX
);
560 abort
= !!(info
& LBR_INFO_ABORT
);
561 cycles
= (info
& LBR_INFO_CYCLES
);
564 if (lbr_format
== LBR_FORMAT_TIME
) {
565 mis
= !!(from
& LBR_FROM_FLAG_MISPRED
);
568 cycles
= ((to
>> 48) & LBR_INFO_CYCLES
);
570 to
= (u64
)((((s64
)to
) << 16) >> 16);
573 if (lbr_flags
& LBR_EIP_FLAGS
) {
574 mis
= !!(from
& LBR_FROM_FLAG_MISPRED
);
578 if (lbr_flags
& LBR_TSX
) {
579 in_tx
= !!(from
& LBR_FROM_FLAG_IN_TX
);
580 abort
= !!(from
& LBR_FROM_FLAG_ABORT
);
583 from
= (u64
)((((s64
)from
) << skip
) >> skip
);
586 * Some CPUs report duplicated abort records,
587 * with the second entry not having an abort bit set.
588 * Skip them here. This loop runs backwards,
589 * so we need to undo the previous record.
590 * If the abort just happened outside the window
591 * the extra entry cannot be removed.
593 if (abort
&& x86_pmu
.lbr_double_abort
&& out
> 0)
596 cpuc
->lbr_entries
[out
].from
= from
;
597 cpuc
->lbr_entries
[out
].to
= to
;
598 cpuc
->lbr_entries
[out
].mispred
= mis
;
599 cpuc
->lbr_entries
[out
].predicted
= pred
;
600 cpuc
->lbr_entries
[out
].in_tx
= in_tx
;
601 cpuc
->lbr_entries
[out
].abort
= abort
;
602 cpuc
->lbr_entries
[out
].cycles
= cycles
;
603 cpuc
->lbr_entries
[out
].reserved
= 0;
606 cpuc
->lbr_stack
.nr
= out
;
609 void intel_pmu_lbr_read(void)
611 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
613 if (!cpuc
->lbr_users
)
616 if (x86_pmu
.intel_cap
.lbr_format
== LBR_FORMAT_32
)
617 intel_pmu_lbr_read_32(cpuc
);
619 intel_pmu_lbr_read_64(cpuc
);
621 intel_pmu_lbr_filter(cpuc
);
626 * - in case there is no HW filter
627 * - in case the HW filter has errata or limitations
629 static int intel_pmu_setup_sw_lbr_filter(struct perf_event
*event
)
631 u64 br_type
= event
->attr
.branch_sample_type
;
634 if (br_type
& PERF_SAMPLE_BRANCH_USER
)
637 if (br_type
& PERF_SAMPLE_BRANCH_KERNEL
)
638 mask
|= X86_BR_KERNEL
;
640 /* we ignore BRANCH_HV here */
642 if (br_type
& PERF_SAMPLE_BRANCH_ANY
)
645 if (br_type
& PERF_SAMPLE_BRANCH_ANY_CALL
)
646 mask
|= X86_BR_ANY_CALL
;
648 if (br_type
& PERF_SAMPLE_BRANCH_ANY_RETURN
)
649 mask
|= X86_BR_RET
| X86_BR_IRET
| X86_BR_SYSRET
;
651 if (br_type
& PERF_SAMPLE_BRANCH_IND_CALL
)
652 mask
|= X86_BR_IND_CALL
;
654 if (br_type
& PERF_SAMPLE_BRANCH_ABORT_TX
)
655 mask
|= X86_BR_ABORT
;
657 if (br_type
& PERF_SAMPLE_BRANCH_IN_TX
)
658 mask
|= X86_BR_IN_TX
;
660 if (br_type
& PERF_SAMPLE_BRANCH_NO_TX
)
661 mask
|= X86_BR_NO_TX
;
663 if (br_type
& PERF_SAMPLE_BRANCH_COND
)
666 if (br_type
& PERF_SAMPLE_BRANCH_CALL_STACK
) {
667 if (!x86_pmu_has_lbr_callstack())
669 if (mask
& ~(X86_BR_USER
| X86_BR_KERNEL
))
671 mask
|= X86_BR_CALL
| X86_BR_IND_CALL
| X86_BR_RET
|
675 if (br_type
& PERF_SAMPLE_BRANCH_IND_JUMP
)
676 mask
|= X86_BR_IND_JMP
;
678 if (br_type
& PERF_SAMPLE_BRANCH_CALL
)
679 mask
|= X86_BR_CALL
| X86_BR_ZERO_CALL
;
681 * stash actual user request into reg, it may
682 * be used by fixup code for some CPU
684 event
->hw
.branch_reg
.reg
= mask
;
689 * setup the HW LBR filter
690 * Used only when available, may not be enough to disambiguate
691 * all branches, may need the help of the SW filter
693 static int intel_pmu_setup_hw_lbr_filter(struct perf_event
*event
)
695 struct hw_perf_event_extra
*reg
;
696 u64 br_type
= event
->attr
.branch_sample_type
;
700 for (i
= 0; i
< PERF_SAMPLE_BRANCH_MAX_SHIFT
; i
++) {
701 if (!(br_type
& (1ULL << i
)))
704 v
= x86_pmu
.lbr_sel_map
[i
];
705 if (v
== LBR_NOT_SUPP
)
712 reg
= &event
->hw
.branch_reg
;
713 reg
->idx
= EXTRA_REG_LBR
;
716 * The first 9 bits (LBR_SEL_MASK) in LBR_SELECT operate
717 * in suppress mode. So LBR_SELECT should be set to
718 * (~mask & LBR_SEL_MASK) | (mask & ~LBR_SEL_MASK)
719 * But the 10th bit LBR_CALL_STACK does not operate
722 reg
->config
= mask
^ (x86_pmu
.lbr_sel_mask
& ~LBR_CALL_STACK
);
724 if ((br_type
& PERF_SAMPLE_BRANCH_NO_CYCLES
) &&
725 (br_type
& PERF_SAMPLE_BRANCH_NO_FLAGS
) &&
726 (x86_pmu
.intel_cap
.lbr_format
== LBR_FORMAT_INFO
))
727 reg
->config
|= LBR_NO_INFO
;
732 int intel_pmu_setup_lbr_filter(struct perf_event
*event
)
743 * setup SW LBR filter
745 ret
= intel_pmu_setup_sw_lbr_filter(event
);
750 * setup HW LBR filter, if any
752 if (x86_pmu
.lbr_sel_map
)
753 ret
= intel_pmu_setup_hw_lbr_filter(event
);
759 * return the type of control flow change at address "from"
760 * instruction is not necessarily a branch (in case of interrupt).
762 * The branch type returned also includes the priv level of the
763 * target of the control flow change (X86_BR_USER, X86_BR_KERNEL).
765 * If a branch type is unknown OR the instruction cannot be
766 * decoded (e.g., text page not present), then X86_BR_NONE is
769 static int branch_type(unsigned long from
, unsigned long to
, int abort
)
773 int bytes_read
, bytes_left
;
774 int ret
= X86_BR_NONE
;
775 int ext
, to_plm
, from_plm
;
776 u8 buf
[MAX_INSN_SIZE
];
779 to_plm
= kernel_ip(to
) ? X86_BR_KERNEL
: X86_BR_USER
;
780 from_plm
= kernel_ip(from
) ? X86_BR_KERNEL
: X86_BR_USER
;
783 * maybe zero if lbr did not fill up after a reset by the time
784 * we get a PMU interrupt
786 if (from
== 0 || to
== 0)
790 return X86_BR_ABORT
| to_plm
;
792 if (from_plm
== X86_BR_USER
) {
794 * can happen if measuring at the user level only
795 * and we interrupt in a kernel thread, e.g., idle.
800 /* may fail if text not present */
801 bytes_left
= copy_from_user_nmi(buf
, (void __user
*)from
,
803 bytes_read
= MAX_INSN_SIZE
- bytes_left
;
810 * The LBR logs any address in the IP, even if the IP just
811 * faulted. This means userspace can control the from address.
812 * Ensure we don't blindy read any address by validating it is
813 * a known text address.
815 if (kernel_text_address(from
)) {
818 * Assume we can get the maximum possible size
819 * when grabbing kernel data. This is not
820 * _strictly_ true since we could possibly be
821 * executing up next to a memory hole, but
822 * it is very unlikely to be a problem.
824 bytes_read
= MAX_INSN_SIZE
;
831 * decoder needs to know the ABI especially
832 * on 64-bit systems running 32-bit apps
835 is64
= kernel_ip((unsigned long)addr
) || !test_thread_flag(TIF_IA32
);
837 insn_init(&insn
, addr
, bytes_read
, is64
);
838 insn_get_opcode(&insn
);
839 if (!insn
.opcode
.got
)
842 switch (insn
.opcode
.bytes
[0]) {
844 switch (insn
.opcode
.bytes
[1]) {
845 case 0x05: /* syscall */
846 case 0x34: /* sysenter */
847 ret
= X86_BR_SYSCALL
;
849 case 0x07: /* sysret */
850 case 0x35: /* sysexit */
853 case 0x80 ... 0x8f: /* conditional */
860 case 0x70 ... 0x7f: /* conditional */
863 case 0xc2: /* near ret */
864 case 0xc3: /* near ret */
865 case 0xca: /* far ret */
866 case 0xcb: /* far ret */
869 case 0xcf: /* iret */
872 case 0xcc ... 0xce: /* int */
875 case 0xe8: /* call near rel */
876 insn_get_immediate(&insn
);
877 if (insn
.immediate1
.value
== 0) {
878 /* zero length call */
879 ret
= X86_BR_ZERO_CALL
;
882 case 0x9a: /* call far absolute */
885 case 0xe0 ... 0xe3: /* loop jmp */
888 case 0xe9 ... 0xeb: /* jmp */
891 case 0xff: /* call near absolute, call far absolute ind */
892 insn_get_modrm(&insn
);
893 ext
= (insn
.modrm
.bytes
[0] >> 3) & 0x7;
895 case 2: /* near ind call */
896 case 3: /* far ind call */
897 ret
= X86_BR_IND_CALL
;
901 ret
= X86_BR_IND_JMP
;
909 * interrupts, traps, faults (and thus ring transition) may
910 * occur on any instructions. Thus, to classify them correctly,
911 * we need to first look at the from and to priv levels. If they
912 * are different and to is in the kernel, then it indicates
913 * a ring transition. If the from instruction is not a ring
914 * transition instr (syscall, systenter, int), then it means
915 * it was a irq, trap or fault.
917 * we have no way of detecting kernel to kernel faults.
919 if (from_plm
== X86_BR_USER
&& to_plm
== X86_BR_KERNEL
920 && ret
!= X86_BR_SYSCALL
&& ret
!= X86_BR_INT
)
924 * branch priv level determined by target as
925 * is done by HW when LBR_SELECT is implemented
927 if (ret
!= X86_BR_NONE
)
934 * implement actual branch filter based on user demand.
935 * Hardware may not exactly satisfy that request, thus
936 * we need to inspect opcodes. Mismatched branches are
937 * discarded. Therefore, the number of branches returned
938 * in PERF_SAMPLE_BRANCH_STACK sample may vary.
941 intel_pmu_lbr_filter(struct cpu_hw_events
*cpuc
)
944 int br_sel
= cpuc
->br_sel
;
946 bool compress
= false;
948 /* if sampling all branches, then nothing to filter */
949 if ((br_sel
& X86_BR_ALL
) == X86_BR_ALL
)
952 for (i
= 0; i
< cpuc
->lbr_stack
.nr
; i
++) {
954 from
= cpuc
->lbr_entries
[i
].from
;
955 to
= cpuc
->lbr_entries
[i
].to
;
957 type
= branch_type(from
, to
, cpuc
->lbr_entries
[i
].abort
);
958 if (type
!= X86_BR_NONE
&& (br_sel
& X86_BR_ANYTX
)) {
959 if (cpuc
->lbr_entries
[i
].in_tx
)
960 type
|= X86_BR_IN_TX
;
962 type
|= X86_BR_NO_TX
;
965 /* if type does not correspond, then discard */
966 if (type
== X86_BR_NONE
|| (br_sel
& type
) != type
) {
967 cpuc
->lbr_entries
[i
].from
= 0;
975 /* remove all entries with from=0 */
976 for (i
= 0; i
< cpuc
->lbr_stack
.nr
; ) {
977 if (!cpuc
->lbr_entries
[i
].from
) {
979 while (++j
< cpuc
->lbr_stack
.nr
)
980 cpuc
->lbr_entries
[j
-1] = cpuc
->lbr_entries
[j
];
981 cpuc
->lbr_stack
.nr
--;
982 if (!cpuc
->lbr_entries
[i
].from
)
990 * Map interface branch filters onto LBR filters
992 static const int nhm_lbr_sel_map
[PERF_SAMPLE_BRANCH_MAX_SHIFT
] = {
993 [PERF_SAMPLE_BRANCH_ANY_SHIFT
] = LBR_ANY
,
994 [PERF_SAMPLE_BRANCH_USER_SHIFT
] = LBR_USER
,
995 [PERF_SAMPLE_BRANCH_KERNEL_SHIFT
] = LBR_KERNEL
,
996 [PERF_SAMPLE_BRANCH_HV_SHIFT
] = LBR_IGN
,
997 [PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT
] = LBR_RETURN
| LBR_REL_JMP
998 | LBR_IND_JMP
| LBR_FAR
,
1000 * NHM/WSM erratum: must include REL_JMP+IND_JMP to get CALL branches
1002 [PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT
] =
1003 LBR_REL_CALL
| LBR_IND_CALL
| LBR_REL_JMP
| LBR_IND_JMP
| LBR_FAR
,
1005 * NHM/WSM erratum: must include IND_JMP to capture IND_CALL
1007 [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT
] = LBR_IND_CALL
| LBR_IND_JMP
,
1008 [PERF_SAMPLE_BRANCH_COND_SHIFT
] = LBR_JCC
,
1009 [PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT
] = LBR_IND_JMP
,
1012 static const int snb_lbr_sel_map
[PERF_SAMPLE_BRANCH_MAX_SHIFT
] = {
1013 [PERF_SAMPLE_BRANCH_ANY_SHIFT
] = LBR_ANY
,
1014 [PERF_SAMPLE_BRANCH_USER_SHIFT
] = LBR_USER
,
1015 [PERF_SAMPLE_BRANCH_KERNEL_SHIFT
] = LBR_KERNEL
,
1016 [PERF_SAMPLE_BRANCH_HV_SHIFT
] = LBR_IGN
,
1017 [PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT
] = LBR_RETURN
| LBR_FAR
,
1018 [PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT
] = LBR_REL_CALL
| LBR_IND_CALL
1020 [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT
] = LBR_IND_CALL
,
1021 [PERF_SAMPLE_BRANCH_COND_SHIFT
] = LBR_JCC
,
1022 [PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT
] = LBR_IND_JMP
,
1023 [PERF_SAMPLE_BRANCH_CALL_SHIFT
] = LBR_REL_CALL
,
1026 static const int hsw_lbr_sel_map
[PERF_SAMPLE_BRANCH_MAX_SHIFT
] = {
1027 [PERF_SAMPLE_BRANCH_ANY_SHIFT
] = LBR_ANY
,
1028 [PERF_SAMPLE_BRANCH_USER_SHIFT
] = LBR_USER
,
1029 [PERF_SAMPLE_BRANCH_KERNEL_SHIFT
] = LBR_KERNEL
,
1030 [PERF_SAMPLE_BRANCH_HV_SHIFT
] = LBR_IGN
,
1031 [PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT
] = LBR_RETURN
| LBR_FAR
,
1032 [PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT
] = LBR_REL_CALL
| LBR_IND_CALL
1034 [PERF_SAMPLE_BRANCH_IND_CALL_SHIFT
] = LBR_IND_CALL
,
1035 [PERF_SAMPLE_BRANCH_COND_SHIFT
] = LBR_JCC
,
1036 [PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT
] = LBR_REL_CALL
| LBR_IND_CALL
1037 | LBR_RETURN
| LBR_CALL_STACK
,
1038 [PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT
] = LBR_IND_JMP
,
1039 [PERF_SAMPLE_BRANCH_CALL_SHIFT
] = LBR_REL_CALL
,
1043 void __init
intel_pmu_lbr_init_core(void)
1046 x86_pmu
.lbr_tos
= MSR_LBR_TOS
;
1047 x86_pmu
.lbr_from
= MSR_LBR_CORE_FROM
;
1048 x86_pmu
.lbr_to
= MSR_LBR_CORE_TO
;
1051 * SW branch filter usage:
1052 * - compensate for lack of HW filter
1056 /* nehalem/westmere */
1057 void __init
intel_pmu_lbr_init_nhm(void)
1059 x86_pmu
.lbr_nr
= 16;
1060 x86_pmu
.lbr_tos
= MSR_LBR_TOS
;
1061 x86_pmu
.lbr_from
= MSR_LBR_NHM_FROM
;
1062 x86_pmu
.lbr_to
= MSR_LBR_NHM_TO
;
1064 x86_pmu
.lbr_sel_mask
= LBR_SEL_MASK
;
1065 x86_pmu
.lbr_sel_map
= nhm_lbr_sel_map
;
1068 * SW branch filter usage:
1069 * - workaround LBR_SEL errata (see above)
1070 * - support syscall, sysret capture.
1071 * That requires LBR_FAR but that means far
1072 * jmp need to be filtered out
1077 void __init
intel_pmu_lbr_init_snb(void)
1079 x86_pmu
.lbr_nr
= 16;
1080 x86_pmu
.lbr_tos
= MSR_LBR_TOS
;
1081 x86_pmu
.lbr_from
= MSR_LBR_NHM_FROM
;
1082 x86_pmu
.lbr_to
= MSR_LBR_NHM_TO
;
1084 x86_pmu
.lbr_sel_mask
= LBR_SEL_MASK
;
1085 x86_pmu
.lbr_sel_map
= snb_lbr_sel_map
;
1088 * SW branch filter usage:
1089 * - support syscall, sysret capture.
1090 * That requires LBR_FAR but that means far
1091 * jmp need to be filtered out
1096 void intel_pmu_lbr_init_hsw(void)
1098 x86_pmu
.lbr_nr
= 16;
1099 x86_pmu
.lbr_tos
= MSR_LBR_TOS
;
1100 x86_pmu
.lbr_from
= MSR_LBR_NHM_FROM
;
1101 x86_pmu
.lbr_to
= MSR_LBR_NHM_TO
;
1103 x86_pmu
.lbr_sel_mask
= LBR_SEL_MASK
;
1104 x86_pmu
.lbr_sel_map
= hsw_lbr_sel_map
;
1106 if (lbr_from_signext_quirk_needed())
1107 static_branch_enable(&lbr_from_quirk_key
);
1111 __init
void intel_pmu_lbr_init_skl(void)
1113 x86_pmu
.lbr_nr
= 32;
1114 x86_pmu
.lbr_tos
= MSR_LBR_TOS
;
1115 x86_pmu
.lbr_from
= MSR_LBR_NHM_FROM
;
1116 x86_pmu
.lbr_to
= MSR_LBR_NHM_TO
;
1118 x86_pmu
.lbr_sel_mask
= LBR_SEL_MASK
;
1119 x86_pmu
.lbr_sel_map
= hsw_lbr_sel_map
;
1122 * SW branch filter usage:
1123 * - support syscall, sysret capture.
1124 * That requires LBR_FAR but that means far
1125 * jmp need to be filtered out
1130 void __init
intel_pmu_lbr_init_atom(void)
1133 * only models starting at stepping 10 seems
1134 * to have an operational LBR which can freeze
1137 if (boot_cpu_data
.x86_model
== 28
1138 && boot_cpu_data
.x86_mask
< 10) {
1139 pr_cont("LBR disabled due to erratum");
1144 x86_pmu
.lbr_tos
= MSR_LBR_TOS
;
1145 x86_pmu
.lbr_from
= MSR_LBR_CORE_FROM
;
1146 x86_pmu
.lbr_to
= MSR_LBR_CORE_TO
;
1149 * SW branch filter usage:
1150 * - compensate for lack of HW filter
1155 void __init
intel_pmu_lbr_init_slm(void)
1158 x86_pmu
.lbr_tos
= MSR_LBR_TOS
;
1159 x86_pmu
.lbr_from
= MSR_LBR_CORE_FROM
;
1160 x86_pmu
.lbr_to
= MSR_LBR_CORE_TO
;
1162 x86_pmu
.lbr_sel_mask
= LBR_SEL_MASK
;
1163 x86_pmu
.lbr_sel_map
= nhm_lbr_sel_map
;
1166 * SW branch filter usage:
1167 * - compensate for lack of HW filter
1169 pr_cont("8-deep LBR, ");
1172 /* Knights Landing */
1173 void intel_pmu_lbr_init_knl(void)
1176 x86_pmu
.lbr_tos
= MSR_LBR_TOS
;
1177 x86_pmu
.lbr_from
= MSR_LBR_NHM_FROM
;
1178 x86_pmu
.lbr_to
= MSR_LBR_NHM_TO
;
1180 x86_pmu
.lbr_sel_mask
= LBR_SEL_MASK
;
1181 x86_pmu
.lbr_sel_map
= snb_lbr_sel_map
;