2 * Performance events x86 architecture header
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
17 #include <asm/intel_ds.h>
19 /* To enable MSR tracing please use the generic trace points. */
23 * register -------------------------------
24 * | HT | no HT | HT | no HT |
25 *-----------------------------------------
26 * offcore | core | core | cpu | core |
27 * lbr_sel | core | core | cpu | core |
28 * ld_lat | cpu | core | cpu | core |
29 *-----------------------------------------
31 * Given that there is a small number of shared regs,
32 * we can pre-allocate their slot in the per-cpu
33 * per-core reg tables.
36 EXTRA_REG_NONE
= -1, /* not used */
38 EXTRA_REG_RSP_0
= 0, /* offcore_response_0 */
39 EXTRA_REG_RSP_1
= 1, /* offcore_response_1 */
40 EXTRA_REG_LBR
= 2, /* lbr_select */
41 EXTRA_REG_LDLAT
= 3, /* ld_lat_threshold */
42 EXTRA_REG_FE
= 4, /* fe_* */
44 EXTRA_REG_MAX
/* number of entries needed */
47 struct event_constraint
{
49 unsigned long idxmsk
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
59 * struct hw_perf_event.flags flags
61 #define PERF_X86_EVENT_PEBS_LDLAT 0x0001 /* ld+ldlat data address sampling */
62 #define PERF_X86_EVENT_PEBS_ST 0x0002 /* st data address sampling */
63 #define PERF_X86_EVENT_PEBS_ST_HSW 0x0004 /* haswell style datala, store */
64 #define PERF_X86_EVENT_COMMITTED 0x0008 /* event passed commit_txn */
65 #define PERF_X86_EVENT_PEBS_LD_HSW 0x0010 /* haswell style datala, load */
66 #define PERF_X86_EVENT_PEBS_NA_HSW 0x0020 /* haswell style datala, unknown */
67 #define PERF_X86_EVENT_EXCL 0x0040 /* HT exclusivity on counter */
68 #define PERF_X86_EVENT_DYNAMIC 0x0080 /* dynamic alloc'd constraint */
69 #define PERF_X86_EVENT_RDPMC_ALLOWED 0x0100 /* grant rdpmc permission */
70 #define PERF_X86_EVENT_EXCL_ACCT 0x0200 /* accounted EXCL event */
71 #define PERF_X86_EVENT_AUTO_RELOAD 0x0400 /* use PEBS auto-reload */
72 #define PERF_X86_EVENT_FREERUNNING 0x0800 /* use freerunning PEBS */
76 int nb_id
; /* NorthBridge id */
77 int refcnt
; /* reference count */
78 struct perf_event
*owners
[X86_PMC_IDX_MAX
];
79 struct event_constraint event_constraints
[X86_PMC_IDX_MAX
];
82 #define PEBS_COUNTER_MASK ((1ULL << MAX_PEBS_EVENTS) - 1)
85 * Flags PEBS can handle without an PMI.
87 * TID can only be handled by flushing at context switch.
88 * REGS_USER can be handled for events limited to ring 3.
91 #define PEBS_FREERUNNING_FLAGS \
92 (PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | \
93 PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \
94 PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \
95 PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR | \
96 PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER)
108 PERF_REG_X86_FLAGS | \
119 * Per register state.
122 raw_spinlock_t lock
; /* per-core: protect structure */
123 u64 config
; /* extra MSR config */
124 u64 reg
; /* extra MSR number */
125 atomic_t ref
; /* reference count */
131 * Used to coordinate shared registers between HT threads or
132 * among events on a single PMU.
134 struct intel_shared_regs
{
135 struct er_account regs
[EXTRA_REG_MAX
];
136 int refcnt
; /* per-core: #HT threads */
137 unsigned core_id
; /* per-core: core id */
140 enum intel_excl_state_type
{
141 INTEL_EXCL_UNUSED
= 0, /* counter is unused */
142 INTEL_EXCL_SHARED
= 1, /* counter can be used by both threads */
143 INTEL_EXCL_EXCLUSIVE
= 2, /* counter can be used by one thread only */
146 struct intel_excl_states
{
147 enum intel_excl_state_type state
[X86_PMC_IDX_MAX
];
148 bool sched_started
; /* true if scheduling has started */
151 struct intel_excl_cntrs
{
154 struct intel_excl_states states
[2];
157 u16 has_exclusive
[2];
158 u32 exclusive_present
;
161 int refcnt
; /* per-core: #HT threads */
162 unsigned core_id
; /* per-core: core id */
165 #define MAX_LBR_ENTRIES 32
168 X86_PERF_KFREE_SHARED
= 0,
169 X86_PERF_KFREE_EXCL
= 1,
173 struct cpu_hw_events
{
175 * Generic x86 PMC bits
177 struct perf_event
*events
[X86_PMC_IDX_MAX
]; /* in counter order */
178 unsigned long active_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
179 unsigned long running
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
182 int n_events
; /* the # of events in the below arrays */
183 int n_added
; /* the # last events in the below arrays;
184 they've never been enabled yet */
185 int n_txn
; /* the # last events in the below arrays;
186 added in the current transaction */
187 int assign
[X86_PMC_IDX_MAX
]; /* event to counter assignment */
188 u64 tags
[X86_PMC_IDX_MAX
];
190 struct perf_event
*event_list
[X86_PMC_IDX_MAX
]; /* in enabled order */
191 struct event_constraint
*event_constraint
[X86_PMC_IDX_MAX
];
193 int n_excl
; /* the number of exclusive events */
195 unsigned int txn_flags
;
199 * Intel DebugStore bits
201 struct debug_store
*ds
;
212 struct perf_branch_stack lbr_stack
;
213 struct perf_branch_entry lbr_entries
[MAX_LBR_ENTRIES
];
214 struct er_account
*lbr_sel
;
218 * Intel host/guest exclude bits
220 u64 intel_ctrl_guest_mask
;
221 u64 intel_ctrl_host_mask
;
222 struct perf_guest_switch_msr guest_switch_msrs
[X86_PMC_IDX_MAX
];
225 * Intel checkpoint mask
230 * manage shared (per-core, per-cpu) registers
231 * used on Intel NHM/WSM/SNB
233 struct intel_shared_regs
*shared_regs
;
235 * manage exclusive counter access between hyperthread
237 struct event_constraint
*constraint_list
; /* in enable order */
238 struct intel_excl_cntrs
*excl_cntrs
;
239 int excl_thread_id
; /* 0 or 1 */
244 struct amd_nb
*amd_nb
;
245 /* Inverted mask of bits to clear in the perf_ctr ctrl registers */
246 u64 perf_ctr_virt_mask
;
248 void *kfree_on_online
[X86_PERF_KFREE_MAX
];
251 #define __EVENT_CONSTRAINT(c, n, m, w, o, f) {\
252 { .idxmsk64 = (n) }, \
260 #define EVENT_CONSTRAINT(c, n, m) \
261 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0)
263 #define INTEL_EXCLEVT_CONSTRAINT(c, n) \
264 __EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT, HWEIGHT(n),\
265 0, PERF_X86_EVENT_EXCL)
268 * The overlap flag marks event constraints with overlapping counter
269 * masks. This is the case if the counter mask of such an event is not
270 * a subset of any other counter mask of a constraint with an equal or
271 * higher weight, e.g.:
273 * c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0);
274 * c_another1 = EVENT_CONSTRAINT(0, 0x07, 0);
275 * c_another2 = EVENT_CONSTRAINT(0, 0x38, 0);
277 * The event scheduler may not select the correct counter in the first
278 * cycle because it needs to know which subsequent events will be
279 * scheduled. It may fail to schedule the events then. So we set the
280 * overlap flag for such constraints to give the scheduler a hint which
281 * events to select for counter rescheduling.
283 * Care must be taken as the rescheduling algorithm is O(n!) which
284 * will increase scheduling cycles for an over-committed system
285 * dramatically. The number of such EVENT_CONSTRAINT_OVERLAP() macros
286 * and its counter masks must be kept at a minimum.
288 #define EVENT_CONSTRAINT_OVERLAP(c, n, m) \
289 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1, 0)
292 * Constraint on the Event code.
294 #define INTEL_EVENT_CONSTRAINT(c, n) \
295 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
298 * Constraint on the Event code + UMask + fixed-mask
300 * filter mask to validate fixed counter events.
301 * the following filters disqualify for fixed counters:
306 * - in_tx_checkpointed
307 * The other filters are supported by fixed counters.
308 * The any-thread option is supported starting with v3.
310 #define FIXED_EVENT_FLAGS (X86_RAW_EVENT_MASK|HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)
311 #define FIXED_EVENT_CONSTRAINT(c, n) \
312 EVENT_CONSTRAINT(c, (1ULL << (32+n)), FIXED_EVENT_FLAGS)
315 * Constraint on the Event code + UMask
317 #define INTEL_UEVENT_CONSTRAINT(c, n) \
318 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
320 /* Constraint on specific umask bit only + event */
321 #define INTEL_UBIT_EVENT_CONSTRAINT(c, n) \
322 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|(c))
324 /* Like UEVENT_CONSTRAINT, but match flags too */
325 #define INTEL_FLAGS_UEVENT_CONSTRAINT(c, n) \
326 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS)
328 #define INTEL_EXCLUEVT_CONSTRAINT(c, n) \
329 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \
330 HWEIGHT(n), 0, PERF_X86_EVENT_EXCL)
332 #define INTEL_PLD_CONSTRAINT(c, n) \
333 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
334 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LDLAT)
336 #define INTEL_PST_CONSTRAINT(c, n) \
337 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
338 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST)
340 /* Event constraint, but match on all event flags too. */
341 #define INTEL_FLAGS_EVENT_CONSTRAINT(c, n) \
342 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS)
344 /* Check only flags, but allow all event/umask */
345 #define INTEL_ALL_EVENT_CONSTRAINT(code, n) \
346 EVENT_CONSTRAINT(code, n, X86_ALL_EVENT_FLAGS)
348 /* Check flags and event code, and set the HSW store flag */
349 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_ST(code, n) \
350 __EVENT_CONSTRAINT(code, n, \
351 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
352 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW)
354 /* Check flags and event code, and set the HSW load flag */
355 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(code, n) \
356 __EVENT_CONSTRAINT(code, n, \
357 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
358 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
360 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(code, n) \
361 __EVENT_CONSTRAINT(code, n, \
362 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
364 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL)
366 /* Check flags and event code/umask, and set the HSW store flag */
367 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(code, n) \
368 __EVENT_CONSTRAINT(code, n, \
369 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
370 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW)
372 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(code, n) \
373 __EVENT_CONSTRAINT(code, n, \
374 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
376 PERF_X86_EVENT_PEBS_ST_HSW|PERF_X86_EVENT_EXCL)
378 /* Check flags and event code/umask, and set the HSW load flag */
379 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(code, n) \
380 __EVENT_CONSTRAINT(code, n, \
381 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
382 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
384 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(code, n) \
385 __EVENT_CONSTRAINT(code, n, \
386 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
388 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL)
390 /* Check flags and event code/umask, and set the HSW N/A flag */
391 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(code, n) \
392 __EVENT_CONSTRAINT(code, n, \
393 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
394 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_NA_HSW)
398 * We define the end marker as having a weight of -1
399 * to enable blacklisting of events using a counter bitmask
400 * of zero and thus a weight of zero.
401 * The end marker has a weight that cannot possibly be
402 * obtained from counting the bits in the bitmask.
404 #define EVENT_CONSTRAINT_END { .weight = -1 }
407 * Check for end marker with weight == -1
409 #define for_each_event_constraint(e, c) \
410 for ((e) = (c); (e)->weight != -1; (e)++)
413 * Extra registers for specific events.
415 * Some events need large masks and require external MSRs.
416 * Those extra MSRs end up being shared for all events on
417 * a PMU and sometimes between PMU of sibling HT threads.
418 * In either case, the kernel needs to handle conflicting
419 * accesses to those extra, shared, regs. The data structure
420 * to manage those registers is stored in cpu_hw_event.
427 int idx
; /* per_xxx->regs[] reg index */
428 bool extra_msr_access
;
431 #define EVENT_EXTRA_REG(e, ms, m, vm, i) { \
434 .config_mask = (m), \
435 .valid_mask = (vm), \
436 .idx = EXTRA_REG_##i, \
437 .extra_msr_access = true, \
440 #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \
441 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx)
443 #define INTEL_UEVENT_EXTRA_REG(event, msr, vm, idx) \
444 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT | \
445 ARCH_PERFMON_EVENTSEL_UMASK, vm, idx)
447 #define INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(c) \
448 INTEL_UEVENT_EXTRA_REG(c, \
449 MSR_PEBS_LD_LAT_THRESHOLD, \
453 #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0)
455 union perf_capabilities
{
463 * PMU supports separate counter range for writing
466 u64 full_width_write
:1;
471 struct x86_pmu_quirk
{
472 struct x86_pmu_quirk
*next
;
476 union x86_pmu_config
{
497 #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value
500 x86_lbr_exclusive_lbr
,
501 x86_lbr_exclusive_bts
,
502 x86_lbr_exclusive_pt
,
503 x86_lbr_exclusive_max
,
507 * struct x86_pmu - generic x86 pmu
511 * Generic x86 PMC bits
515 int (*handle_irq
)(struct pt_regs
*);
516 void (*disable_all
)(void);
517 void (*enable_all
)(int added
);
518 void (*enable
)(struct perf_event
*);
519 void (*disable
)(struct perf_event
*);
520 void (*add
)(struct perf_event
*);
521 void (*del
)(struct perf_event
*);
522 int (*hw_config
)(struct perf_event
*event
);
523 int (*schedule_events
)(struct cpu_hw_events
*cpuc
, int n
, int *assign
);
526 int (*addr_offset
)(int index
, bool eventsel
);
527 int (*rdpmc_index
)(int index
);
528 u64 (*event_map
)(int);
531 int num_counters_fixed
;
535 unsigned long events_maskl
;
536 unsigned long events_mask
[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT
)];
541 struct event_constraint
*
542 (*get_event_constraints
)(struct cpu_hw_events
*cpuc
,
544 struct perf_event
*event
);
546 void (*put_event_constraints
)(struct cpu_hw_events
*cpuc
,
547 struct perf_event
*event
);
549 void (*start_scheduling
)(struct cpu_hw_events
*cpuc
);
551 void (*commit_scheduling
)(struct cpu_hw_events
*cpuc
, int idx
, int cntr
);
553 void (*stop_scheduling
)(struct cpu_hw_events
*cpuc
);
555 struct event_constraint
*event_constraints
;
556 struct x86_pmu_quirk
*quirks
;
557 int perfctr_second_write
;
559 unsigned (*limit_period
)(struct perf_event
*event
, unsigned l
);
564 int attr_rdpmc_broken
;
566 struct attribute
**format_attrs
;
567 struct attribute
**event_attrs
;
568 struct attribute
**caps_attrs
;
570 ssize_t (*events_sysfs_show
)(char *page
, u64 config
);
571 struct attribute
**cpu_events
;
573 unsigned long attr_freeze_on_smi
;
574 struct attribute
**attrs
;
579 int (*cpu_prepare
)(int cpu
);
580 void (*cpu_starting
)(int cpu
);
581 void (*cpu_dying
)(int cpu
);
582 void (*cpu_dead
)(int cpu
);
584 void (*check_microcode
)(void);
585 void (*sched_task
)(struct perf_event_context
*ctx
,
589 * Intel Arch Perfmon v2+
592 union perf_capabilities intel_cap
;
595 * Intel DebugStore bits
604 int pebs_record_size
;
605 int pebs_buffer_size
;
606 void (*drain_pebs
)(struct pt_regs
*regs
);
607 struct event_constraint
*pebs_constraints
;
608 void (*pebs_aliases
)(struct perf_event
*event
);
610 unsigned long free_running_flags
;
615 unsigned long lbr_tos
, lbr_from
, lbr_to
; /* MSR base regs */
616 int lbr_nr
; /* hardware stack size */
617 u64 lbr_sel_mask
; /* LBR_SELECT valid bits */
618 const int *lbr_sel_map
; /* lbr_select mappings */
619 bool lbr_double_abort
; /* duplicated lbr aborts */
620 bool lbr_pt_coexist
; /* (LBR|BTS) may coexist with PT */
623 * Intel PT/LBR/BTS are exclusive
625 atomic_t lbr_exclusive
[x86_lbr_exclusive_max
];
630 unsigned int amd_nb_constraints
: 1;
633 * Extra registers for events
635 struct extra_reg
*extra_regs
;
639 * Intel host/guest support (KVM)
641 struct perf_guest_switch_msr
*(*guest_get_msrs
)(int *nr
);
644 struct x86_perf_task_context
{
645 u64 lbr_from
[MAX_LBR_ENTRIES
];
646 u64 lbr_to
[MAX_LBR_ENTRIES
];
647 u64 lbr_info
[MAX_LBR_ENTRIES
];
649 int lbr_callstack_users
;
653 #define x86_add_quirk(func_) \
655 static struct x86_pmu_quirk __quirk __initdata = { \
658 __quirk.next = x86_pmu.quirks; \
659 x86_pmu.quirks = &__quirk; \
665 #define PMU_FL_NO_HT_SHARING 0x1 /* no hyper-threading resource sharing */
666 #define PMU_FL_HAS_RSP_1 0x2 /* has 2 equivalent offcore_rsp regs */
667 #define PMU_FL_EXCL_CNTRS 0x4 /* has exclusive counter requirements */
668 #define PMU_FL_EXCL_ENABLED 0x8 /* exclusive counter active */
670 #define EVENT_VAR(_id) event_attr_##_id
671 #define EVENT_PTR(_id) &event_attr_##_id.attr.attr
673 #define EVENT_ATTR(_name, _id) \
674 static struct perf_pmu_events_attr EVENT_VAR(_id) = { \
675 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \
676 .id = PERF_COUNT_HW_##_id, \
680 #define EVENT_ATTR_STR(_name, v, str) \
681 static struct perf_pmu_events_attr event_attr_##v = { \
682 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \
687 #define EVENT_ATTR_STR_HT(_name, v, noht, ht) \
688 static struct perf_pmu_events_ht_attr event_attr_##v = { \
689 .attr = __ATTR(_name, 0444, events_ht_sysfs_show, NULL),\
691 .event_str_noht = noht, \
692 .event_str_ht = ht, \
695 extern struct x86_pmu x86_pmu __read_mostly
;
697 static inline bool x86_pmu_has_lbr_callstack(void)
699 return x86_pmu
.lbr_sel_map
&&
700 x86_pmu
.lbr_sel_map
[PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT
] > 0;
703 DECLARE_PER_CPU(struct cpu_hw_events
, cpu_hw_events
);
705 int x86_perf_event_set_period(struct perf_event
*event
);
708 * Generalized hw caching related hw_event table, filled
709 * in on a per model basis. A value of 0 means
710 * 'not supported', -1 means 'hw_event makes no sense on
711 * this CPU', any other value means the raw hw_event
715 #define C(x) PERF_COUNT_HW_CACHE_##x
717 extern u64 __read_mostly hw_cache_event_ids
718 [PERF_COUNT_HW_CACHE_MAX
]
719 [PERF_COUNT_HW_CACHE_OP_MAX
]
720 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
721 extern u64 __read_mostly hw_cache_extra_regs
722 [PERF_COUNT_HW_CACHE_MAX
]
723 [PERF_COUNT_HW_CACHE_OP_MAX
]
724 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
726 u64
x86_perf_event_update(struct perf_event
*event
);
728 static inline unsigned int x86_pmu_config_addr(int index
)
730 return x86_pmu
.eventsel
+ (x86_pmu
.addr_offset
?
731 x86_pmu
.addr_offset(index
, true) : index
);
734 static inline unsigned int x86_pmu_event_addr(int index
)
736 return x86_pmu
.perfctr
+ (x86_pmu
.addr_offset
?
737 x86_pmu
.addr_offset(index
, false) : index
);
740 static inline int x86_pmu_rdpmc_index(int index
)
742 return x86_pmu
.rdpmc_index
? x86_pmu
.rdpmc_index(index
) : index
;
745 int x86_add_exclusive(unsigned int what
);
747 void x86_del_exclusive(unsigned int what
);
749 int x86_reserve_hardware(void);
751 void x86_release_hardware(void);
753 int x86_pmu_max_precise(void);
755 void hw_perf_lbr_event_destroy(struct perf_event
*event
);
757 int x86_setup_perfctr(struct perf_event
*event
);
759 int x86_pmu_hw_config(struct perf_event
*event
);
761 void x86_pmu_disable_all(void);
763 static inline void __x86_pmu_enable_event(struct hw_perf_event
*hwc
,
766 u64 disable_mask
= __this_cpu_read(cpu_hw_events
.perf_ctr_virt_mask
);
768 if (hwc
->extra_reg
.reg
)
769 wrmsrl(hwc
->extra_reg
.reg
, hwc
->extra_reg
.config
);
770 wrmsrl(hwc
->config_base
, (hwc
->config
| enable_mask
) & ~disable_mask
);
773 void x86_pmu_enable_all(int added
);
775 int perf_assign_events(struct event_constraint
**constraints
, int n
,
776 int wmin
, int wmax
, int gpmax
, int *assign
);
777 int x86_schedule_events(struct cpu_hw_events
*cpuc
, int n
, int *assign
);
779 void x86_pmu_stop(struct perf_event
*event
, int flags
);
781 static inline void x86_pmu_disable_event(struct perf_event
*event
)
783 struct hw_perf_event
*hwc
= &event
->hw
;
785 wrmsrl(hwc
->config_base
, hwc
->config
);
788 void x86_pmu_enable_event(struct perf_event
*event
);
790 int x86_pmu_handle_irq(struct pt_regs
*regs
);
792 extern struct event_constraint emptyconstraint
;
794 extern struct event_constraint unconstrained
;
796 static inline bool kernel_ip(unsigned long ip
)
799 return ip
> PAGE_OFFSET
;
806 * Not all PMUs provide the right context information to place the reported IP
807 * into full context. Specifically segment registers are typically not
810 * Assuming the address is a linear address (it is for IBS), we fake the CS and
811 * vm86 mode using the known zero-based code segment and 'fix up' the registers
814 * Intel PEBS/LBR appear to typically provide the effective address, nothing
815 * much we can do about that but pray and treat it like a linear address.
817 static inline void set_linear_ip(struct pt_regs
*regs
, unsigned long ip
)
819 regs
->cs
= kernel_ip(ip
) ? __KERNEL_CS
: __USER_CS
;
820 if (regs
->flags
& X86_VM_MASK
)
821 regs
->flags
^= (PERF_EFLAGS_VM
| X86_VM_MASK
);
825 ssize_t
x86_event_sysfs_show(char *page
, u64 config
, u64 event
);
826 ssize_t
intel_event_sysfs_show(char *page
, u64 config
);
828 struct attribute
**merge_attr(struct attribute
**a
, struct attribute
**b
);
830 ssize_t
events_sysfs_show(struct device
*dev
, struct device_attribute
*attr
,
832 ssize_t
events_ht_sysfs_show(struct device
*dev
, struct device_attribute
*attr
,
835 #ifdef CONFIG_CPU_SUP_AMD
837 int amd_pmu_init(void);
839 #else /* CONFIG_CPU_SUP_AMD */
841 static inline int amd_pmu_init(void)
846 #endif /* CONFIG_CPU_SUP_AMD */
848 #ifdef CONFIG_CPU_SUP_INTEL
850 static inline bool intel_pmu_has_bts(struct perf_event
*event
)
852 if (event
->attr
.config
== PERF_COUNT_HW_BRANCH_INSTRUCTIONS
&&
853 !event
->attr
.freq
&& event
->hw
.sample_period
== 1)
859 int intel_pmu_save_and_restart(struct perf_event
*event
);
861 struct event_constraint
*
862 x86_get_event_constraints(struct cpu_hw_events
*cpuc
, int idx
,
863 struct perf_event
*event
);
865 struct intel_shared_regs
*allocate_shared_regs(int cpu
);
867 int intel_pmu_init(void);
869 void init_debug_store_on_cpu(int cpu
);
871 void fini_debug_store_on_cpu(int cpu
);
873 void release_ds_buffers(void);
875 void reserve_ds_buffers(void);
877 extern struct event_constraint bts_constraint
;
879 void intel_pmu_enable_bts(u64 config
);
881 void intel_pmu_disable_bts(void);
883 int intel_pmu_drain_bts_buffer(void);
885 extern struct event_constraint intel_core2_pebs_event_constraints
[];
887 extern struct event_constraint intel_atom_pebs_event_constraints
[];
889 extern struct event_constraint intel_slm_pebs_event_constraints
[];
891 extern struct event_constraint intel_glm_pebs_event_constraints
[];
893 extern struct event_constraint intel_glp_pebs_event_constraints
[];
895 extern struct event_constraint intel_nehalem_pebs_event_constraints
[];
897 extern struct event_constraint intel_westmere_pebs_event_constraints
[];
899 extern struct event_constraint intel_snb_pebs_event_constraints
[];
901 extern struct event_constraint intel_ivb_pebs_event_constraints
[];
903 extern struct event_constraint intel_hsw_pebs_event_constraints
[];
905 extern struct event_constraint intel_bdw_pebs_event_constraints
[];
907 extern struct event_constraint intel_skl_pebs_event_constraints
[];
909 struct event_constraint
*intel_pebs_constraints(struct perf_event
*event
);
911 void intel_pmu_pebs_add(struct perf_event
*event
);
913 void intel_pmu_pebs_del(struct perf_event
*event
);
915 void intel_pmu_pebs_enable(struct perf_event
*event
);
917 void intel_pmu_pebs_disable(struct perf_event
*event
);
919 void intel_pmu_pebs_enable_all(void);
921 void intel_pmu_pebs_disable_all(void);
923 void intel_pmu_pebs_sched_task(struct perf_event_context
*ctx
, bool sched_in
);
925 void intel_ds_init(void);
927 void intel_pmu_lbr_sched_task(struct perf_event_context
*ctx
, bool sched_in
);
929 u64
lbr_from_signext_quirk_wr(u64 val
);
931 void intel_pmu_lbr_reset(void);
933 void intel_pmu_lbr_add(struct perf_event
*event
);
935 void intel_pmu_lbr_del(struct perf_event
*event
);
937 void intel_pmu_lbr_enable_all(bool pmi
);
939 void intel_pmu_lbr_disable_all(void);
941 void intel_pmu_lbr_read(void);
943 void intel_pmu_lbr_init_core(void);
945 void intel_pmu_lbr_init_nhm(void);
947 void intel_pmu_lbr_init_atom(void);
949 void intel_pmu_lbr_init_slm(void);
951 void intel_pmu_lbr_init_snb(void);
953 void intel_pmu_lbr_init_hsw(void);
955 void intel_pmu_lbr_init_skl(void);
957 void intel_pmu_lbr_init_knl(void);
959 void intel_pmu_pebs_data_source_nhm(void);
961 void intel_pmu_pebs_data_source_skl(bool pmem
);
963 int intel_pmu_setup_lbr_filter(struct perf_event
*event
);
965 void intel_pt_interrupt(void);
967 int intel_bts_interrupt(void);
969 void intel_bts_enable_local(void);
971 void intel_bts_disable_local(void);
973 int p4_pmu_init(void);
975 int p6_pmu_init(void);
977 int knc_pmu_init(void);
979 static inline int is_ht_workaround_enabled(void)
981 return !!(x86_pmu
.flags
& PMU_FL_EXCL_ENABLED
);
984 #else /* CONFIG_CPU_SUP_INTEL */
986 static inline void reserve_ds_buffers(void)
990 static inline void release_ds_buffers(void)
994 static inline int intel_pmu_init(void)
999 static inline struct intel_shared_regs
*allocate_shared_regs(int cpu
)
1004 static inline int is_ht_workaround_enabled(void)
1008 #endif /* CONFIG_CPU_SUP_INTEL */