arch/x86/include/asm/amd_iommu_types.h

   1 /*
   2  * Copyright (C) 2007-2009 Advanced Micro Devices, Inc.
   3  * Author: Joerg Roedel <joerg.roedel@amd.com>
   4  *         Leo Duran <leo.duran@amd.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  18  */
  19
  20 #ifndef _ASM_X86_AMD_IOMMU_TYPES_H
  21 #define _ASM_X86_AMD_IOMMU_TYPES_H
  22
  23 #include <linux/types.h>
  24 #include <linux/list.h>
  25 #include <linux/spinlock.h>
  26
  27 /*
  28  * Maximum number of IOMMUs supported
  29  */
  30 #define MAX_IOMMUS      32
  31
  32 /*
  33  * some size calculation constants
  34  */
  35 #define DEV_TABLE_ENTRY_SIZE            32
  36 #define ALIAS_TABLE_ENTRY_SIZE          2
  37 #define RLOOKUP_TABLE_ENTRY_SIZE        (sizeof(void *))
  38
  39 /* Length of the MMIO region for the AMD IOMMU */
  40 #define MMIO_REGION_LENGTH       0x4000
  41
  42 /* Capability offsets used by the driver */
  43 #define MMIO_CAP_HDR_OFFSET     0x00
  44 #define MMIO_RANGE_OFFSET       0x0c
  45 #define MMIO_MISC_OFFSET        0x10
  46
  47 /* Masks, shifts and macros to parse the device range capability */
  48 #define MMIO_RANGE_LD_MASK      0xff000000
  49 #define MMIO_RANGE_FD_MASK      0x00ff0000
  50 #define MMIO_RANGE_BUS_MASK     0x0000ff00
  51 #define MMIO_RANGE_LD_SHIFT     24
  52 #define MMIO_RANGE_FD_SHIFT     16
  53 #define MMIO_RANGE_BUS_SHIFT    8
  54 #define MMIO_GET_LD(x)  (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT)
  55 #define MMIO_GET_FD(x)  (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT)
  56 #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT)
  57 #define MMIO_MSI_NUM(x) ((x) & 0x1f)
  58
  59 /* Flag masks for the AMD IOMMU exclusion range */
  60 #define MMIO_EXCL_ENABLE_MASK 0x01ULL
  61 #define MMIO_EXCL_ALLOW_MASK  0x02ULL
  62
  63 /* Used offsets into the MMIO space */
  64 #define MMIO_DEV_TABLE_OFFSET   0x0000
  65 #define MMIO_CMD_BUF_OFFSET     0x0008
  66 #define MMIO_EVT_BUF_OFFSET     0x0010
  67 #define MMIO_CONTROL_OFFSET     0x0018
  68 #define MMIO_EXCL_BASE_OFFSET   0x0020
  69 #define MMIO_EXCL_LIMIT_OFFSET  0x0028
  70 #define MMIO_CMD_HEAD_OFFSET    0x2000
  71 #define MMIO_CMD_TAIL_OFFSET    0x2008
  72 #define MMIO_EVT_HEAD_OFFSET    0x2010
  73 #define MMIO_EVT_TAIL_OFFSET    0x2018
  74 #define MMIO_STATUS_OFFSET      0x2020
  75
  76 /* MMIO status bits */
  77 #define MMIO_STATUS_COM_WAIT_INT_MASK   0x04
  78
  79 /* event logging constants */
  80 #define EVENT_ENTRY_SIZE        0x10
  81 #define EVENT_TYPE_SHIFT        28
  82 #define EVENT_TYPE_MASK         0xf
  83 #define EVENT_TYPE_ILL_DEV      0x1
  84 #define EVENT_TYPE_IO_FAULT     0x2
  85 #define EVENT_TYPE_DEV_TAB_ERR  0x3
  86 #define EVENT_TYPE_PAGE_TAB_ERR 0x4
  87 #define EVENT_TYPE_ILL_CMD      0x5
  88 #define EVENT_TYPE_CMD_HARD_ERR 0x6
  89 #define EVENT_TYPE_IOTLB_INV_TO 0x7
  90 #define EVENT_TYPE_INV_DEV_REQ  0x8
  91 #define EVENT_DEVID_MASK        0xffff
  92 #define EVENT_DEVID_SHIFT       0
  93 #define EVENT_DOMID_MASK        0xffff
  94 #define EVENT_DOMID_SHIFT       0
  95 #define EVENT_FLAGS_MASK        0xfff
  96 #define EVENT_FLAGS_SHIFT       0x10
  97
  98 /* feature control bits */
  99 #define CONTROL_IOMMU_EN        0x00ULL
 100 #define CONTROL_HT_TUN_EN       0x01ULL
 101 #define CONTROL_EVT_LOG_EN      0x02ULL
 102 #define CONTROL_EVT_INT_EN      0x03ULL
 103 #define CONTROL_COMWAIT_EN      0x04ULL
 104 #define CONTROL_PASSPW_EN       0x08ULL
 105 #define CONTROL_RESPASSPW_EN    0x09ULL
 106 #define CONTROL_COHERENT_EN     0x0aULL
 107 #define CONTROL_ISOC_EN         0x0bULL
 108 #define CONTROL_CMDBUF_EN       0x0cULL
 109 #define CONTROL_PPFLOG_EN       0x0dULL
 110 #define CONTROL_PPFINT_EN       0x0eULL
 111
 112 /* command specific defines */
 113 #define CMD_COMPL_WAIT          0x01
 114 #define CMD_INV_DEV_ENTRY       0x02
 115 #define CMD_INV_IOMMU_PAGES     0x03
 116
 117 #define CMD_COMPL_WAIT_STORE_MASK       0x01
 118 #define CMD_COMPL_WAIT_INT_MASK         0x02
 119 #define CMD_INV_IOMMU_PAGES_SIZE_MASK   0x01
 120 #define CMD_INV_IOMMU_PAGES_PDE_MASK    0x02
 121
 122 #define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL
 123
 124 /* macros and definitions for device table entries */
 125 #define DEV_ENTRY_VALID         0x00
 126 #define DEV_ENTRY_TRANSLATION   0x01
 127 #define DEV_ENTRY_IR            0x3d
 128 #define DEV_ENTRY_IW            0x3e
 129 #define DEV_ENTRY_NO_PAGE_FAULT 0x62
 130 #define DEV_ENTRY_EX            0x67
 131 #define DEV_ENTRY_SYSMGT1       0x68
 132 #define DEV_ENTRY_SYSMGT2       0x69
 133 #define DEV_ENTRY_INIT_PASS     0xb8
 134 #define DEV_ENTRY_EINT_PASS     0xb9
 135 #define DEV_ENTRY_NMI_PASS      0xba
 136 #define DEV_ENTRY_LINT0_PASS    0xbe
 137 #define DEV_ENTRY_LINT1_PASS    0xbf
 138 #define DEV_ENTRY_MODE_MASK     0x07
 139 #define DEV_ENTRY_MODE_SHIFT    0x09
 140
 141 /* constants to configure the command buffer */
 142 #define CMD_BUFFER_SIZE    8192
 143 #define CMD_BUFFER_ENTRIES 512
 144 #define MMIO_CMD_SIZE_SHIFT 56
 145 #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT)
 146
 147 /* constants for event buffer handling */
 148 #define EVT_BUFFER_SIZE         8192 /* 512 entries */
 149 #define EVT_LEN_MASK            (0x9ULL << 56)
 150
 151 #define PAGE_MODE_NONE    0x00
 152 #define PAGE_MODE_1_LEVEL 0x01
 153 #define PAGE_MODE_2_LEVEL 0x02
 154 #define PAGE_MODE_3_LEVEL 0x03
 155 #define PAGE_MODE_4_LEVEL 0x04
 156 #define PAGE_MODE_5_LEVEL 0x05
 157 #define PAGE_MODE_6_LEVEL 0x06
 158
 159 #define PM_LEVEL_SHIFT(x)       (12 + ((x) * 9))
 160 #define PM_LEVEL_SIZE(x)        (((x) < 6) ? \
 161                                   ((1ULL << PM_LEVEL_SHIFT((x))) - 1): \
 162                                    (0xffffffffffffffffULL))
 163 #define PM_LEVEL_INDEX(x, a)    (((a) >> PM_LEVEL_SHIFT((x))) & 0x1ffULL)
 164 #define PM_LEVEL_ENC(x)         (((x) << 9) & 0xe00ULL)
 165 #define PM_LEVEL_PDE(x, a)      ((a) | PM_LEVEL_ENC((x)) | \
 166                                  IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW)
 167 #define PM_PTE_LEVEL(pte)       (((pte) >> 9) & 0x7ULL)
 168
 169 #define PM_MAP_4k               0
 170 #define PM_ADDR_MASK            0x000ffffffffff000ULL
 171 #define PM_MAP_MASK(lvl)        (PM_ADDR_MASK & \
 172                                 (~((1ULL << (12 + ((lvl) * 9))) - 1)))
 173 #define PM_ALIGNED(lvl, addr)   ((PM_MAP_MASK(lvl) & (addr)) == (addr))
 174
 175 #define IOMMU_PTE_P  (1ULL << 0)
 176 #define IOMMU_PTE_TV (1ULL << 1)
 177 #define IOMMU_PTE_U  (1ULL << 59)
 178 #define IOMMU_PTE_FC (1ULL << 60)
 179 #define IOMMU_PTE_IR (1ULL << 61)
 180 #define IOMMU_PTE_IW (1ULL << 62)
 181
 182 #define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL)
 183 #define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_P)
 184 #define IOMMU_PTE_PAGE(pte) (phys_to_virt((pte) & IOMMU_PAGE_MASK))
 185 #define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07)
 186
 187 #define IOMMU_PROT_MASK 0x03
 188 #define IOMMU_PROT_IR 0x01
 189 #define IOMMU_PROT_IW 0x02
 190
 191 /* IOMMU capabilities */
 192 #define IOMMU_CAP_IOTLB   24
 193 #define IOMMU_CAP_NPCACHE 26
 194
 195 #define MAX_DOMAIN_ID 65536
 196
 197 /* FIXME: move this macro to <linux/pci.h> */
 198 #define PCI_BUS(x) (((x) >> 8) & 0xff)
 199
 200 /* Protection domain flags */
 201 #define PD_DMA_OPS_MASK         (1UL << 0) /* domain used for dma_ops */
 202 #define PD_DEFAULT_MASK         (1UL << 1) /* domain is a default dma_ops
 203                                               domain for an IOMMU */
 204 #define PD_PASSTHROUGH_MASK     (1UL << 2) /* domain has no page
 205                                               translation */
 206
 207 extern bool amd_iommu_dump;
 208 #define DUMP_printk(format, arg...)                                     \
 209         do {                                                            \
 210                 if (amd_iommu_dump)                                             \
 211                         printk(KERN_INFO "AMD-Vi: " format, ## arg);    \
 212         } while(0);
 213
 214 /* global flag if IOMMUs cache non-present entries */
 215 extern bool amd_iommu_np_cache;
 216
 217 /*
 218  * Make iterating over all IOMMUs easier
 219  */
 220 #define for_each_iommu(iommu) \
 221         list_for_each_entry((iommu), &amd_iommu_list, list)
 222 #define for_each_iommu_safe(iommu, next) \
 223         list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list)
 224
 225 #define APERTURE_RANGE_SHIFT    27      /* 128 MB */
 226 #define APERTURE_RANGE_SIZE     (1ULL << APERTURE_RANGE_SHIFT)
 227 #define APERTURE_RANGE_PAGES    (APERTURE_RANGE_SIZE >> PAGE_SHIFT)
 228 #define APERTURE_MAX_RANGES     32      /* allows 4GB of DMA address space */
 229 #define APERTURE_RANGE_INDEX(a) ((a) >> APERTURE_RANGE_SHIFT)
 230 #define APERTURE_PAGE_INDEX(a)  (((a) >> 21) & 0x3fULL)
 231
 232 /*
 233  * This structure contains generic data for  IOMMU protection domains
 234  * independent of their use.
 235  */
 236 struct protection_domain {
 237         struct list_head list;  /* for list of all protection domains */
 238         struct list_head dev_list; /* List of all devices in this domain */
 239         spinlock_t lock;        /* mostly used to lock the page table*/
 240         u16 id;                 /* the domain id written to the device table */
 241         int mode;               /* paging mode (0-6 levels) */
 242         u64 *pt_root;           /* page table root pointer */
 243         unsigned long flags;    /* flags to find out type of domain */
 244         bool updated;           /* complete domain flush required */
 245         unsigned dev_cnt;       /* devices assigned to this domain */
 246         unsigned dev_iommu[MAX_IOMMUS]; /* per-IOMMU reference count */
 247         void *priv;             /* private data */
 248
 249 };
 250
 251 /*
 252  * This struct contains device specific data for the IOMMU
 253  */
 254 struct iommu_dev_data {
 255         struct list_head list;            /* For domain->dev_list */
 256         struct device *dev;               /* Device this data belong to */
 257         struct device *alias;             /* The Alias Device */
 258         struct protection_domain *domain; /* Domain the device is bound to */
 259         atomic_t bind;                    /* Domain attach reverent count */
 260 };
 261
 262 /*
 263  * For dynamic growth the aperture size is split into ranges of 128MB of
 264  * DMA address space each. This struct represents one such range.
 265  */
 266 struct aperture_range {
 267
 268         /* address allocation bitmap */
 269         unsigned long *bitmap;
 270
 271         /*
 272          * Array of PTE pages for the aperture. In this array we save all the
 273          * leaf pages of the domain page table used for the aperture. This way
 274          * we don't need to walk the page table to find a specific PTE. We can
 275          * just calculate its address in constant time.
 276          */
 277         u64 *pte_pages[64];
 278
 279         unsigned long offset;
 280 };
 281
 282 /*
 283  * Data container for a dma_ops specific protection domain
 284  */
 285 struct dma_ops_domain {
 286         struct list_head list;
 287
 288         /* generic protection domain information */
 289         struct protection_domain domain;
 290
 291         /* size of the aperture for the mappings */
 292         unsigned long aperture_size;
 293
 294         /* address we start to search for free addresses */
 295         unsigned long next_address;
 296
 297         /* address space relevant data */
 298         struct aperture_range *aperture[APERTURE_MAX_RANGES];
 299
 300         /* This will be set to true when TLB needs to be flushed */
 301         bool need_flush;
 302
 303         /*
 304          * if this is a preallocated domain, keep the device for which it was
 305          * preallocated in this variable
 306          */
 307         u16 target_dev;
 308 };
 309
 310 /*
 311  * Structure where we save information about one hardware AMD IOMMU in the
 312  * system.
 313  */
 314 struct amd_iommu {
 315         struct list_head list;
 316
 317         /* Index within the IOMMU array */
 318         int index;
 319
 320         /* locks the accesses to the hardware */
 321         spinlock_t lock;
 322
 323         /* Pointer to PCI device of this IOMMU */
 324         struct pci_dev *dev;
 325
 326         /* physical address of MMIO space */
 327         u64 mmio_phys;
 328         /* virtual address of MMIO space */
 329         u8 *mmio_base;
 330
 331         /* capabilities of that IOMMU read from ACPI */
 332         u32 cap;
 333
 334         /*
 335          * Capability pointer. There could be more than one IOMMU per PCI
 336          * device function if there are more than one AMD IOMMU capability
 337          * pointers.
 338          */
 339         u16 cap_ptr;
 340
 341         /* pci domain of this IOMMU */
 342         u16 pci_seg;
 343
 344         /* first device this IOMMU handles. read from PCI */
 345         u16 first_device;
 346         /* last device this IOMMU handles. read from PCI */
 347         u16 last_device;
 348
 349         /* start of exclusion range of that IOMMU */
 350         u64 exclusion_start;
 351         /* length of exclusion range of that IOMMU */
 352         u64 exclusion_length;
 353
 354         /* command buffer virtual address */
 355         u8 *cmd_buf;
 356         /* size of command buffer */
 357         u32 cmd_buf_size;
 358
 359         /* size of event buffer */
 360         u32 evt_buf_size;
 361         /* event buffer virtual address */
 362         u8 *evt_buf;
 363         /* MSI number for event interrupt */
 364         u16 evt_msi_num;
 365
 366         /* true if interrupts for this IOMMU are already enabled */
 367         bool int_enabled;
 368
 369         /* if one, we need to send a completion wait command */
 370         bool need_sync;
 371
 372         /* becomes true if a command buffer reset is running */
 373         bool reset_in_progress;
 374
 375         /* default dma_ops domain for that IOMMU */
 376         struct dma_ops_domain *default_dom;
 377 };
 378
 379 /*
 380  * List with all IOMMUs in the system. This list is not locked because it is
 381  * only written and read at driver initialization or suspend time
 382  */
 383 extern struct list_head amd_iommu_list;
 384
 385 /*
 386  * Array with pointers to each IOMMU struct
 387  * The indices are referenced in the protection domains
 388  */
 389 extern struct amd_iommu *amd_iommus[MAX_IOMMUS];
 390
 391 /* Number of IOMMUs present in the system */
 392 extern int amd_iommus_present;
 393
 394 /*
 395  * Declarations for the global list of all protection domains
 396  */
 397 extern spinlock_t amd_iommu_pd_lock;
 398 extern struct list_head amd_iommu_pd_list;
 399
 400 /*
 401  * Structure defining one entry in the device table
 402  */
 403 struct dev_table_entry {
 404         u32 data[8];
 405 };
 406
 407 /*
 408  * One entry for unity mappings parsed out of the ACPI table.
 409  */
 410 struct unity_map_entry {
 411         struct list_head list;
 412
 413         /* starting device id this entry is used for (including) */
 414         u16 devid_start;
 415         /* end device id this entry is used for (including) */
 416         u16 devid_end;
 417
 418         /* start address to unity map (including) */
 419         u64 address_start;
 420         /* end address to unity map (including) */
 421         u64 address_end;
 422
 423         /* required protection */
 424         int prot;
 425 };
 426
 427 /*
 428  * List of all unity mappings. It is not locked because as runtime it is only
 429  * read. It is created at ACPI table parsing time.
 430  */
 431 extern struct list_head amd_iommu_unity_map;
 432
 433 /*
 434  * Data structures for device handling
 435  */
 436
 437 /*
 438  * Device table used by hardware. Read and write accesses by software are
 439  * locked with the amd_iommu_pd_table lock.
 440  */
 441 extern struct dev_table_entry *amd_iommu_dev_table;
 442
 443 /*
 444  * Alias table to find requestor ids to device ids. Not locked because only
 445  * read on runtime.
 446  */
 447 extern u16 *amd_iommu_alias_table;
 448
 449 /*
 450  * Reverse lookup table to find the IOMMU which translates a specific device.
 451  */
 452 extern struct amd_iommu **amd_iommu_rlookup_table;
 453
 454 /* size of the dma_ops aperture as power of 2 */
 455 extern unsigned amd_iommu_aperture_order;
 456
 457 /* largest PCI device id we expect translation requests for */
 458 extern u16 amd_iommu_last_bdf;
 459
 460 /* allocation bitmap for domain ids */
 461 extern unsigned long *amd_iommu_pd_alloc_bitmap;
 462
 463 /*
 464  * If true, the addresses will be flushed on unmap time, not when
 465  * they are reused
 466  */
 467 extern bool amd_iommu_unmap_flush;
 468
 469 /* takes bus and device/function and returns the device id
 470  * FIXME: should that be in generic PCI code? */
 471 static inline u16 calc_devid(u8 bus, u8 devfn)
 472 {
 473         return (((u16)bus) << 8) | devfn;
 474 }
 475
 476 #ifdef CONFIG_AMD_IOMMU_STATS
 477
 478 struct __iommu_counter {
 479         char *name;
 480         struct dentry *dent;
 481         u64 value;
 482 };
 483
 484 #define DECLARE_STATS_COUNTER(nm) \
 485         static struct __iommu_counter nm = {    \
 486                 .name = #nm,                    \
 487         }
 488
 489 #define INC_STATS_COUNTER(name)         name.value += 1
 490 #define ADD_STATS_COUNTER(name, x)      name.value += (x)
 491 #define SUB_STATS_COUNTER(name, x)      name.value -= (x)
 492
 493 #else /* CONFIG_AMD_IOMMU_STATS */
 494
 495 #define DECLARE_STATS_COUNTER(name)
 496 #define INC_STATS_COUNTER(name)
 497 #define ADD_STATS_COUNTER(name, x)
 498 #define SUB_STATS_COUNTER(name, x)
 499
 500 #endif /* CONFIG_AMD_IOMMU_STATS */
 501
 502 #endif /* _ASM_X86_AMD_IOMMU_TYPES_H */