arch/x86/include/asm/apic.h

   1 #ifndef _ASM_X86_APIC_H
   2 #define _ASM_X86_APIC_H
   3
   4 #include <linux/cpumask.h>
   5 #include <linux/delay.h>
   6 #include <linux/pm.h>
   7
   8 #include <asm/alternative.h>
   9 #include <asm/cpufeature.h>
  10 #include <asm/processor.h>
  11 #include <asm/apicdef.h>
  12 #include <asm/atomic.h>
  13 #include <asm/fixmap.h>
  14 #include <asm/mpspec.h>
  15 #include <asm/system.h>
  16 #include <asm/msr.h>
  17
  18 #define ARCH_APICTIMER_STOPS_ON_C3      1
  19
  20 /*
  21  * Debugging macros
  22  */
  23 #define APIC_QUIET   0
  24 #define APIC_VERBOSE 1
  25 #define APIC_DEBUG   2
  26
  27 /*
  28  * Define the default level of output to be very little
  29  * This can be turned up by using apic=verbose for more
  30  * information and apic=debug for _lots_ of information.
  31  * apic_verbosity is defined in apic.c
  32  */
  33 #define apic_printk(v, s, a...) do {       \
  34                 if ((v) <= apic_verbosity) \
  35                         printk(s, ##a);    \
  36         } while (0)
  37
  38
  39 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
  40 extern void generic_apic_probe(void);
  41 #else
  42 static inline void generic_apic_probe(void)
  43 {
  44 }
  45 #endif
  46
  47 #ifdef CONFIG_X86_LOCAL_APIC
  48
  49 extern unsigned int apic_verbosity;
  50 extern int local_apic_timer_c2_ok;
  51
  52 extern int disable_apic;
  53
  54 #ifdef CONFIG_SMP
  55 extern void __inquire_remote_apic(int apicid);
  56 #else /* CONFIG_SMP */
  57 static inline void __inquire_remote_apic(int apicid)
  58 {
  59 }
  60 #endif /* CONFIG_SMP */
  61
  62 static inline void default_inquire_remote_apic(int apicid)
  63 {
  64         if (apic_verbosity >= APIC_DEBUG)
  65                 __inquire_remote_apic(apicid);
  66 }
  67
  68 /*
  69  * Basic functions accessing APICs.
  70  */
  71 #ifdef CONFIG_PARAVIRT
  72 #include <asm/paravirt.h>
  73 #else
  74 #define setup_boot_clock setup_boot_APIC_clock
  75 #define setup_secondary_clock setup_secondary_APIC_clock
  76 #endif
  77
  78 #ifdef CONFIG_X86_64
  79 extern int is_vsmp_box(void);
  80 #else
  81 static inline int is_vsmp_box(void)
  82 {
  83         return 0;
  84 }
  85 #endif
  86 extern void xapic_wait_icr_idle(void);
  87 extern u32 safe_xapic_wait_icr_idle(void);
  88 extern void xapic_icr_write(u32, u32);
  89 extern int setup_profiling_timer(unsigned int);
  90
  91 static inline void native_apic_mem_write(u32 reg, u32 v)
  92 {
  93         volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
  94
  95         alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP,
  96                        ASM_OUTPUT2("=r" (v), "=m" (*addr)),
  97                        ASM_OUTPUT2("0" (v), "m" (*addr)));
  98 }
  99
 100 static inline u32 native_apic_mem_read(u32 reg)
 101 {
 102         return *((volatile u32 *)(APIC_BASE + reg));
 103 }
 104
 105 extern void native_apic_wait_icr_idle(void);
 106 extern u32 native_safe_apic_wait_icr_idle(void);
 107 extern void native_apic_icr_write(u32 low, u32 id);
 108 extern u64 native_apic_icr_read(void);
 109
 110 extern int x2apic_mode;
 111
 112 #ifdef CONFIG_X86_X2APIC
 113 /*
 114  * Make previous memory operations globally visible before
 115  * sending the IPI through x2apic wrmsr. We need a serializing instruction or
 116  * mfence for this.
 117  */
 118 static inline void x2apic_wrmsr_fence(void)
 119 {
 120         asm volatile("mfence" : : : "memory");
 121 }
 122
 123 static inline void native_apic_msr_write(u32 reg, u32 v)
 124 {
 125         if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
 126             reg == APIC_LVR)
 127                 return;
 128
 129         wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
 130 }
 131
 132 static inline u32 native_apic_msr_read(u32 reg)
 133 {
 134         u32 low, high;
 135
 136         if (reg == APIC_DFR)
 137                 return -1;
 138
 139         rdmsr(APIC_BASE_MSR + (reg >> 4), low, high);
 140         return low;
 141 }
 142
 143 static inline void native_x2apic_wait_icr_idle(void)
 144 {
 145         /* no need to wait for icr idle in x2apic */
 146         return;
 147 }
 148
 149 static inline u32 native_safe_x2apic_wait_icr_idle(void)
 150 {
 151         /* no need to wait for icr idle in x2apic */
 152         return 0;
 153 }
 154
 155 static inline void native_x2apic_icr_write(u32 low, u32 id)
 156 {
 157         wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
 158 }
 159
 160 static inline u64 native_x2apic_icr_read(void)
 161 {
 162         unsigned long val;
 163
 164         rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
 165         return val;
 166 }
 167
 168 extern int x2apic_phys;
 169 extern void check_x2apic(void);
 170 extern void enable_x2apic(void);
 171 extern void x2apic_icr_write(u32 low, u32 id);
 172 static inline int x2apic_enabled(void)
 173 {
 174         int msr, msr2;
 175
 176         if (!cpu_has_x2apic)
 177                 return 0;
 178
 179         rdmsr(MSR_IA32_APICBASE, msr, msr2);
 180         if (msr & X2APIC_ENABLE)
 181                 return 1;
 182         return 0;
 183 }
 184
 185 #define x2apic_supported()      (cpu_has_x2apic)
 186 #else
 187 static inline void check_x2apic(void)
 188 {
 189 }
 190 static inline void enable_x2apic(void)
 191 {
 192 }
 193 static inline int x2apic_enabled(void)
 194 {
 195         return 0;
 196 }
 197
 198 #define x2apic_preenabled 0
 199 #define x2apic_supported()      0
 200 #endif
 201
 202 extern void enable_IR_x2apic(void);
 203
 204 extern int get_physical_broadcast(void);
 205
 206 extern void apic_disable(void);
 207 extern int lapic_get_maxlvt(void);
 208 extern void clear_local_APIC(void);
 209 extern void connect_bsp_APIC(void);
 210 extern void disconnect_bsp_APIC(int virt_wire_setup);
 211 extern void disable_local_APIC(void);
 212 extern void lapic_shutdown(void);
 213 extern int verify_local_APIC(void);
 214 extern void cache_APIC_registers(void);
 215 extern void sync_Arb_IDs(void);
 216 extern void init_bsp_APIC(void);
 217 extern void setup_local_APIC(void);
 218 extern void end_local_APIC_setup(void);
 219 extern void init_apic_mappings(void);
 220 extern void setup_boot_APIC_clock(void);
 221 extern void setup_secondary_APIC_clock(void);
 222 extern int APIC_init_uniprocessor(void);
 223 extern void enable_NMI_through_LVT0(void);
 224
 225 /*
 226  * On 32bit this is mach-xxx local
 227  */
 228 #ifdef CONFIG_X86_64
 229 extern void early_init_lapic_mapping(void);
 230 extern int apic_is_clustered_box(void);
 231 #else
 232 static inline int apic_is_clustered_box(void)
 233 {
 234         return 0;
 235 }
 236 #endif
 237
 238 extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask);
 239 extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask);
 240
 241
 242 #else /* !CONFIG_X86_LOCAL_APIC */
 243 static inline void lapic_shutdown(void) { }
 244 #define local_apic_timer_c2_ok          1
 245 static inline void init_apic_mappings(void) { }
 246 static inline void disable_local_APIC(void) { }
 247 static inline void apic_disable(void) { }
 248 #endif /* !CONFIG_X86_LOCAL_APIC */
 249
 250 #ifdef CONFIG_X86_64
 251 #define SET_APIC_ID(x)          (apic->set_apic_id(x))
 252 #else
 253
 254 #endif
 255
 256 /*
 257  * Copyright 2004 James Cleverdon, IBM.
 258  * Subject to the GNU Public License, v.2
 259  *
 260  * Generic APIC sub-arch data struct.
 261  *
 262  * Hacked for x86-64 by James Cleverdon from i386 architecture code by
 263  * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
 264  * James Cleverdon.
 265  */
 266 struct apic {
 267         char *name;
 268
 269         int (*probe)(void);
 270         int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
 271         int (*apic_id_registered)(void);
 272
 273         u32 irq_delivery_mode;
 274         u32 irq_dest_mode;
 275
 276         const struct cpumask *(*target_cpus)(void);
 277
 278         int disable_esr;
 279
 280         int dest_logical;
 281         unsigned long (*check_apicid_used)(physid_mask_t bitmap, int apicid);
 282         unsigned long (*check_apicid_present)(int apicid);
 283
 284         void (*vector_allocation_domain)(int cpu, struct cpumask *retmask);
 285         void (*init_apic_ldr)(void);
 286
 287         physid_mask_t (*ioapic_phys_id_map)(physid_mask_t map);
 288
 289         void (*setup_apic_routing)(void);
 290         int (*multi_timer_check)(int apic, int irq);
 291         int (*apicid_to_node)(int logical_apicid);
 292         int (*cpu_to_logical_apicid)(int cpu);
 293         int (*cpu_present_to_apicid)(int mps_cpu);
 294         physid_mask_t (*apicid_to_cpu_present)(int phys_apicid);
 295         void (*setup_portio_remap)(void);
 296         int (*check_phys_apicid_present)(int boot_cpu_physical_apicid);
 297         void (*enable_apic_mode)(void);
 298         int (*phys_pkg_id)(int cpuid_apic, int index_msb);
 299
 300         /*
 301          * When one of the next two hooks returns 1 the apic
 302          * is switched to this. Essentially they are additional
 303          * probe functions:
 304          */
 305         int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid);
 306
 307         unsigned int (*get_apic_id)(unsigned long x);
 308         unsigned long (*set_apic_id)(unsigned int id);
 309         unsigned long apic_id_mask;
 310
 311         unsigned int (*cpu_mask_to_apicid)(const struct cpumask *cpumask);
 312         unsigned int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask,
 313                                                const struct cpumask *andmask);
 314
 315         /* ipi */
 316         void (*send_IPI_mask)(const struct cpumask *mask, int vector);
 317         void (*send_IPI_mask_allbutself)(const struct cpumask *mask,
 318                                          int vector);
 319         void (*send_IPI_allbutself)(int vector);
 320         void (*send_IPI_all)(int vector);
 321         void (*send_IPI_self)(int vector);
 322
 323         /* wakeup_secondary_cpu */
 324         int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
 325
 326         int trampoline_phys_low;
 327         int trampoline_phys_high;
 328
 329         void (*wait_for_init_deassert)(atomic_t *deassert);
 330         void (*smp_callin_clear_local_apic)(void);
 331         void (*inquire_remote_apic)(int apicid);
 332
 333         /* apic ops */
 334         u32 (*read)(u32 reg);
 335         void (*write)(u32 reg, u32 v);
 336         u64 (*icr_read)(void);
 337         void (*icr_write)(u32 low, u32 high);
 338         void (*wait_icr_idle)(void);
 339         u32 (*safe_wait_icr_idle)(void);
 340 };
 341
 342 /*
 343  * Pointer to the local APIC driver in use on this system (there's
 344  * always just one such driver in use - the kernel decides via an
 345  * early probing process which one it picks - and then sticks to it):
 346  */
 347 extern struct apic *apic;
 348
 349 /*
 350  * APIC functionality to boot other CPUs - only used on SMP:
 351  */
 352 #ifdef CONFIG_SMP
 353 extern atomic_t init_deasserted;
 354 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
 355 #endif
 356
 357 static inline u32 apic_read(u32 reg)
 358 {
 359         return apic->read(reg);
 360 }
 361
 362 static inline void apic_write(u32 reg, u32 val)
 363 {
 364         apic->write(reg, val);
 365 }
 366
 367 static inline u64 apic_icr_read(void)
 368 {
 369         return apic->icr_read();
 370 }
 371
 372 static inline void apic_icr_write(u32 low, u32 high)
 373 {
 374         apic->icr_write(low, high);
 375 }
 376
 377 static inline void apic_wait_icr_idle(void)
 378 {
 379         apic->wait_icr_idle();
 380 }
 381
 382 static inline u32 safe_apic_wait_icr_idle(void)
 383 {
 384         return apic->safe_wait_icr_idle();
 385 }
 386
 387
 388 static inline void ack_APIC_irq(void)
 389 {
 390 #ifdef CONFIG_X86_LOCAL_APIC
 391         /*
 392          * ack_APIC_irq() actually gets compiled as a single instruction
 393          * ... yummie.
 394          */
 395
 396         /* Docs say use 0 for future compatibility */
 397         apic_write(APIC_EOI, 0);
 398 #endif
 399 }
 400
 401 static inline unsigned default_get_apic_id(unsigned long x)
 402 {
 403         unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
 404
 405         if (APIC_XAPIC(ver))
 406                 return (x >> 24) & 0xFF;
 407         else
 408                 return (x >> 24) & 0x0F;
 409 }
 410
 411 /*
 412  * Warm reset vector default position:
 413  */
 414 #define DEFAULT_TRAMPOLINE_PHYS_LOW             0x467
 415 #define DEFAULT_TRAMPOLINE_PHYS_HIGH            0x469
 416
 417 #ifdef CONFIG_X86_64
 418 extern struct apic apic_flat;
 419 extern struct apic apic_physflat;
 420 extern struct apic apic_x2apic_cluster;
 421 extern struct apic apic_x2apic_phys;
 422 extern int default_acpi_madt_oem_check(char *, char *);
 423
 424 extern void apic_send_IPI_self(int vector);
 425
 426 extern struct apic apic_x2apic_uv_x;
 427 DECLARE_PER_CPU(int, x2apic_extra_bits);
 428
 429 extern int default_cpu_present_to_apicid(int mps_cpu);
 430 extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid);
 431 #endif
 432
 433 static inline void default_wait_for_init_deassert(atomic_t *deassert)
 434 {
 435         while (!atomic_read(deassert))
 436                 cpu_relax();
 437         return;
 438 }
 439
 440 extern void generic_bigsmp_probe(void);
 441
 442
 443 #ifdef CONFIG_X86_LOCAL_APIC
 444
 445 #include <asm/smp.h>
 446
 447 #define APIC_DFR_VALUE  (APIC_DFR_FLAT)
 448
 449 static inline const struct cpumask *default_target_cpus(void)
 450 {
 451 #ifdef CONFIG_SMP
 452         return cpu_online_mask;
 453 #else
 454         return cpumask_of(0);
 455 #endif
 456 }
 457
 458 DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid);
 459
 460
 461 static inline unsigned int read_apic_id(void)
 462 {
 463         unsigned int reg;
 464
 465         reg = apic_read(APIC_ID);
 466
 467         return apic->get_apic_id(reg);
 468 }
 469
 470 extern void default_setup_apic_routing(void);
 471
 472 #ifdef CONFIG_X86_32
 473
 474 extern struct apic apic_default;
 475
 476 /*
 477  * Set up the logical destination ID.
 478  *
 479  * Intel recommends to set DFR, LDR and TPR before enabling
 480  * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
 481  * document number 292116).  So here it goes...
 482  */
 483 extern void default_init_apic_ldr(void);
 484
 485 static inline int default_apic_id_registered(void)
 486 {
 487         return physid_isset(read_apic_id(), phys_cpu_present_map);
 488 }
 489
 490 static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
 491 {
 492         return cpuid_apic >> index_msb;
 493 }
 494
 495 extern int default_apicid_to_node(int logical_apicid);
 496
 497 #endif
 498
 499 static inline unsigned int
 500 default_cpu_mask_to_apicid(const struct cpumask *cpumask)
 501 {
 502         return cpumask_bits(cpumask)[0] & APIC_ALL_CPUS;
 503 }
 504
 505 static inline unsigned int
 506 default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
 507                                const struct cpumask *andmask)
 508 {
 509         unsigned long mask1 = cpumask_bits(cpumask)[0];
 510         unsigned long mask2 = cpumask_bits(andmask)[0];
 511         unsigned long mask3 = cpumask_bits(cpu_online_mask)[0];
 512
 513         return (unsigned int)(mask1 & mask2 & mask3);
 514 }
 515
 516 static inline unsigned long default_check_apicid_used(physid_mask_t bitmap, int apicid)
 517 {
 518         return physid_isset(apicid, bitmap);
 519 }
 520
 521 static inline unsigned long default_check_apicid_present(int bit)
 522 {
 523         return physid_isset(bit, phys_cpu_present_map);
 524 }
 525
 526 static inline physid_mask_t default_ioapic_phys_id_map(physid_mask_t phys_map)
 527 {
 528         return phys_map;
 529 }
 530
 531 /* Mapping from cpu number to logical apicid */
 532 static inline int default_cpu_to_logical_apicid(int cpu)
 533 {
 534         return 1 << cpu;
 535 }
 536
 537 static inline int __default_cpu_present_to_apicid(int mps_cpu)
 538 {
 539         if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
 540                 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
 541         else
 542                 return BAD_APICID;
 543 }
 544
 545 static inline int
 546 __default_check_phys_apicid_present(int boot_cpu_physical_apicid)
 547 {
 548         return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map);
 549 }
 550
 551 #ifdef CONFIG_X86_32
 552 static inline int default_cpu_present_to_apicid(int mps_cpu)
 553 {
 554         return __default_cpu_present_to_apicid(mps_cpu);
 555 }
 556
 557 static inline int
 558 default_check_phys_apicid_present(int boot_cpu_physical_apicid)
 559 {
 560         return __default_check_phys_apicid_present(boot_cpu_physical_apicid);
 561 }
 562 #else
 563 extern int default_cpu_present_to_apicid(int mps_cpu);
 564 extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid);
 565 #endif
 566
 567 static inline physid_mask_t default_apicid_to_cpu_present(int phys_apicid)
 568 {
 569         return physid_mask_of_physid(phys_apicid);
 570 }
 571
 572 #endif /* CONFIG_X86_LOCAL_APIC */
 573
 574 #ifdef CONFIG_X86_32
 575 extern u8 cpu_2_logical_apicid[NR_CPUS];
 576 #endif
 577
 578 #endif /* _ASM_X86_APIC_H */