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1 #ifndef _ASM_X86_APIC_H
2 #define _ASM_X86_APIC_H
3
4 #include <linux/cpumask.h>
5 #include <linux/pm.h>
6
7 #include <asm/alternative.h>
8 #include <asm/cpufeature.h>
9 #include <asm/processor.h>
10 #include <asm/apicdef.h>
11 #include <linux/atomic.h>
12 #include <asm/fixmap.h>
13 #include <asm/mpspec.h>
14 #include <asm/msr.h>
15
16 #define ARCH_APICTIMER_STOPS_ON_C3 1
17
18 /*
19 * Debugging macros
20 */
21 #define APIC_QUIET 0
22 #define APIC_VERBOSE 1
23 #define APIC_DEBUG 2
24
25 /*
26 * Define the default level of output to be very little
27 * This can be turned up by using apic=verbose for more
28 * information and apic=debug for _lots_ of information.
29 * apic_verbosity is defined in apic.c
30 */
31 #define apic_printk(v, s, a...) do { \
32 if ((v) <= apic_verbosity) \
33 printk(s, ##a); \
34 } while (0)
35
36
37 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
38 extern void generic_apic_probe(void);
39 #else
40 static inline void generic_apic_probe(void)
41 {
42 }
43 #endif
44
45 #ifdef CONFIG_X86_LOCAL_APIC
46
47 extern unsigned int apic_verbosity;
48 extern int local_apic_timer_c2_ok;
49
50 extern int disable_apic;
51 extern unsigned int lapic_timer_frequency;
52
53 #ifdef CONFIG_SMP
54 extern void __inquire_remote_apic(int apicid);
55 #else /* CONFIG_SMP */
56 static inline void __inquire_remote_apic(int apicid)
57 {
58 }
59 #endif /* CONFIG_SMP */
60
61 static inline void default_inquire_remote_apic(int apicid)
62 {
63 if (apic_verbosity >= APIC_DEBUG)
64 __inquire_remote_apic(apicid);
65 }
66
67 /*
68 * With 82489DX we can't rely on apic feature bit
69 * retrieved via cpuid but still have to deal with
70 * such an apic chip so we assume that SMP configuration
71 * is found from MP table (64bit case uses ACPI mostly
72 * which set smp presence flag as well so we are safe
73 * to use this helper too).
74 */
75 static inline bool apic_from_smp_config(void)
76 {
77 return smp_found_config && !disable_apic;
78 }
79
80 /*
81 * Basic functions accessing APICs.
82 */
83 #ifdef CONFIG_PARAVIRT
84 #include <asm/paravirt.h>
85 #endif
86
87 #ifdef CONFIG_X86_64
88 extern int is_vsmp_box(void);
89 #else
90 static inline int is_vsmp_box(void)
91 {
92 return 0;
93 }
94 #endif
95 extern void xapic_wait_icr_idle(void);
96 extern u32 safe_xapic_wait_icr_idle(void);
97 extern void xapic_icr_write(u32, u32);
98 extern int setup_profiling_timer(unsigned int);
99
100 static inline void native_apic_mem_write(u32 reg, u32 v)
101 {
102 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
103
104 alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP,
105 ASM_OUTPUT2("=r" (v), "=m" (*addr)),
106 ASM_OUTPUT2("0" (v), "m" (*addr)));
107 }
108
109 static inline u32 native_apic_mem_read(u32 reg)
110 {
111 return *((volatile u32 *)(APIC_BASE + reg));
112 }
113
114 extern void native_apic_wait_icr_idle(void);
115 extern u32 native_safe_apic_wait_icr_idle(void);
116 extern void native_apic_icr_write(u32 low, u32 id);
117 extern u64 native_apic_icr_read(void);
118
119 extern int x2apic_mode;
120
121 #ifdef CONFIG_X86_X2APIC
122 /*
123 * Make previous memory operations globally visible before
124 * sending the IPI through x2apic wrmsr. We need a serializing instruction or
125 * mfence for this.
126 */
127 static inline void x2apic_wrmsr_fence(void)
128 {
129 asm volatile("mfence" : : : "memory");
130 }
131
132 static inline void native_apic_msr_write(u32 reg, u32 v)
133 {
134 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
135 reg == APIC_LVR)
136 return;
137
138 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
139 }
140
141 static inline void native_apic_msr_eoi_write(u32 reg, u32 v)
142 {
143 wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0);
144 }
145
146 static inline u32 native_apic_msr_read(u32 reg)
147 {
148 u64 msr;
149
150 if (reg == APIC_DFR)
151 return -1;
152
153 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
154 return (u32)msr;
155 }
156
157 static inline void native_x2apic_wait_icr_idle(void)
158 {
159 /* no need to wait for icr idle in x2apic */
160 return;
161 }
162
163 static inline u32 native_safe_x2apic_wait_icr_idle(void)
164 {
165 /* no need to wait for icr idle in x2apic */
166 return 0;
167 }
168
169 static inline void native_x2apic_icr_write(u32 low, u32 id)
170 {
171 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
172 }
173
174 static inline u64 native_x2apic_icr_read(void)
175 {
176 unsigned long val;
177
178 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
179 return val;
180 }
181
182 extern int x2apic_phys;
183 extern int x2apic_preenabled;
184 extern void check_x2apic(void);
185 extern void enable_x2apic(void);
186 extern void x2apic_icr_write(u32 low, u32 id);
187 static inline int x2apic_enabled(void)
188 {
189 u64 msr;
190
191 if (!cpu_has_x2apic)
192 return 0;
193
194 rdmsrl(MSR_IA32_APICBASE, msr);
195 if (msr & X2APIC_ENABLE)
196 return 1;
197 return 0;
198 }
199
200 #define x2apic_supported() (cpu_has_x2apic)
201 static inline void x2apic_force_phys(void)
202 {
203 x2apic_phys = 1;
204 }
205 #else
206 static inline void disable_x2apic(void)
207 {
208 }
209 static inline void check_x2apic(void)
210 {
211 }
212 static inline void enable_x2apic(void)
213 {
214 }
215 static inline int x2apic_enabled(void)
216 {
217 return 0;
218 }
219 static inline void x2apic_force_phys(void)
220 {
221 }
222
223 #define nox2apic 0
224 #define x2apic_preenabled 0
225 #define x2apic_supported() 0
226 #endif
227
228 extern void enable_IR_x2apic(void);
229
230 extern int get_physical_broadcast(void);
231
232 extern int lapic_get_maxlvt(void);
233 extern void clear_local_APIC(void);
234 extern void connect_bsp_APIC(void);
235 extern void disconnect_bsp_APIC(int virt_wire_setup);
236 extern void disable_local_APIC(void);
237 extern void lapic_shutdown(void);
238 extern int verify_local_APIC(void);
239 extern void sync_Arb_IDs(void);
240 extern void init_bsp_APIC(void);
241 extern void setup_local_APIC(void);
242 extern void end_local_APIC_setup(void);
243 extern void bsp_end_local_APIC_setup(void);
244 extern void init_apic_mappings(void);
245 void register_lapic_address(unsigned long address);
246 extern void setup_boot_APIC_clock(void);
247 extern void setup_secondary_APIC_clock(void);
248 extern int APIC_init_uniprocessor(void);
249 extern int apic_force_enable(unsigned long addr);
250
251 /*
252 * On 32bit this is mach-xxx local
253 */
254 #ifdef CONFIG_X86_64
255 extern int apic_is_clustered_box(void);
256 #else
257 static inline int apic_is_clustered_box(void)
258 {
259 return 0;
260 }
261 #endif
262
263 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
264
265 #else /* !CONFIG_X86_LOCAL_APIC */
266 static inline void lapic_shutdown(void) { }
267 #define local_apic_timer_c2_ok 1
268 static inline void init_apic_mappings(void) { }
269 static inline void disable_local_APIC(void) { }
270 # define setup_boot_APIC_clock x86_init_noop
271 # define setup_secondary_APIC_clock x86_init_noop
272 #endif /* !CONFIG_X86_LOCAL_APIC */
273
274 #ifdef CONFIG_X86_64
275 #define SET_APIC_ID(x) (apic->set_apic_id(x))
276 #else
277
278 #endif
279
280 /*
281 * Copyright 2004 James Cleverdon, IBM.
282 * Subject to the GNU Public License, v.2
283 *
284 * Generic APIC sub-arch data struct.
285 *
286 * Hacked for x86-64 by James Cleverdon from i386 architecture code by
287 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
288 * James Cleverdon.
289 */
290 struct apic {
291 char *name;
292
293 int (*probe)(void);
294 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
295 int (*apic_id_valid)(int apicid);
296 int (*apic_id_registered)(void);
297
298 u32 irq_delivery_mode;
299 u32 irq_dest_mode;
300
301 const struct cpumask *(*target_cpus)(void);
302
303 int disable_esr;
304
305 int dest_logical;
306 unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid);
307 unsigned long (*check_apicid_present)(int apicid);
308
309 bool (*vector_allocation_domain)(int cpu, struct cpumask *retmask);
310 void (*init_apic_ldr)(void);
311
312 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap);
313
314 void (*setup_apic_routing)(void);
315 int (*multi_timer_check)(int apic, int irq);
316 int (*cpu_present_to_apicid)(int mps_cpu);
317 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap);
318 void (*setup_portio_remap)(void);
319 int (*check_phys_apicid_present)(int phys_apicid);
320 void (*enable_apic_mode)(void);
321 int (*phys_pkg_id)(int cpuid_apic, int index_msb);
322
323 /*
324 * When one of the next two hooks returns 1 the apic
325 * is switched to this. Essentially they are additional
326 * probe functions:
327 */
328 int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid);
329
330 unsigned int (*get_apic_id)(unsigned long x);
331 unsigned long (*set_apic_id)(unsigned int id);
332 unsigned long apic_id_mask;
333
334 int (*cpu_mask_to_apicid)(const struct cpumask *cpumask,
335 unsigned int *apicid);
336 int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask,
337 const struct cpumask *andmask,
338 unsigned int *apicid);
339
340 /* ipi */
341 void (*send_IPI_mask)(const struct cpumask *mask, int vector);
342 void (*send_IPI_mask_allbutself)(const struct cpumask *mask,
343 int vector);
344 void (*send_IPI_allbutself)(int vector);
345 void (*send_IPI_all)(int vector);
346 void (*send_IPI_self)(int vector);
347
348 /* wakeup_secondary_cpu */
349 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
350
351 int trampoline_phys_low;
352 int trampoline_phys_high;
353
354 void (*wait_for_init_deassert)(atomic_t *deassert);
355 void (*smp_callin_clear_local_apic)(void);
356 void (*inquire_remote_apic)(int apicid);
357
358 /* apic ops */
359 u32 (*read)(u32 reg);
360 void (*write)(u32 reg, u32 v);
361 /*
362 * ->eoi_write() has the same signature as ->write().
363 *
364 * Drivers can support both ->eoi_write() and ->write() by passing the same
365 * callback value. Kernel can override ->eoi_write() and fall back
366 * on write for EOI.
367 */
368 void (*eoi_write)(u32 reg, u32 v);
369 u64 (*icr_read)(void);
370 void (*icr_write)(u32 low, u32 high);
371 void (*wait_icr_idle)(void);
372 u32 (*safe_wait_icr_idle)(void);
373
374 #ifdef CONFIG_X86_32
375 /*
376 * Called very early during boot from get_smp_config(). It should
377 * return the logical apicid. x86_[bios]_cpu_to_apicid is
378 * initialized before this function is called.
379 *
380 * If logical apicid can't be determined that early, the function
381 * may return BAD_APICID. Logical apicid will be configured after
382 * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity
383 * won't be applied properly during early boot in this case.
384 */
385 int (*x86_32_early_logical_apicid)(int cpu);
386
387 /*
388 * Optional method called from setup_local_APIC() after logical
389 * apicid is guaranteed to be known to initialize apicid -> node
390 * mapping if NUMA initialization hasn't done so already. Don't
391 * add new users.
392 */
393 int (*x86_32_numa_cpu_node)(int cpu);
394 #endif
395 };
396
397 /*
398 * Pointer to the local APIC driver in use on this system (there's
399 * always just one such driver in use - the kernel decides via an
400 * early probing process which one it picks - and then sticks to it):
401 */
402 extern struct apic *apic;
403
404 /*
405 * APIC drivers are probed based on how they are listed in the .apicdrivers
406 * section. So the order is important and enforced by the ordering
407 * of different apic driver files in the Makefile.
408 *
409 * For the files having two apic drivers, we use apic_drivers()
410 * to enforce the order with in them.
411 */
412 #define apic_driver(sym) \
413 static struct apic *__apicdrivers_##sym __used \
414 __aligned(sizeof(struct apic *)) \
415 __section(.apicdrivers) = { &sym }
416
417 #define apic_drivers(sym1, sym2) \
418 static struct apic *__apicdrivers_##sym1##sym2[2] __used \
419 __aligned(sizeof(struct apic *)) \
420 __section(.apicdrivers) = { &sym1, &sym2 }
421
422 extern struct apic *__apicdrivers[], *__apicdrivers_end[];
423
424 /*
425 * APIC functionality to boot other CPUs - only used on SMP:
426 */
427 #ifdef CONFIG_SMP
428 extern atomic_t init_deasserted;
429 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
430 #endif
431
432 #ifdef CONFIG_X86_LOCAL_APIC
433
434 static inline u32 apic_read(u32 reg)
435 {
436 return apic->read(reg);
437 }
438
439 static inline void apic_write(u32 reg, u32 val)
440 {
441 apic->write(reg, val);
442 }
443
444 static inline void apic_eoi(void)
445 {
446 apic->eoi_write(APIC_EOI, APIC_EOI_ACK);
447 }
448
449 static inline u64 apic_icr_read(void)
450 {
451 return apic->icr_read();
452 }
453
454 static inline void apic_icr_write(u32 low, u32 high)
455 {
456 apic->icr_write(low, high);
457 }
458
459 static inline void apic_wait_icr_idle(void)
460 {
461 apic->wait_icr_idle();
462 }
463
464 static inline u32 safe_apic_wait_icr_idle(void)
465 {
466 return apic->safe_wait_icr_idle();
467 }
468
469 #else /* CONFIG_X86_LOCAL_APIC */
470
471 static inline u32 apic_read(u32 reg) { return 0; }
472 static inline void apic_write(u32 reg, u32 val) { }
473 static inline void apic_eoi(void) { }
474 static inline u64 apic_icr_read(void) { return 0; }
475 static inline void apic_icr_write(u32 low, u32 high) { }
476 static inline void apic_wait_icr_idle(void) { }
477 static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
478
479 #endif /* CONFIG_X86_LOCAL_APIC */
480
481 static inline void ack_APIC_irq(void)
482 {
483 /*
484 * ack_APIC_irq() actually gets compiled as a single instruction
485 * ... yummie.
486 */
487 apic_eoi();
488 }
489
490 static inline unsigned default_get_apic_id(unsigned long x)
491 {
492 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
493
494 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID))
495 return (x >> 24) & 0xFF;
496 else
497 return (x >> 24) & 0x0F;
498 }
499
500 /*
501 * Warm reset vector default position:
502 */
503 #define DEFAULT_TRAMPOLINE_PHYS_LOW 0x467
504 #define DEFAULT_TRAMPOLINE_PHYS_HIGH 0x469
505
506 #ifdef CONFIG_X86_64
507 extern int default_acpi_madt_oem_check(char *, char *);
508
509 extern void apic_send_IPI_self(int vector);
510
511 DECLARE_PER_CPU(int, x2apic_extra_bits);
512
513 extern int default_cpu_present_to_apicid(int mps_cpu);
514 extern int default_check_phys_apicid_present(int phys_apicid);
515 #endif
516
517 static inline void default_wait_for_init_deassert(atomic_t *deassert)
518 {
519 while (!atomic_read(deassert))
520 cpu_relax();
521 return;
522 }
523
524 extern void generic_bigsmp_probe(void);
525
526
527 #ifdef CONFIG_X86_LOCAL_APIC
528
529 #include <asm/smp.h>
530
531 #define APIC_DFR_VALUE (APIC_DFR_FLAT)
532
533 static inline const struct cpumask *default_target_cpus(void)
534 {
535 #ifdef CONFIG_SMP
536 return cpu_online_mask;
537 #else
538 return cpumask_of(0);
539 #endif
540 }
541
542 static inline const struct cpumask *online_target_cpus(void)
543 {
544 return cpu_online_mask;
545 }
546
547 DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid);
548
549
550 static inline unsigned int read_apic_id(void)
551 {
552 unsigned int reg;
553
554 reg = apic_read(APIC_ID);
555
556 return apic->get_apic_id(reg);
557 }
558
559 static inline int default_apic_id_valid(int apicid)
560 {
561 return (apicid < 255);
562 }
563
564 extern void default_setup_apic_routing(void);
565
566 extern struct apic apic_noop;
567
568 #ifdef CONFIG_X86_32
569
570 static inline int noop_x86_32_early_logical_apicid(int cpu)
571 {
572 return BAD_APICID;
573 }
574
575 /*
576 * Set up the logical destination ID.
577 *
578 * Intel recommends to set DFR, LDR and TPR before enabling
579 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
580 * document number 292116). So here it goes...
581 */
582 extern void default_init_apic_ldr(void);
583
584 static inline int default_apic_id_registered(void)
585 {
586 return physid_isset(read_apic_id(), phys_cpu_present_map);
587 }
588
589 static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
590 {
591 return cpuid_apic >> index_msb;
592 }
593
594 #endif
595
596 static inline int
597 __flat_cpu_mask_to_apicid(unsigned long cpu_mask, unsigned int *apicid)
598 {
599 cpu_mask &= APIC_ALL_CPUS;
600 if (likely(cpu_mask)) {
601 *apicid = (unsigned int)cpu_mask;
602 return 0;
603 } else {
604 return -EINVAL;
605 }
606 }
607
608 static inline int
609 flat_cpu_mask_to_apicid(const struct cpumask *cpumask,
610 unsigned int *apicid)
611 {
612 return __flat_cpu_mask_to_apicid(cpumask_bits(cpumask)[0], apicid);
613 }
614
615 static inline int
616 flat_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
617 const struct cpumask *andmask,
618 unsigned int *apicid)
619 {
620 unsigned long mask1 = cpumask_bits(cpumask)[0];
621 unsigned long mask2 = cpumask_bits(andmask)[0];
622 unsigned long mask3 = cpumask_bits(cpu_online_mask)[0];
623
624 return __flat_cpu_mask_to_apicid(mask1 & mask2 & mask3, apicid);
625 }
626
627 extern int
628 default_cpu_mask_to_apicid(const struct cpumask *cpumask,
629 unsigned int *apicid);
630
631 extern int
632 default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
633 const struct cpumask *andmask,
634 unsigned int *apicid);
635
636 static inline bool
637 flat_vector_allocation_domain(int cpu, struct cpumask *retmask)
638 {
639 /* Careful. Some cpus do not strictly honor the set of cpus
640 * specified in the interrupt destination when using lowest
641 * priority interrupt delivery mode.
642 *
643 * In particular there was a hyperthreading cpu observed to
644 * deliver interrupts to the wrong hyperthread when only one
645 * hyperthread was specified in the interrupt desitination.
646 */
647 cpumask_clear(retmask);
648 cpumask_bits(retmask)[0] = APIC_ALL_CPUS;
649 return false;
650 }
651
652 static inline bool
653 default_vector_allocation_domain(int cpu, struct cpumask *retmask)
654 {
655 cpumask_copy(retmask, cpumask_of(cpu));
656 return true;
657 }
658
659 static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid)
660 {
661 return physid_isset(apicid, *map);
662 }
663
664 static inline unsigned long default_check_apicid_present(int bit)
665 {
666 return physid_isset(bit, phys_cpu_present_map);
667 }
668
669 static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap)
670 {
671 *retmap = *phys_map;
672 }
673
674 static inline int __default_cpu_present_to_apicid(int mps_cpu)
675 {
676 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
677 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
678 else
679 return BAD_APICID;
680 }
681
682 static inline int
683 __default_check_phys_apicid_present(int phys_apicid)
684 {
685 return physid_isset(phys_apicid, phys_cpu_present_map);
686 }
687
688 #ifdef CONFIG_X86_32
689 static inline int default_cpu_present_to_apicid(int mps_cpu)
690 {
691 return __default_cpu_present_to_apicid(mps_cpu);
692 }
693
694 static inline int
695 default_check_phys_apicid_present(int phys_apicid)
696 {
697 return __default_check_phys_apicid_present(phys_apicid);
698 }
699 #else
700 extern int default_cpu_present_to_apicid(int mps_cpu);
701 extern int default_check_phys_apicid_present(int phys_apicid);
702 #endif
703
704 #endif /* CONFIG_X86_LOCAL_APIC */
705
706 #endif /* _ASM_X86_APIC_H */