1 #ifndef _ASM_X86_APIC_H
2 #define _ASM_X86_APIC_H
4 #include <linux/cpumask.h>
7 #include <asm/alternative.h>
8 #include <asm/cpufeature.h>
9 #include <asm/processor.h>
10 #include <asm/apicdef.h>
11 #include <linux/atomic.h>
12 #include <asm/fixmap.h>
13 #include <asm/mpspec.h>
16 #define ARCH_APICTIMER_STOPS_ON_C3 1
22 #define APIC_VERBOSE 1
26 * Define the default level of output to be very little
27 * This can be turned up by using apic=verbose for more
28 * information and apic=debug for _lots_ of information.
29 * apic_verbosity is defined in apic.c
31 #define apic_printk(v, s, a...) do { \
32 if ((v) <= apic_verbosity) \
37 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
38 extern void generic_apic_probe(void);
40 static inline void generic_apic_probe(void)
45 #ifdef CONFIG_X86_LOCAL_APIC
47 extern unsigned int apic_verbosity
;
48 extern int local_apic_timer_c2_ok
;
50 extern int disable_apic
;
51 extern unsigned int lapic_timer_frequency
;
54 extern void __inquire_remote_apic(int apicid
);
55 #else /* CONFIG_SMP */
56 static inline void __inquire_remote_apic(int apicid
)
59 #endif /* CONFIG_SMP */
61 static inline void default_inquire_remote_apic(int apicid
)
63 if (apic_verbosity
>= APIC_DEBUG
)
64 __inquire_remote_apic(apicid
);
68 * With 82489DX we can't rely on apic feature bit
69 * retrieved via cpuid but still have to deal with
70 * such an apic chip so we assume that SMP configuration
71 * is found from MP table (64bit case uses ACPI mostly
72 * which set smp presence flag as well so we are safe
73 * to use this helper too).
75 static inline bool apic_from_smp_config(void)
77 return smp_found_config
&& !disable_apic
;
81 * Basic functions accessing APICs.
83 #ifdef CONFIG_PARAVIRT
84 #include <asm/paravirt.h>
88 extern int is_vsmp_box(void);
90 static inline int is_vsmp_box(void)
95 extern void xapic_wait_icr_idle(void);
96 extern u32
safe_xapic_wait_icr_idle(void);
97 extern void xapic_icr_write(u32
, u32
);
98 extern int setup_profiling_timer(unsigned int);
100 static inline void native_apic_mem_write(u32 reg
, u32 v
)
102 volatile u32
*addr
= (volatile u32
*)(APIC_BASE
+ reg
);
104 alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP
,
105 ASM_OUTPUT2("=r" (v
), "=m" (*addr
)),
106 ASM_OUTPUT2("0" (v
), "m" (*addr
)));
109 static inline u32
native_apic_mem_read(u32 reg
)
111 return *((volatile u32
*)(APIC_BASE
+ reg
));
114 extern void native_apic_wait_icr_idle(void);
115 extern u32
native_safe_apic_wait_icr_idle(void);
116 extern void native_apic_icr_write(u32 low
, u32 id
);
117 extern u64
native_apic_icr_read(void);
119 extern int x2apic_mode
;
121 #ifdef CONFIG_X86_X2APIC
123 * Make previous memory operations globally visible before
124 * sending the IPI through x2apic wrmsr. We need a serializing instruction or
127 static inline void x2apic_wrmsr_fence(void)
129 asm volatile("mfence" : : : "memory");
132 static inline void native_apic_msr_write(u32 reg
, u32 v
)
134 if (reg
== APIC_DFR
|| reg
== APIC_ID
|| reg
== APIC_LDR
||
138 wrmsr(APIC_BASE_MSR
+ (reg
>> 4), v
, 0);
141 static inline void native_apic_msr_eoi_write(u32 reg
, u32 v
)
143 wrmsr(APIC_BASE_MSR
+ (APIC_EOI
>> 4), APIC_EOI_ACK
, 0);
146 static inline u32
native_apic_msr_read(u32 reg
)
153 rdmsrl(APIC_BASE_MSR
+ (reg
>> 4), msr
);
157 static inline void native_x2apic_wait_icr_idle(void)
159 /* no need to wait for icr idle in x2apic */
163 static inline u32
native_safe_x2apic_wait_icr_idle(void)
165 /* no need to wait for icr idle in x2apic */
169 static inline void native_x2apic_icr_write(u32 low
, u32 id
)
171 wrmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), ((__u64
) id
) << 32 | low
);
174 static inline u64
native_x2apic_icr_read(void)
178 rdmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), val
);
182 extern int x2apic_phys
;
183 extern int x2apic_preenabled
;
184 extern void check_x2apic(void);
185 extern void enable_x2apic(void);
186 extern void x2apic_icr_write(u32 low
, u32 id
);
187 static inline int x2apic_enabled(void)
194 rdmsrl(MSR_IA32_APICBASE
, msr
);
195 if (msr
& X2APIC_ENABLE
)
200 #define x2apic_supported() (cpu_has_x2apic)
201 static inline void x2apic_force_phys(void)
206 static inline void disable_x2apic(void)
209 static inline void check_x2apic(void)
212 static inline void enable_x2apic(void)
215 static inline int x2apic_enabled(void)
219 static inline void x2apic_force_phys(void)
224 #define x2apic_preenabled 0
225 #define x2apic_supported() 0
228 extern void enable_IR_x2apic(void);
230 extern int get_physical_broadcast(void);
232 extern int lapic_get_maxlvt(void);
233 extern void clear_local_APIC(void);
234 extern void connect_bsp_APIC(void);
235 extern void disconnect_bsp_APIC(int virt_wire_setup
);
236 extern void disable_local_APIC(void);
237 extern void lapic_shutdown(void);
238 extern int verify_local_APIC(void);
239 extern void sync_Arb_IDs(void);
240 extern void init_bsp_APIC(void);
241 extern void setup_local_APIC(void);
242 extern void end_local_APIC_setup(void);
243 extern void bsp_end_local_APIC_setup(void);
244 extern void init_apic_mappings(void);
245 void register_lapic_address(unsigned long address
);
246 extern void setup_boot_APIC_clock(void);
247 extern void setup_secondary_APIC_clock(void);
248 extern int APIC_init_uniprocessor(void);
249 extern int apic_force_enable(unsigned long addr
);
252 * On 32bit this is mach-xxx local
255 extern int apic_is_clustered_box(void);
257 static inline int apic_is_clustered_box(void)
263 extern int setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
);
265 #else /* !CONFIG_X86_LOCAL_APIC */
266 static inline void lapic_shutdown(void) { }
267 #define local_apic_timer_c2_ok 1
268 static inline void init_apic_mappings(void) { }
269 static inline void disable_local_APIC(void) { }
270 # define setup_boot_APIC_clock x86_init_noop
271 # define setup_secondary_APIC_clock x86_init_noop
272 #endif /* !CONFIG_X86_LOCAL_APIC */
275 #define SET_APIC_ID(x) (apic->set_apic_id(x))
281 * Copyright 2004 James Cleverdon, IBM.
282 * Subject to the GNU Public License, v.2
284 * Generic APIC sub-arch data struct.
286 * Hacked for x86-64 by James Cleverdon from i386 architecture code by
287 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
294 int (*acpi_madt_oem_check
)(char *oem_id
, char *oem_table_id
);
295 int (*apic_id_valid
)(int apicid
);
296 int (*apic_id_registered
)(void);
298 u32 irq_delivery_mode
;
301 const struct cpumask
*(*target_cpus
)(void);
306 unsigned long (*check_apicid_used
)(physid_mask_t
*map
, int apicid
);
307 unsigned long (*check_apicid_present
)(int apicid
);
309 void (*vector_allocation_domain
)(int cpu
, struct cpumask
*retmask
);
310 void (*init_apic_ldr
)(void);
312 void (*ioapic_phys_id_map
)(physid_mask_t
*phys_map
, physid_mask_t
*retmap
);
314 void (*setup_apic_routing
)(void);
315 int (*multi_timer_check
)(int apic
, int irq
);
316 int (*cpu_present_to_apicid
)(int mps_cpu
);
317 void (*apicid_to_cpu_present
)(int phys_apicid
, physid_mask_t
*retmap
);
318 void (*setup_portio_remap
)(void);
319 int (*check_phys_apicid_present
)(int phys_apicid
);
320 void (*enable_apic_mode
)(void);
321 int (*phys_pkg_id
)(int cpuid_apic
, int index_msb
);
324 * When one of the next two hooks returns 1 the apic
325 * is switched to this. Essentially they are additional
328 int (*mps_oem_check
)(struct mpc_table
*mpc
, char *oem
, char *productid
);
330 unsigned int (*get_apic_id
)(unsigned long x
);
331 unsigned long (*set_apic_id
)(unsigned int id
);
332 unsigned long apic_id_mask
;
334 unsigned int (*cpu_mask_to_apicid
)(const struct cpumask
*cpumask
);
335 unsigned int (*cpu_mask_to_apicid_and
)(const struct cpumask
*cpumask
,
336 const struct cpumask
*andmask
);
339 void (*send_IPI_mask
)(const struct cpumask
*mask
, int vector
);
340 void (*send_IPI_mask_allbutself
)(const struct cpumask
*mask
,
342 void (*send_IPI_allbutself
)(int vector
);
343 void (*send_IPI_all
)(int vector
);
344 void (*send_IPI_self
)(int vector
);
346 /* wakeup_secondary_cpu */
347 int (*wakeup_secondary_cpu
)(int apicid
, unsigned long start_eip
);
349 int trampoline_phys_low
;
350 int trampoline_phys_high
;
352 void (*wait_for_init_deassert
)(atomic_t
*deassert
);
353 void (*smp_callin_clear_local_apic
)(void);
354 void (*inquire_remote_apic
)(int apicid
);
357 u32 (*read
)(u32 reg
);
358 void (*write
)(u32 reg
, u32 v
);
360 * ->eoi_write() has the same signature as ->write().
362 * Drivers can support both ->eoi_write() and ->write() by passing the same
363 * callback value. Kernel can override ->eoi_write() and fall back
366 void (*eoi_write
)(u32 reg
, u32 v
);
367 u64 (*icr_read
)(void);
368 void (*icr_write
)(u32 low
, u32 high
);
369 void (*wait_icr_idle
)(void);
370 u32 (*safe_wait_icr_idle
)(void);
374 * Called very early during boot from get_smp_config(). It should
375 * return the logical apicid. x86_[bios]_cpu_to_apicid is
376 * initialized before this function is called.
378 * If logical apicid can't be determined that early, the function
379 * may return BAD_APICID. Logical apicid will be configured after
380 * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity
381 * won't be applied properly during early boot in this case.
383 int (*x86_32_early_logical_apicid
)(int cpu
);
386 * Optional method called from setup_local_APIC() after logical
387 * apicid is guaranteed to be known to initialize apicid -> node
388 * mapping if NUMA initialization hasn't done so already. Don't
391 int (*x86_32_numa_cpu_node
)(int cpu
);
396 * Pointer to the local APIC driver in use on this system (there's
397 * always just one such driver in use - the kernel decides via an
398 * early probing process which one it picks - and then sticks to it):
400 extern struct apic
*apic
;
403 * APIC drivers are probed based on how they are listed in the .apicdrivers
404 * section. So the order is important and enforced by the ordering
405 * of different apic driver files in the Makefile.
407 * For the files having two apic drivers, we use apic_drivers()
408 * to enforce the order with in them.
410 #define apic_driver(sym) \
411 static struct apic *__apicdrivers_##sym __used \
412 __aligned(sizeof(struct apic *)) \
413 __section(.apicdrivers) = { &sym }
415 #define apic_drivers(sym1, sym2) \
416 static struct apic *__apicdrivers_##sym1##sym2[2] __used \
417 __aligned(sizeof(struct apic *)) \
418 __section(.apicdrivers) = { &sym1, &sym2 }
420 #ifdef CONFIG_X86_LOCAL_APIC
421 extern struct apic
*__apicdrivers
[], *__apicdrivers_end
[];
423 #define __apicdrivers ((struct apic **)NULL)
424 #define __apicdrivers_end ((struct apic **)NULL)
428 * APIC functionality to boot other CPUs - only used on SMP:
431 extern atomic_t init_deasserted
;
432 extern int wakeup_secondary_cpu_via_nmi(int apicid
, unsigned long start_eip
);
435 #ifdef CONFIG_X86_LOCAL_APIC
437 static inline u32
apic_read(u32 reg
)
439 return apic
->read(reg
);
442 static inline void apic_write(u32 reg
, u32 val
)
444 apic
->write(reg
, val
);
447 static inline void apic_eoi(void)
449 apic
->eoi_write(APIC_EOI
, APIC_EOI_ACK
);
452 static inline u64
apic_icr_read(void)
454 return apic
->icr_read();
457 static inline void apic_icr_write(u32 low
, u32 high
)
459 apic
->icr_write(low
, high
);
462 static inline void apic_wait_icr_idle(void)
464 apic
->wait_icr_idle();
467 static inline u32
safe_apic_wait_icr_idle(void)
469 return apic
->safe_wait_icr_idle();
472 extern void __init
apic_set_eoi_write(void (*eoi_write
)(u32 reg
, u32 v
));
474 #else /* CONFIG_X86_LOCAL_APIC */
476 static inline u32
apic_read(u32 reg
) { return 0; }
477 static inline void apic_write(u32 reg
, u32 val
) { }
478 static inline void apic_eoi(void) { }
479 static inline u64
apic_icr_read(void) { return 0; }
480 static inline void apic_icr_write(u32 low
, u32 high
) { }
481 static inline void apic_wait_icr_idle(void) { }
482 static inline u32
safe_apic_wait_icr_idle(void) { return 0; }
483 static inline void apic_set_eoi_write(void (*eoi_write
)(u32 reg
, u32 v
)) {}
485 #endif /* CONFIG_X86_LOCAL_APIC */
487 static inline void ack_APIC_irq(void)
490 * ack_APIC_irq() actually gets compiled as a single instruction
496 static inline unsigned default_get_apic_id(unsigned long x
)
498 unsigned int ver
= GET_APIC_VERSION(apic_read(APIC_LVR
));
500 if (APIC_XAPIC(ver
) || boot_cpu_has(X86_FEATURE_EXTD_APICID
))
501 return (x
>> 24) & 0xFF;
503 return (x
>> 24) & 0x0F;
507 * Warm reset vector default position:
509 #define DEFAULT_TRAMPOLINE_PHYS_LOW 0x467
510 #define DEFAULT_TRAMPOLINE_PHYS_HIGH 0x469
513 extern int default_acpi_madt_oem_check(char *, char *);
515 extern void apic_send_IPI_self(int vector
);
517 DECLARE_PER_CPU(int, x2apic_extra_bits
);
519 extern int default_cpu_present_to_apicid(int mps_cpu
);
520 extern int default_check_phys_apicid_present(int phys_apicid
);
523 static inline void default_wait_for_init_deassert(atomic_t
*deassert
)
525 while (!atomic_read(deassert
))
530 extern void generic_bigsmp_probe(void);
533 #ifdef CONFIG_X86_LOCAL_APIC
537 #define APIC_DFR_VALUE (APIC_DFR_FLAT)
539 static inline const struct cpumask
*default_target_cpus(void)
542 return cpu_online_mask
;
544 return cpumask_of(0);
548 DECLARE_EARLY_PER_CPU(u16
, x86_bios_cpu_apicid
);
551 static inline unsigned int read_apic_id(void)
555 reg
= apic_read(APIC_ID
);
557 return apic
->get_apic_id(reg
);
560 static inline int default_apic_id_valid(int apicid
)
562 return (apicid
< 255);
565 extern void default_setup_apic_routing(void);
567 extern struct apic apic_noop
;
571 static inline int noop_x86_32_early_logical_apicid(int cpu
)
577 * Set up the logical destination ID.
579 * Intel recommends to set DFR, LDR and TPR before enabling
580 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
581 * document number 292116). So here it goes...
583 extern void default_init_apic_ldr(void);
585 static inline int default_apic_id_registered(void)
587 return physid_isset(read_apic_id(), phys_cpu_present_map
);
590 static inline int default_phys_pkg_id(int cpuid_apic
, int index_msb
)
592 return cpuid_apic
>> index_msb
;
597 static inline unsigned int
598 default_cpu_mask_to_apicid(const struct cpumask
*cpumask
)
600 return cpumask_bits(cpumask
)[0] & APIC_ALL_CPUS
;
603 static inline unsigned int
604 default_cpu_mask_to_apicid_and(const struct cpumask
*cpumask
,
605 const struct cpumask
*andmask
)
607 unsigned long mask1
= cpumask_bits(cpumask
)[0];
608 unsigned long mask2
= cpumask_bits(andmask
)[0];
609 unsigned long mask3
= cpumask_bits(cpu_online_mask
)[0];
611 return (unsigned int)(mask1
& mask2
& mask3
);
614 static inline unsigned long default_check_apicid_used(physid_mask_t
*map
, int apicid
)
616 return physid_isset(apicid
, *map
);
619 static inline unsigned long default_check_apicid_present(int bit
)
621 return physid_isset(bit
, phys_cpu_present_map
);
624 static inline void default_ioapic_phys_id_map(physid_mask_t
*phys_map
, physid_mask_t
*retmap
)
629 static inline int __default_cpu_present_to_apicid(int mps_cpu
)
631 if (mps_cpu
< nr_cpu_ids
&& cpu_present(mps_cpu
))
632 return (int)per_cpu(x86_bios_cpu_apicid
, mps_cpu
);
638 __default_check_phys_apicid_present(int phys_apicid
)
640 return physid_isset(phys_apicid
, phys_cpu_present_map
);
644 static inline int default_cpu_present_to_apicid(int mps_cpu
)
646 return __default_cpu_present_to_apicid(mps_cpu
);
650 default_check_phys_apicid_present(int phys_apicid
)
652 return __default_check_phys_apicid_present(phys_apicid
);
655 extern int default_cpu_present_to_apicid(int mps_cpu
);
656 extern int default_check_phys_apicid_present(int phys_apicid
);
659 #endif /* CONFIG_X86_LOCAL_APIC */
661 #endif /* _ASM_X86_APIC_H */