arch/x86/include/asm/desc.h

   1 #ifndef _ASM_X86_DESC_H
   2 #define _ASM_X86_DESC_H
   3
   4 #include <asm/desc_defs.h>
   5 #include <asm/ldt.h>
   6 #include <asm/mmu.h>
   7 #include <asm/fixmap.h>
   8
   9 #include <linux/smp.h>
  10 #include <linux/percpu.h>
  11
  12 static inline void fill_ldt(struct desc_struct *desc, const struct user_desc *info)
  13 {
  14         desc->limit0            = info->limit & 0x0ffff;
  15
  16         desc->base0             = (info->base_addr & 0x0000ffff);
  17         desc->base1             = (info->base_addr & 0x00ff0000) >> 16;
  18
  19         desc->type              = (info->read_exec_only ^ 1) << 1;
  20         desc->type             |= info->contents << 2;
  21
  22         desc->s                 = 1;
  23         desc->dpl               = 0x3;
  24         desc->p                 = info->seg_not_present ^ 1;
  25         desc->limit             = (info->limit & 0xf0000) >> 16;
  26         desc->avl               = info->useable;
  27         desc->d                 = info->seg_32bit;
  28         desc->g                 = info->limit_in_pages;
  29
  30         desc->base2             = (info->base_addr & 0xff000000) >> 24;
  31         /*
  32          * Don't allow setting of the lm bit. It would confuse
  33          * user_64bit_mode and would get overridden by sysret anyway.
  34          */
  35         desc->l                 = 0;
  36 }
  37
  38 extern struct desc_ptr idt_descr;
  39 extern gate_desc idt_table[];
  40 extern const struct desc_ptr debug_idt_descr;
  41 extern gate_desc debug_idt_table[];
  42 extern pgprot_t pg_fixmap_gdt_flags;
  43
  44 struct gdt_page {
  45         struct desc_struct gdt[GDT_ENTRIES];
  46 } __attribute__((aligned(PAGE_SIZE)));
  47
  48 DECLARE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page);
  49
  50 /* Provide the original GDT */
  51 static inline struct desc_struct *get_cpu_gdt_rw(unsigned int cpu)
  52 {
  53         return per_cpu(gdt_page, cpu).gdt;
  54 }
  55
  56 /* Provide the current original GDT */
  57 static inline struct desc_struct *get_current_gdt_rw(void)
  58 {
  59         return this_cpu_ptr(&gdt_page)->gdt;
  60 }
  61
  62 /* Get the fixmap index for a specific processor */
  63 static inline unsigned int get_cpu_gdt_ro_index(int cpu)
  64 {
  65         return FIX_GDT_REMAP_BEGIN + cpu;
  66 }
  67
  68 /* Provide the fixmap address of the remapped GDT */
  69 static inline struct desc_struct *get_cpu_gdt_ro(int cpu)
  70 {
  71         unsigned int idx = get_cpu_gdt_ro_index(cpu);
  72         return (struct desc_struct *)__fix_to_virt(idx);
  73 }
  74
  75 /* Provide the current read-only GDT */
  76 static inline struct desc_struct *get_current_gdt_ro(void)
  77 {
  78         return get_cpu_gdt_ro(smp_processor_id());
  79 }
  80
  81 /* Provide the physical address of the GDT page. */
  82 static inline phys_addr_t get_cpu_gdt_paddr(unsigned int cpu)
  83 {
  84         return per_cpu_ptr_to_phys(get_cpu_gdt_rw(cpu));
  85 }
  86
  87 #ifdef CONFIG_X86_64
  88
  89 static inline void pack_gate(gate_desc *gate, unsigned type, unsigned long func,
  90                              unsigned dpl, unsigned ist, unsigned seg)
  91 {
  92         gate->offset_low        = PTR_LOW(func);
  93         gate->segment           = __KERNEL_CS;
  94         gate->ist               = ist;
  95         gate->p                 = 1;
  96         gate->dpl               = dpl;
  97         gate->zero0             = 0;
  98         gate->zero1             = 0;
  99         gate->type              = type;
 100         gate->offset_middle     = PTR_MIDDLE(func);
 101         gate->offset_high       = PTR_HIGH(func);
 102 }
 103
 104 #else
 105 static inline void pack_gate(gate_desc *gate, unsigned char type,
 106                              unsigned long base, unsigned dpl, unsigned flags,
 107                              unsigned short seg)
 108 {
 109         gate->a = (seg << 16) | (base & 0xffff);
 110         gate->b = (base & 0xffff0000) | (((0x80 | type | (dpl << 5)) & 0xff) << 8);
 111 }
 112
 113 #endif
 114
 115 static inline int desc_empty(const void *ptr)
 116 {
 117         const u32 *desc = ptr;
 118
 119         return !(desc[0] | desc[1]);
 120 }
 121
 122 #ifdef CONFIG_PARAVIRT
 123 #include <asm/paravirt.h>
 124 #else
 125 #define load_TR_desc()                          native_load_tr_desc()
 126 #define load_gdt(dtr)                           native_load_gdt(dtr)
 127 #define load_idt(dtr)                           native_load_idt(dtr)
 128 #define load_tr(tr)                             asm volatile("ltr %0"::"m" (tr))
 129 #define load_ldt(ldt)                           asm volatile("lldt %0"::"m" (ldt))
 130
 131 #define store_gdt(dtr)                          native_store_gdt(dtr)
 132 #define store_idt(dtr)                          native_store_idt(dtr)
 133 #define store_tr(tr)                            (tr = native_store_tr())
 134
 135 #define load_TLS(t, cpu)                        native_load_tls(t, cpu)
 136 #define set_ldt                                 native_set_ldt
 137
 138 #define write_ldt_entry(dt, entry, desc)        native_write_ldt_entry(dt, entry, desc)
 139 #define write_gdt_entry(dt, entry, desc, type)  native_write_gdt_entry(dt, entry, desc, type)
 140 #define write_idt_entry(dt, entry, g)           native_write_idt_entry(dt, entry, g)
 141
 142 static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries)
 143 {
 144 }
 145
 146 static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries)
 147 {
 148 }
 149 #endif  /* CONFIG_PARAVIRT */
 150
 151 #define store_ldt(ldt) asm("sldt %0" : "=m"(ldt))
 152
 153 static inline void native_write_idt_entry(gate_desc *idt, int entry, const gate_desc *gate)
 154 {
 155         memcpy(&idt[entry], gate, sizeof(*gate));
 156 }
 157
 158 static inline void native_write_ldt_entry(struct desc_struct *ldt, int entry, const void *desc)
 159 {
 160         memcpy(&ldt[entry], desc, 8);
 161 }
 162
 163 static inline void
 164 native_write_gdt_entry(struct desc_struct *gdt, int entry, const void *desc, int type)
 165 {
 166         unsigned int size;
 167
 168         switch (type) {
 169         case DESC_TSS:  size = sizeof(tss_desc);        break;
 170         case DESC_LDT:  size = sizeof(ldt_desc);        break;
 171         default:        size = sizeof(*gdt);            break;
 172         }
 173
 174         memcpy(&gdt[entry], desc, size);
 175 }
 176
 177 static inline void pack_descriptor(struct desc_struct *desc, unsigned long base,
 178                                    unsigned long limit, unsigned char type,
 179                                    unsigned char flags)
 180 {
 181         desc->a = ((base & 0xffff) << 16) | (limit & 0xffff);
 182         desc->b = (base & 0xff000000) | ((base & 0xff0000) >> 16) |
 183                 (limit & 0x000f0000) | ((type & 0xff) << 8) |
 184                 ((flags & 0xf) << 20);
 185         desc->p = 1;
 186 }
 187
 188
 189 static inline void set_tssldt_descriptor(void *d, unsigned long addr, unsigned type, unsigned size)
 190 {
 191 #ifdef CONFIG_X86_64
 192         struct ldttss_desc64 *desc = d;
 193
 194         memset(desc, 0, sizeof(*desc));
 195
 196         desc->limit0            = size & 0xFFFF;
 197         desc->base0             = PTR_LOW(addr);
 198         desc->base1             = PTR_MIDDLE(addr) & 0xFF;
 199         desc->type              = type;
 200         desc->p                 = 1;
 201         desc->limit1            = (size >> 16) & 0xF;
 202         desc->base2             = (PTR_MIDDLE(addr) >> 8) & 0xFF;
 203         desc->base3             = PTR_HIGH(addr);
 204 #else
 205         pack_descriptor((struct desc_struct *)d, addr, size, 0x80 | type, 0);
 206 #endif
 207 }
 208
 209 static inline void __set_tss_desc(unsigned cpu, unsigned int entry, void *addr)
 210 {
 211         struct desc_struct *d = get_cpu_gdt_rw(cpu);
 212         tss_desc tss;
 213
 214         set_tssldt_descriptor(&tss, (unsigned long)addr, DESC_TSS,
 215                               __KERNEL_TSS_LIMIT);
 216         write_gdt_entry(d, entry, &tss, DESC_TSS);
 217 }
 218
 219 #define set_tss_desc(cpu, addr) __set_tss_desc(cpu, GDT_ENTRY_TSS, addr)
 220
 221 static inline void native_set_ldt(const void *addr, unsigned int entries)
 222 {
 223         if (likely(entries == 0))
 224                 asm volatile("lldt %w0"::"q" (0));
 225         else {
 226                 unsigned cpu = smp_processor_id();
 227                 ldt_desc ldt;
 228
 229                 set_tssldt_descriptor(&ldt, (unsigned long)addr, DESC_LDT,
 230                                       entries * LDT_ENTRY_SIZE - 1);
 231                 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_LDT,
 232                                 &ldt, DESC_LDT);
 233                 asm volatile("lldt %w0"::"q" (GDT_ENTRY_LDT*8));
 234         }
 235 }
 236
 237 static inline void native_load_gdt(const struct desc_ptr *dtr)
 238 {
 239         asm volatile("lgdt %0"::"m" (*dtr));
 240 }
 241
 242 static inline void native_load_idt(const struct desc_ptr *dtr)
 243 {
 244         asm volatile("lidt %0"::"m" (*dtr));
 245 }
 246
 247 static inline void native_store_gdt(struct desc_ptr *dtr)
 248 {
 249         asm volatile("sgdt %0":"=m" (*dtr));
 250 }
 251
 252 static inline void native_store_idt(struct desc_ptr *dtr)
 253 {
 254         asm volatile("sidt %0":"=m" (*dtr));
 255 }
 256
 257 /*
 258  * The LTR instruction marks the TSS GDT entry as busy. On 64-bit, the GDT is
 259  * a read-only remapping. To prevent a page fault, the GDT is switched to the
 260  * original writeable version when needed.
 261  */
 262 #ifdef CONFIG_X86_64
 263 static inline void native_load_tr_desc(void)
 264 {
 265         struct desc_ptr gdt;
 266         int cpu = raw_smp_processor_id();
 267         bool restore = 0;
 268         struct desc_struct *fixmap_gdt;
 269
 270         native_store_gdt(&gdt);
 271         fixmap_gdt = get_cpu_gdt_ro(cpu);
 272
 273         /*
 274          * If the current GDT is the read-only fixmap, swap to the original
 275          * writeable version. Swap back at the end.
 276          */
 277         if (gdt.address == (unsigned long)fixmap_gdt) {
 278                 load_direct_gdt(cpu);
 279                 restore = 1;
 280         }
 281         asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8));
 282         if (restore)
 283                 load_fixmap_gdt(cpu);
 284 }
 285 #else
 286 static inline void native_load_tr_desc(void)
 287 {
 288         asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8));
 289 }
 290 #endif
 291
 292 static inline unsigned long native_store_tr(void)
 293 {
 294         unsigned long tr;
 295
 296         asm volatile("str %0":"=r" (tr));
 297
 298         return tr;
 299 }
 300
 301 static inline void native_load_tls(struct thread_struct *t, unsigned int cpu)
 302 {
 303         struct desc_struct *gdt = get_cpu_gdt_rw(cpu);
 304         unsigned int i;
 305
 306         for (i = 0; i < GDT_ENTRY_TLS_ENTRIES; i++)
 307                 gdt[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i];
 308 }
 309
 310 DECLARE_PER_CPU(bool, __tss_limit_invalid);
 311
 312 static inline void force_reload_TR(void)
 313 {
 314         struct desc_struct *d = get_current_gdt_rw();
 315         tss_desc tss;
 316
 317         memcpy(&tss, &d[GDT_ENTRY_TSS], sizeof(tss_desc));
 318
 319         /*
 320          * LTR requires an available TSS, and the TSS is currently
 321          * busy.  Make it be available so that LTR will work.
 322          */
 323         tss.type = DESC_TSS;
 324         write_gdt_entry(d, GDT_ENTRY_TSS, &tss, DESC_TSS);
 325
 326         load_TR_desc();
 327         this_cpu_write(__tss_limit_invalid, false);
 328 }
 329
 330 /*
 331  * Call this if you need the TSS limit to be correct, which should be the case
 332  * if and only if you have TIF_IO_BITMAP set or you're switching to a task
 333  * with TIF_IO_BITMAP set.
 334  */
 335 static inline void refresh_tss_limit(void)
 336 {
 337         DEBUG_LOCKS_WARN_ON(preemptible());
 338
 339         if (unlikely(this_cpu_read(__tss_limit_invalid)))
 340                 force_reload_TR();
 341 }
 342
 343 /*
 344  * If you do something evil that corrupts the cached TSS limit (I'm looking
 345  * at you, VMX exits), call this function.
 346  *
 347  * The optimization here is that the TSS limit only matters for Linux if the
 348  * IO bitmap is in use.  If the TSS limit gets forced to its minimum value,
 349  * everything works except that IO bitmap will be ignored and all CPL 3 IO
 350  * instructions will #GP, which is exactly what we want for normal tasks.
 351  */
 352 static inline void invalidate_tss_limit(void)
 353 {
 354         DEBUG_LOCKS_WARN_ON(preemptible());
 355
 356         if (unlikely(test_thread_flag(TIF_IO_BITMAP)))
 357                 force_reload_TR();
 358         else
 359                 this_cpu_write(__tss_limit_invalid, true);
 360 }
 361
 362 /* This intentionally ignores lm, since 32-bit apps don't have that field. */
 363 #define LDT_empty(info)                                 \
 364         ((info)->base_addr              == 0    &&      \
 365          (info)->limit                  == 0    &&      \
 366          (info)->contents               == 0    &&      \
 367          (info)->read_exec_only         == 1    &&      \
 368          (info)->seg_32bit              == 0    &&      \
 369          (info)->limit_in_pages         == 0    &&      \
 370          (info)->seg_not_present        == 1    &&      \
 371          (info)->useable                == 0)
 372
 373 /* Lots of programs expect an all-zero user_desc to mean "no segment at all". */
 374 static inline bool LDT_zero(const struct user_desc *info)
 375 {
 376         return (info->base_addr         == 0 &&
 377                 info->limit             == 0 &&
 378                 info->contents          == 0 &&
 379                 info->read_exec_only    == 0 &&
 380                 info->seg_32bit         == 0 &&
 381                 info->limit_in_pages    == 0 &&
 382                 info->seg_not_present   == 0 &&
 383                 info->useable           == 0);
 384 }
 385
 386 static inline void clear_LDT(void)
 387 {
 388         set_ldt(NULL, 0);
 389 }
 390
 391 static inline unsigned long get_desc_base(const struct desc_struct *desc)
 392 {
 393         return (unsigned)(desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24));
 394 }
 395
 396 static inline void set_desc_base(struct desc_struct *desc, unsigned long base)
 397 {
 398         desc->base0 = base & 0xffff;
 399         desc->base1 = (base >> 16) & 0xff;
 400         desc->base2 = (base >> 24) & 0xff;
 401 }
 402
 403 static inline unsigned long get_desc_limit(const struct desc_struct *desc)
 404 {
 405         return desc->limit0 | (desc->limit << 16);
 406 }
 407
 408 static inline void set_desc_limit(struct desc_struct *desc, unsigned long limit)
 409 {
 410         desc->limit0 = limit & 0xffff;
 411         desc->limit = (limit >> 16) & 0xf;
 412 }
 413
 414 #ifdef CONFIG_X86_64
 415 static inline void set_nmi_gate(int gate, void *addr)
 416 {
 417         gate_desc s;
 418
 419         pack_gate(&s, GATE_INTERRUPT, (unsigned long)addr, 0, 0, __KERNEL_CS);
 420         write_idt_entry(debug_idt_table, gate, &s);
 421 }
 422 #endif
 423
 424 #ifdef CONFIG_TRACING
 425 extern struct desc_ptr trace_idt_descr;
 426 extern gate_desc trace_idt_table[];
 427 static inline void write_trace_idt_entry(int entry, const gate_desc *gate)
 428 {
 429         write_idt_entry(trace_idt_table, entry, gate);
 430 }
 431
 432 static inline void _trace_set_gate(int gate, unsigned type, void *addr,
 433                                    unsigned dpl, unsigned ist, unsigned seg)
 434 {
 435         gate_desc s;
 436
 437         pack_gate(&s, type, (unsigned long)addr, dpl, ist, seg);
 438         /*
 439          * does not need to be atomic because it is only done once at
 440          * setup time
 441          */
 442         write_trace_idt_entry(gate, &s);
 443 }
 444 #else
 445 static inline void write_trace_idt_entry(int entry, const gate_desc *gate)
 446 {
 447 }
 448
 449 #define _trace_set_gate(gate, type, addr, dpl, ist, seg)
 450 #endif
 451
 452 static inline void _set_gate(int gate, unsigned type, void *addr,
 453                              unsigned dpl, unsigned ist, unsigned seg)
 454 {
 455         gate_desc s;
 456
 457         pack_gate(&s, type, (unsigned long)addr, dpl, ist, seg);
 458         /*
 459          * does not need to be atomic because it is only done once at
 460          * setup time
 461          */
 462         write_idt_entry(idt_table, gate, &s);
 463         write_trace_idt_entry(gate, &s);
 464 }
 465
 466 /*
 467  * This needs to use 'idt_table' rather than 'idt', and
 468  * thus use the _nonmapped_ version of the IDT, as the
 469  * Pentium F0 0F bugfix can have resulted in the mapped
 470  * IDT being write-protected.
 471  */
 472 #define set_intr_gate_notrace(n, addr)                                  \
 473         do {                                                            \
 474                 BUG_ON((unsigned)n > 0xFF);                             \
 475                 _set_gate(n, GATE_INTERRUPT, (void *)addr, 0, 0,        \
 476                           __KERNEL_CS);                                 \
 477         } while (0)
 478
 479 #define set_intr_gate(n, addr)                                          \
 480         do {                                                            \
 481                 set_intr_gate_notrace(n, addr);                         \
 482                 _trace_set_gate(n, GATE_INTERRUPT, (void *)trace_##addr,\
 483                                 0, 0, __KERNEL_CS);                     \
 484         } while (0)
 485
 486 extern int first_system_vector;
 487 /* used_vectors is BITMAP for irq is not managed by percpu vector_irq */
 488 extern unsigned long used_vectors[];
 489
 490 static inline void alloc_system_vector(int vector)
 491 {
 492         if (!test_bit(vector, used_vectors)) {
 493                 set_bit(vector, used_vectors);
 494                 if (first_system_vector > vector)
 495                         first_system_vector = vector;
 496         } else {
 497                 BUG();
 498         }
 499 }
 500
 501 #define alloc_intr_gate(n, addr)                                \
 502         do {                                                    \
 503                 alloc_system_vector(n);                         \
 504                 set_intr_gate(n, addr);                         \
 505         } while (0)
 506
 507 /*
 508  * This routine sets up an interrupt gate at directory privilege level 3.
 509  */
 510 static inline void set_system_intr_gate(unsigned int n, void *addr)
 511 {
 512         BUG_ON((unsigned)n > 0xFF);
 513         _set_gate(n, GATE_INTERRUPT, addr, 0x3, 0, __KERNEL_CS);
 514 }
 515
 516 static inline void set_system_trap_gate(unsigned int n, void *addr)
 517 {
 518         BUG_ON((unsigned)n > 0xFF);
 519         _set_gate(n, GATE_TRAP, addr, 0x3, 0, __KERNEL_CS);
 520 }
 521
 522 static inline void set_trap_gate(unsigned int n, void *addr)
 523 {
 524         BUG_ON((unsigned)n > 0xFF);
 525         _set_gate(n, GATE_TRAP, addr, 0, 0, __KERNEL_CS);
 526 }
 527
 528 static inline void set_task_gate(unsigned int n, unsigned int gdt_entry)
 529 {
 530         BUG_ON((unsigned)n > 0xFF);
 531         _set_gate(n, GATE_TASK, (void *)0, 0, 0, (gdt_entry<<3));
 532 }
 533
 534 static inline void set_intr_gate_ist(int n, void *addr, unsigned ist)
 535 {
 536         BUG_ON((unsigned)n > 0xFF);
 537         _set_gate(n, GATE_INTERRUPT, addr, 0, ist, __KERNEL_CS);
 538 }
 539
 540 static inline void set_system_intr_gate_ist(int n, void *addr, unsigned ist)
 541 {
 542         BUG_ON((unsigned)n > 0xFF);
 543         _set_gate(n, GATE_INTERRUPT, addr, 0x3, ist, __KERNEL_CS);
 544 }
 545
 546 #ifdef CONFIG_X86_64
 547 DECLARE_PER_CPU(u32, debug_idt_ctr);
 548 static inline bool is_debug_idt_enabled(void)
 549 {
 550         if (this_cpu_read(debug_idt_ctr))
 551                 return true;
 552
 553         return false;
 554 }
 555
 556 static inline void load_debug_idt(void)
 557 {
 558         load_idt((const struct desc_ptr *)&debug_idt_descr);
 559 }
 560 #else
 561 static inline bool is_debug_idt_enabled(void)
 562 {
 563         return false;
 564 }
 565
 566 static inline void load_debug_idt(void)
 567 {
 568 }
 569 #endif
 570
 571 #ifdef CONFIG_TRACING
 572 extern atomic_t trace_idt_ctr;
 573 static inline bool is_trace_idt_enabled(void)
 574 {
 575         if (atomic_read(&trace_idt_ctr))
 576                 return true;
 577
 578         return false;
 579 }
 580
 581 static inline void load_trace_idt(void)
 582 {
 583         load_idt((const struct desc_ptr *)&trace_idt_descr);
 584 }
 585 #else
 586 static inline bool is_trace_idt_enabled(void)
 587 {
 588         return false;
 589 }
 590
 591 static inline void load_trace_idt(void)
 592 {
 593 }
 594 #endif
 595
 596 /*
 597  * The load_current_idt() must be called with interrupts disabled
 598  * to avoid races. That way the IDT will always be set back to the expected
 599  * descriptor. It's also called when a CPU is being initialized, and
 600  * that doesn't need to disable interrupts, as nothing should be
 601  * bothering the CPU then.
 602  */
 603 static inline void load_current_idt(void)
 604 {
 605         if (is_debug_idt_enabled())
 606                 load_debug_idt();
 607         else if (is_trace_idt_enabled())
 608                 load_trace_idt();
 609         else
 610                 load_idt((const struct desc_ptr *)&idt_descr);
 611 }
 612 #endif /* _ASM_X86_DESC_H */