arch/x86/include/asm/desc.h

   1 #ifndef _ASM_X86_DESC_H
   2 #define _ASM_X86_DESC_H
   3
   4 #include <asm/desc_defs.h>
   5 #include <asm/ldt.h>
   6 #include <asm/mmu.h>
   7
   8 #include <linux/smp.h>
   9 #include <linux/percpu.h>
  10
  11 static inline void fill_ldt(struct desc_struct *desc, const struct user_desc *info)
  12 {
  13         desc->limit0            = info->limit & 0x0ffff;
  14
  15         desc->base0             = (info->base_addr & 0x0000ffff);
  16         desc->base1             = (info->base_addr & 0x00ff0000) >> 16;
  17
  18         desc->type              = (info->read_exec_only ^ 1) << 1;
  19         desc->type             |= info->contents << 2;
  20
  21         desc->s                 = 1;
  22         desc->dpl               = 0x3;
  23         desc->p                 = info->seg_not_present ^ 1;
  24         desc->limit             = (info->limit & 0xf0000) >> 16;
  25         desc->avl               = info->useable;
  26         desc->d                 = info->seg_32bit;
  27         desc->g                 = info->limit_in_pages;
  28
  29         desc->base2             = (info->base_addr & 0xff000000) >> 24;
  30         /*
  31          * Don't allow setting of the lm bit. It would confuse
  32          * user_64bit_mode and would get overridden by sysret anyway.
  33          */
  34         desc->l                 = 0;
  35 }
  36
  37 extern struct desc_ptr idt_descr;
  38 extern gate_desc idt_table[];
  39 extern const struct desc_ptr debug_idt_descr;
  40 extern gate_desc debug_idt_table[];
  41
  42 struct gdt_page {
  43         struct desc_struct gdt[GDT_ENTRIES];
  44 } __attribute__((aligned(PAGE_SIZE)));
  45
  46 DECLARE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page);
  47
  48 static inline struct desc_struct *get_cpu_gdt_table(unsigned int cpu)
  49 {
  50         return per_cpu(gdt_page, cpu).gdt;
  51 }
  52
  53 #ifdef CONFIG_X86_64
  54
  55 static inline void pack_gate(gate_desc *gate, unsigned type, unsigned long func,
  56                              unsigned dpl, unsigned ist, unsigned seg)
  57 {
  58         gate->offset_low        = PTR_LOW(func);
  59         gate->segment           = __KERNEL_CS;
  60         gate->ist               = ist;
  61         gate->p                 = 1;
  62         gate->dpl               = dpl;
  63         gate->zero0             = 0;
  64         gate->zero1             = 0;
  65         gate->type              = type;
  66         gate->offset_middle     = PTR_MIDDLE(func);
  67         gate->offset_high       = PTR_HIGH(func);
  68 }
  69
  70 #else
  71 static inline void pack_gate(gate_desc *gate, unsigned char type,
  72                              unsigned long base, unsigned dpl, unsigned flags,
  73                              unsigned short seg)
  74 {
  75         gate->a = (seg << 16) | (base & 0xffff);
  76         gate->b = (base & 0xffff0000) | (((0x80 | type | (dpl << 5)) & 0xff) << 8);
  77 }
  78
  79 #endif
  80
  81 static inline int desc_empty(const void *ptr)
  82 {
  83         const u32 *desc = ptr;
  84
  85         return !(desc[0] | desc[1]);
  86 }
  87
  88 #ifdef CONFIG_PARAVIRT
  89 #include <asm/paravirt.h>
  90 #else
  91 #define load_TR_desc()                          native_load_tr_desc()
  92 #define load_gdt(dtr)                           native_load_gdt(dtr)
  93 #define load_idt(dtr)                           native_load_idt(dtr)
  94 #define load_tr(tr)                             asm volatile("ltr %0"::"m" (tr))
  95 #define load_ldt(ldt)                           asm volatile("lldt %0"::"m" (ldt))
  96
  97 #define store_gdt(dtr)                          native_store_gdt(dtr)
  98 #define store_idt(dtr)                          native_store_idt(dtr)
  99 #define store_tr(tr)                            (tr = native_store_tr())
 100
 101 #define load_TLS(t, cpu)                        native_load_tls(t, cpu)
 102 #define set_ldt                                 native_set_ldt
 103
 104 #define write_ldt_entry(dt, entry, desc)        native_write_ldt_entry(dt, entry, desc)
 105 #define write_gdt_entry(dt, entry, desc, type)  native_write_gdt_entry(dt, entry, desc, type)
 106 #define write_idt_entry(dt, entry, g)           native_write_idt_entry(dt, entry, g)
 107
 108 static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries)
 109 {
 110 }
 111
 112 static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries)
 113 {
 114 }
 115 #endif  /* CONFIG_PARAVIRT */
 116
 117 #define store_ldt(ldt) asm("sldt %0" : "=m"(ldt))
 118
 119 static inline void native_write_idt_entry(gate_desc *idt, int entry, const gate_desc *gate)
 120 {
 121         memcpy(&idt[entry], gate, sizeof(*gate));
 122 }
 123
 124 static inline void native_write_ldt_entry(struct desc_struct *ldt, int entry, const void *desc)
 125 {
 126         memcpy(&ldt[entry], desc, 8);
 127 }
 128
 129 static inline void
 130 native_write_gdt_entry(struct desc_struct *gdt, int entry, const void *desc, int type)
 131 {
 132         unsigned int size;
 133
 134         switch (type) {
 135         case DESC_TSS:  size = sizeof(tss_desc);        break;
 136         case DESC_LDT:  size = sizeof(ldt_desc);        break;
 137         default:        size = sizeof(*gdt);            break;
 138         }
 139
 140         memcpy(&gdt[entry], desc, size);
 141 }
 142
 143 static inline void pack_descriptor(struct desc_struct *desc, unsigned long base,
 144                                    unsigned long limit, unsigned char type,
 145                                    unsigned char flags)
 146 {
 147         desc->a = ((base & 0xffff) << 16) | (limit & 0xffff);
 148         desc->b = (base & 0xff000000) | ((base & 0xff0000) >> 16) |
 149                 (limit & 0x000f0000) | ((type & 0xff) << 8) |
 150                 ((flags & 0xf) << 20);
 151         desc->p = 1;
 152 }
 153
 154
 155 static inline void set_tssldt_descriptor(void *d, unsigned long addr, unsigned type, unsigned size)
 156 {
 157 #ifdef CONFIG_X86_64
 158         struct ldttss_desc64 *desc = d;
 159
 160         memset(desc, 0, sizeof(*desc));
 161
 162         desc->limit0            = size & 0xFFFF;
 163         desc->base0             = PTR_LOW(addr);
 164         desc->base1             = PTR_MIDDLE(addr) & 0xFF;
 165         desc->type              = type;
 166         desc->p                 = 1;
 167         desc->limit1            = (size >> 16) & 0xF;
 168         desc->base2             = (PTR_MIDDLE(addr) >> 8) & 0xFF;
 169         desc->base3             = PTR_HIGH(addr);
 170 #else
 171         pack_descriptor((struct desc_struct *)d, addr, size, 0x80 | type, 0);
 172 #endif
 173 }
 174
 175 static inline void __set_tss_desc(unsigned cpu, unsigned int entry, void *addr)
 176 {
 177         struct desc_struct *d = get_cpu_gdt_table(cpu);
 178         tss_desc tss;
 179
 180         set_tssldt_descriptor(&tss, (unsigned long)addr, DESC_TSS,
 181                               __KERNEL_TSS_LIMIT);
 182         write_gdt_entry(d, entry, &tss, DESC_TSS);
 183 }
 184
 185 #define set_tss_desc(cpu, addr) __set_tss_desc(cpu, GDT_ENTRY_TSS, addr)
 186
 187 static inline void native_set_ldt(const void *addr, unsigned int entries)
 188 {
 189         if (likely(entries == 0))
 190                 asm volatile("lldt %w0"::"q" (0));
 191         else {
 192                 unsigned cpu = smp_processor_id();
 193                 ldt_desc ldt;
 194
 195                 set_tssldt_descriptor(&ldt, (unsigned long)addr, DESC_LDT,
 196                                       entries * LDT_ENTRY_SIZE - 1);
 197                 write_gdt_entry(get_cpu_gdt_table(cpu), GDT_ENTRY_LDT,
 198                                 &ldt, DESC_LDT);
 199                 asm volatile("lldt %w0"::"q" (GDT_ENTRY_LDT*8));
 200         }
 201 }
 202
 203 static inline void native_load_tr_desc(void)
 204 {
 205         asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8));
 206 }
 207
 208 static inline void force_reload_TR(void)
 209 {
 210         struct desc_struct *d = get_cpu_gdt_table(smp_processor_id());
 211         tss_desc tss;
 212
 213         memcpy(&tss, &d[GDT_ENTRY_TSS], sizeof(tss_desc));
 214
 215         /*
 216          * LTR requires an available TSS, and the TSS is currently
 217          * busy.  Make it be available so that LTR will work.
 218          */
 219         tss.type = DESC_TSS;
 220         write_gdt_entry(d, GDT_ENTRY_TSS, &tss, DESC_TSS);
 221
 222         load_TR_desc();
 223 }
 224
 225 DECLARE_PER_CPU(bool, need_tr_refresh);
 226
 227 static inline void refresh_TR(void)
 228 {
 229         DEBUG_LOCKS_WARN_ON(preemptible());
 230
 231         if (unlikely(this_cpu_read(need_tr_refresh))) {
 232                 force_reload_TR();
 233                 this_cpu_write(need_tr_refresh, false);
 234         }
 235 }
 236
 237 /*
 238  * If you do something evil that corrupts the cached TSS limit (I'm looking
 239  * at you, VMX exits), call this function.
 240  *
 241  * The optimization here is that the TSS limit only matters for Linux if the
 242  * IO bitmap is in use.  If the TSS limit gets forced to its minimum value,
 243  * everything works except that IO bitmap will be ignored and all CPL 3 IO
 244  * instructions will #GP, which is exactly what we want for normal tasks.
 245  */
 246 static inline void invalidate_tss_limit(void)
 247 {
 248         DEBUG_LOCKS_WARN_ON(preemptible());
 249
 250         if (unlikely(test_thread_flag(TIF_IO_BITMAP)))
 251                 force_reload_TR();
 252         else
 253                 this_cpu_write(need_tr_refresh, true);
 254 }
 255
 256 static inline void native_load_gdt(const struct desc_ptr *dtr)
 257 {
 258         asm volatile("lgdt %0"::"m" (*dtr));
 259 }
 260
 261 static inline void native_load_idt(const struct desc_ptr *dtr)
 262 {
 263         asm volatile("lidt %0"::"m" (*dtr));
 264 }
 265
 266 static inline void native_store_gdt(struct desc_ptr *dtr)
 267 {
 268         asm volatile("sgdt %0":"=m" (*dtr));
 269 }
 270
 271 static inline void native_store_idt(struct desc_ptr *dtr)
 272 {
 273         asm volatile("sidt %0":"=m" (*dtr));
 274 }
 275
 276 static inline unsigned long native_store_tr(void)
 277 {
 278         unsigned long tr;
 279
 280         asm volatile("str %0":"=r" (tr));
 281
 282         return tr;
 283 }
 284
 285 static inline void native_load_tls(struct thread_struct *t, unsigned int cpu)
 286 {
 287         struct desc_struct *gdt = get_cpu_gdt_table(cpu);
 288         unsigned int i;
 289
 290         for (i = 0; i < GDT_ENTRY_TLS_ENTRIES; i++)
 291                 gdt[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i];
 292 }
 293
 294 /* This intentionally ignores lm, since 32-bit apps don't have that field. */
 295 #define LDT_empty(info)                                 \
 296         ((info)->base_addr              == 0    &&      \
 297          (info)->limit                  == 0    &&      \
 298          (info)->contents               == 0    &&      \
 299          (info)->read_exec_only         == 1    &&      \
 300          (info)->seg_32bit              == 0    &&      \
 301          (info)->limit_in_pages         == 0    &&      \
 302          (info)->seg_not_present        == 1    &&      \
 303          (info)->useable                == 0)
 304
 305 /* Lots of programs expect an all-zero user_desc to mean "no segment at all". */
 306 static inline bool LDT_zero(const struct user_desc *info)
 307 {
 308         return (info->base_addr         == 0 &&
 309                 info->limit             == 0 &&
 310                 info->contents          == 0 &&
 311                 info->read_exec_only    == 0 &&
 312                 info->seg_32bit         == 0 &&
 313                 info->limit_in_pages    == 0 &&
 314                 info->seg_not_present   == 0 &&
 315                 info->useable           == 0);
 316 }
 317
 318 static inline void clear_LDT(void)
 319 {
 320         set_ldt(NULL, 0);
 321 }
 322
 323 static inline unsigned long get_desc_base(const struct desc_struct *desc)
 324 {
 325         return (unsigned)(desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24));
 326 }
 327
 328 static inline void set_desc_base(struct desc_struct *desc, unsigned long base)
 329 {
 330         desc->base0 = base & 0xffff;
 331         desc->base1 = (base >> 16) & 0xff;
 332         desc->base2 = (base >> 24) & 0xff;
 333 }
 334
 335 static inline unsigned long get_desc_limit(const struct desc_struct *desc)
 336 {
 337         return desc->limit0 | (desc->limit << 16);
 338 }
 339
 340 static inline void set_desc_limit(struct desc_struct *desc, unsigned long limit)
 341 {
 342         desc->limit0 = limit & 0xffff;
 343         desc->limit = (limit >> 16) & 0xf;
 344 }
 345
 346 #ifdef CONFIG_X86_64
 347 static inline void set_nmi_gate(int gate, void *addr)
 348 {
 349         gate_desc s;
 350
 351         pack_gate(&s, GATE_INTERRUPT, (unsigned long)addr, 0, 0, __KERNEL_CS);
 352         write_idt_entry(debug_idt_table, gate, &s);
 353 }
 354 #endif
 355
 356 #ifdef CONFIG_TRACING
 357 extern struct desc_ptr trace_idt_descr;
 358 extern gate_desc trace_idt_table[];
 359 static inline void write_trace_idt_entry(int entry, const gate_desc *gate)
 360 {
 361         write_idt_entry(trace_idt_table, entry, gate);
 362 }
 363
 364 static inline void _trace_set_gate(int gate, unsigned type, void *addr,
 365                                    unsigned dpl, unsigned ist, unsigned seg)
 366 {
 367         gate_desc s;
 368
 369         pack_gate(&s, type, (unsigned long)addr, dpl, ist, seg);
 370         /*
 371          * does not need to be atomic because it is only done once at
 372          * setup time
 373          */
 374         write_trace_idt_entry(gate, &s);
 375 }
 376 #else
 377 static inline void write_trace_idt_entry(int entry, const gate_desc *gate)
 378 {
 379 }
 380
 381 #define _trace_set_gate(gate, type, addr, dpl, ist, seg)
 382 #endif
 383
 384 static inline void _set_gate(int gate, unsigned type, void *addr,
 385                              unsigned dpl, unsigned ist, unsigned seg)
 386 {
 387         gate_desc s;
 388
 389         pack_gate(&s, type, (unsigned long)addr, dpl, ist, seg);
 390         /*
 391          * does not need to be atomic because it is only done once at
 392          * setup time
 393          */
 394         write_idt_entry(idt_table, gate, &s);
 395         write_trace_idt_entry(gate, &s);
 396 }
 397
 398 /*
 399  * This needs to use 'idt_table' rather than 'idt', and
 400  * thus use the _nonmapped_ version of the IDT, as the
 401  * Pentium F0 0F bugfix can have resulted in the mapped
 402  * IDT being write-protected.
 403  */
 404 #define set_intr_gate_notrace(n, addr)                                  \
 405         do {                                                            \
 406                 BUG_ON((unsigned)n > 0xFF);                             \
 407                 _set_gate(n, GATE_INTERRUPT, (void *)addr, 0, 0,        \
 408                           __KERNEL_CS);                                 \
 409         } while (0)
 410
 411 #define set_intr_gate(n, addr)                                          \
 412         do {                                                            \
 413                 set_intr_gate_notrace(n, addr);                         \
 414                 _trace_set_gate(n, GATE_INTERRUPT, (void *)trace_##addr,\
 415                                 0, 0, __KERNEL_CS);                     \
 416         } while (0)
 417
 418 extern int first_system_vector;
 419 /* used_vectors is BITMAP for irq is not managed by percpu vector_irq */
 420 extern unsigned long used_vectors[];
 421
 422 static inline void alloc_system_vector(int vector)
 423 {
 424         if (!test_bit(vector, used_vectors)) {
 425                 set_bit(vector, used_vectors);
 426                 if (first_system_vector > vector)
 427                         first_system_vector = vector;
 428         } else {
 429                 BUG();
 430         }
 431 }
 432
 433 #define alloc_intr_gate(n, addr)                                \
 434         do {                                                    \
 435                 alloc_system_vector(n);                         \
 436                 set_intr_gate(n, addr);                         \
 437         } while (0)
 438
 439 /*
 440  * This routine sets up an interrupt gate at directory privilege level 3.
 441  */
 442 static inline void set_system_intr_gate(unsigned int n, void *addr)
 443 {
 444         BUG_ON((unsigned)n > 0xFF);
 445         _set_gate(n, GATE_INTERRUPT, addr, 0x3, 0, __KERNEL_CS);
 446 }
 447
 448 static inline void set_system_trap_gate(unsigned int n, void *addr)
 449 {
 450         BUG_ON((unsigned)n > 0xFF);
 451         _set_gate(n, GATE_TRAP, addr, 0x3, 0, __KERNEL_CS);
 452 }
 453
 454 static inline void set_trap_gate(unsigned int n, void *addr)
 455 {
 456         BUG_ON((unsigned)n > 0xFF);
 457         _set_gate(n, GATE_TRAP, addr, 0, 0, __KERNEL_CS);
 458 }
 459
 460 static inline void set_task_gate(unsigned int n, unsigned int gdt_entry)
 461 {
 462         BUG_ON((unsigned)n > 0xFF);
 463         _set_gate(n, GATE_TASK, (void *)0, 0, 0, (gdt_entry<<3));
 464 }
 465
 466 static inline void set_intr_gate_ist(int n, void *addr, unsigned ist)
 467 {
 468         BUG_ON((unsigned)n > 0xFF);
 469         _set_gate(n, GATE_INTERRUPT, addr, 0, ist, __KERNEL_CS);
 470 }
 471
 472 static inline void set_system_intr_gate_ist(int n, void *addr, unsigned ist)
 473 {
 474         BUG_ON((unsigned)n > 0xFF);
 475         _set_gate(n, GATE_INTERRUPT, addr, 0x3, ist, __KERNEL_CS);
 476 }
 477
 478 #ifdef CONFIG_X86_64
 479 DECLARE_PER_CPU(u32, debug_idt_ctr);
 480 static inline bool is_debug_idt_enabled(void)
 481 {
 482         if (this_cpu_read(debug_idt_ctr))
 483                 return true;
 484
 485         return false;
 486 }
 487
 488 static inline void load_debug_idt(void)
 489 {
 490         load_idt((const struct desc_ptr *)&debug_idt_descr);
 491 }
 492 #else
 493 static inline bool is_debug_idt_enabled(void)
 494 {
 495         return false;
 496 }
 497
 498 static inline void load_debug_idt(void)
 499 {
 500 }
 501 #endif
 502
 503 #ifdef CONFIG_TRACING
 504 extern atomic_t trace_idt_ctr;
 505 static inline bool is_trace_idt_enabled(void)
 506 {
 507         if (atomic_read(&trace_idt_ctr))
 508                 return true;
 509
 510         return false;
 511 }
 512
 513 static inline void load_trace_idt(void)
 514 {
 515         load_idt((const struct desc_ptr *)&trace_idt_descr);
 516 }
 517 #else
 518 static inline bool is_trace_idt_enabled(void)
 519 {
 520         return false;
 521 }
 522
 523 static inline void load_trace_idt(void)
 524 {
 525 }
 526 #endif
 527
 528 /*
 529  * The load_current_idt() must be called with interrupts disabled
 530  * to avoid races. That way the IDT will always be set back to the expected
 531  * descriptor. It's also called when a CPU is being initialized, and
 532  * that doesn't need to disable interrupts, as nothing should be
 533  * bothering the CPU then.
 534  */
 535 static inline void load_current_idt(void)
 536 {
 537         if (is_debug_idt_enabled())
 538                 load_debug_idt();
 539         else if (is_trace_idt_enabled())
 540                 load_trace_idt();
 541         else
 542                 load_idt((const struct desc_ptr *)&idt_descr);
 543 }
 544 #endif /* _ASM_X86_DESC_H */