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1 #ifndef _ASM_X86_DMA_MAPPING_H
2 #define _ASM_X86_DMA_MAPPING_H
3
4 /*
5 * IOMMU interface. See Documentation/DMA-API-HOWTO.txt and
6 * Documentation/DMA-API.txt for documentation.
7 */
8
9 #include <linux/kmemcheck.h>
10 #include <linux/scatterlist.h>
11 #include <linux/dma-debug.h>
12 #include <linux/dma-attrs.h>
13 #include <asm/io.h>
14 #include <asm/swiotlb.h>
15 #include <asm-generic/dma-coherent.h>
16
17 #ifdef CONFIG_ISA
18 # define ISA_DMA_BIT_MASK DMA_BIT_MASK(24)
19 #else
20 # define ISA_DMA_BIT_MASK DMA_BIT_MASK(32)
21 #endif
22
23 #define DMA_ERROR_CODE 0
24
25 extern int iommu_merge;
26 extern struct device x86_dma_fallback_dev;
27 extern int panic_on_overflow;
28
29 extern struct dma_map_ops *dma_ops;
30
31 static inline struct dma_map_ops *get_dma_ops(struct device *dev)
32 {
33 #ifdef CONFIG_X86_32
34 return dma_ops;
35 #else
36 if (unlikely(!dev) || !dev->archdata.dma_ops)
37 return dma_ops;
38 else
39 return dev->archdata.dma_ops;
40 #endif
41 }
42
43 #include <asm-generic/dma-mapping-common.h>
44
45 /* Make sure we keep the same behaviour */
46 static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
47 {
48 struct dma_map_ops *ops = get_dma_ops(dev);
49 if (ops->mapping_error)
50 return ops->mapping_error(dev, dma_addr);
51
52 return (dma_addr == DMA_ERROR_CODE);
53 }
54
55 #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
56 #define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
57
58 extern int dma_supported(struct device *hwdev, u64 mask);
59 extern int dma_set_mask(struct device *dev, u64 mask);
60
61 extern void *dma_generic_alloc_coherent(struct device *dev, size_t size,
62 dma_addr_t *dma_addr, gfp_t flag);
63
64 static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
65 {
66 if (!dev->dma_mask)
67 return 0;
68
69 return addr + size - 1 <= *dev->dma_mask;
70 }
71
72 static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
73 {
74 return paddr;
75 }
76
77 static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
78 {
79 return daddr;
80 }
81
82 static inline void
83 dma_cache_sync(struct device *dev, void *vaddr, size_t size,
84 enum dma_data_direction dir)
85 {
86 flush_write_buffers();
87 }
88
89 static inline unsigned long dma_alloc_coherent_mask(struct device *dev,
90 gfp_t gfp)
91 {
92 unsigned long dma_mask = 0;
93
94 dma_mask = dev->coherent_dma_mask;
95 if (!dma_mask)
96 dma_mask = (gfp & GFP_DMA) ? DMA_BIT_MASK(24) : DMA_BIT_MASK(32);
97
98 return dma_mask;
99 }
100
101 static inline gfp_t dma_alloc_coherent_gfp_flags(struct device *dev, gfp_t gfp)
102 {
103 unsigned long dma_mask = dma_alloc_coherent_mask(dev, gfp);
104
105 if (dma_mask <= DMA_BIT_MASK(24))
106 gfp |= GFP_DMA;
107 #ifdef CONFIG_X86_64
108 if (dma_mask <= DMA_BIT_MASK(32) && !(gfp & GFP_DMA))
109 gfp |= GFP_DMA32;
110 #endif
111 return gfp;
112 }
113
114 static inline void *
115 dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
116 gfp_t gfp)
117 {
118 struct dma_map_ops *ops = get_dma_ops(dev);
119 void *memory;
120
121 gfp &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
122
123 if (dma_alloc_from_coherent(dev, size, dma_handle, &memory))
124 return memory;
125
126 if (!dev)
127 dev = &x86_dma_fallback_dev;
128
129 if (!is_device_dma_capable(dev))
130 return NULL;
131
132 if (!ops->alloc_coherent)
133 return NULL;
134
135 memory = ops->alloc_coherent(dev, size, dma_handle,
136 dma_alloc_coherent_gfp_flags(dev, gfp));
137 debug_dma_alloc_coherent(dev, size, *dma_handle, memory);
138
139 return memory;
140 }
141
142 static inline void dma_free_coherent(struct device *dev, size_t size,
143 void *vaddr, dma_addr_t bus)
144 {
145 struct dma_map_ops *ops = get_dma_ops(dev);
146
147 WARN_ON(irqs_disabled()); /* for portability */
148
149 if (dma_release_from_coherent(dev, get_order(size), vaddr))
150 return;
151
152 debug_dma_free_coherent(dev, size, vaddr, bus);
153 if (ops->free_coherent)
154 ops->free_coherent(dev, size, vaddr, bus);
155 }
156
157 #endif