arch/x86/include/asm/dma.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * linux/include/asm/dma.h: Defines for using and allocating dma channels.
   4  * Written by Hennus Bergman, 1992.
   5  * High DMA channel support & info by Hannu Savolainen
   6  * and John Boyd, Nov. 1992.
   7  */
   8
   9 #ifndef _ASM_X86_DMA_H
  10 #define _ASM_X86_DMA_H
  11
  12 #include <linux/spinlock.h>     /* And spinlocks */
  13 #include <asm/io.h>             /* need byte IO */
  14
  15 #ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
  16 #define dma_outb        outb_p
  17 #else
  18 #define dma_outb        outb
  19 #endif
  20
  21 #define dma_inb         inb
  22
  23 /*
  24  * NOTES about DMA transfers:
  25  *
  26  *  controller 1: channels 0-3, byte operations, ports 00-1F
  27  *  controller 2: channels 4-7, word operations, ports C0-DF
  28  *
  29  *  - ALL registers are 8 bits only, regardless of transfer size
  30  *  - channel 4 is not used - cascades 1 into 2.
  31  *  - channels 0-3 are byte - addresses/counts are for physical bytes
  32  *  - channels 5-7 are word - addresses/counts are for physical words
  33  *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
  34  *  - transfer count loaded to registers is 1 less than actual count
  35  *  - controller 2 offsets are all even (2x offsets for controller 1)
  36  *  - page registers for 5-7 don't use data bit 0, represent 128K pages
  37  *  - page registers for 0-3 use bit 0, represent 64K pages
  38  *
  39  * DMA transfers are limited to the lower 16MB of _physical_ memory.
  40  * Note that addresses loaded into registers must be _physical_ addresses,
  41  * not logical addresses (which may differ if paging is active).
  42  *
  43  *  Address mapping for channels 0-3:
  44  *
  45  *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
  46  *    |  ...  |   |  ... |   |  ... |
  47  *    |  ...  |   |  ... |   |  ... |
  48  *    |  ...  |   |  ... |   |  ... |
  49  *   P7  ...  P0  A7 ... A0  A7 ... A0
  50  * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
  51  *
  52  *  Address mapping for channels 5-7:
  53  *
  54  *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
  55  *    |  ...  |   \   \   ... \  \  \  ... \  \
  56  *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
  57  *    |  ...  |     \   \   ... \  \  \  ... \
  58  *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0
  59  * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
  60  *
  61  * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
  62  * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
  63  * the hardware level, so odd-byte transfers aren't possible).
  64  *
  65  * Transfer count (_not # bytes_) is limited to 64K, represented as actual
  66  * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
  67  * and up to 128K bytes may be transferred on channels 5-7 in one operation.
  68  *
  69  */
  70
  71 #define MAX_DMA_CHANNELS        8
  72
  73 /* 16MB ISA DMA zone */
  74 #define MAX_DMA_PFN   ((16UL * 1024 * 1024) >> PAGE_SHIFT)
  75
  76 /* 4GB broken PCI/AGP hardware bus master zone */
  77 #define MAX_DMA32_PFN ((4UL * 1024 * 1024 * 1024) >> PAGE_SHIFT)
  78
  79 #ifdef CONFIG_X86_32
  80 /* The maximum address that we can perform a DMA transfer to on this platform */
  81 #define MAX_DMA_ADDRESS      (PAGE_OFFSET + 0x1000000)
  82 #else
  83 /* Compat define for old dma zone */
  84 #define MAX_DMA_ADDRESS ((unsigned long)__va(MAX_DMA_PFN << PAGE_SHIFT))
  85 #endif
  86
  87 /* 8237 DMA controllers */
  88 #define IO_DMA1_BASE    0x00    /* 8 bit slave DMA, channels 0..3 */
  89 #define IO_DMA2_BASE    0xC0    /* 16 bit master DMA, ch 4(=slave input)..7 */
  90
  91 /* DMA controller registers */
  92 #define DMA1_CMD_REG            0x08    /* command register (w) */
  93 #define DMA1_STAT_REG           0x08    /* status register (r) */
  94 #define DMA1_REQ_REG            0x09    /* request register (w) */
  95 #define DMA1_MASK_REG           0x0A    /* single-channel mask (w) */
  96 #define DMA1_MODE_REG           0x0B    /* mode register (w) */
  97 #define DMA1_CLEAR_FF_REG       0x0C    /* clear pointer flip-flop (w) */
  98 #define DMA1_TEMP_REG           0x0D    /* Temporary Register (r) */
  99 #define DMA1_RESET_REG          0x0D    /* Master Clear (w) */
 100 #define DMA1_CLR_MASK_REG       0x0E    /* Clear Mask */
 101 #define DMA1_MASK_ALL_REG       0x0F    /* all-channels mask (w) */
 102
 103 #define DMA2_CMD_REG            0xD0    /* command register (w) */
 104 #define DMA2_STAT_REG           0xD0    /* status register (r) */
 105 #define DMA2_REQ_REG            0xD2    /* request register (w) */
 106 #define DMA2_MASK_REG           0xD4    /* single-channel mask (w) */
 107 #define DMA2_MODE_REG           0xD6    /* mode register (w) */
 108 #define DMA2_CLEAR_FF_REG       0xD8    /* clear pointer flip-flop (w) */
 109 #define DMA2_TEMP_REG           0xDA    /* Temporary Register (r) */
 110 #define DMA2_RESET_REG          0xDA    /* Master Clear (w) */
 111 #define DMA2_CLR_MASK_REG       0xDC    /* Clear Mask */
 112 #define DMA2_MASK_ALL_REG       0xDE    /* all-channels mask (w) */
 113
 114 #define DMA_ADDR_0              0x00    /* DMA address registers */
 115 #define DMA_ADDR_1              0x02
 116 #define DMA_ADDR_2              0x04
 117 #define DMA_ADDR_3              0x06
 118 #define DMA_ADDR_4              0xC0
 119 #define DMA_ADDR_5              0xC4
 120 #define DMA_ADDR_6              0xC8
 121 #define DMA_ADDR_7              0xCC
 122
 123 #define DMA_CNT_0               0x01    /* DMA count registers */
 124 #define DMA_CNT_1               0x03
 125 #define DMA_CNT_2               0x05
 126 #define DMA_CNT_3               0x07
 127 #define DMA_CNT_4               0xC2
 128 #define DMA_CNT_5               0xC6
 129 #define DMA_CNT_6               0xCA
 130 #define DMA_CNT_7               0xCE
 131
 132 #define DMA_PAGE_0              0x87    /* DMA page registers */
 133 #define DMA_PAGE_1              0x83
 134 #define DMA_PAGE_2              0x81
 135 #define DMA_PAGE_3              0x82
 136 #define DMA_PAGE_5              0x8B
 137 #define DMA_PAGE_6              0x89
 138 #define DMA_PAGE_7              0x8A
 139
 140 /* I/O to memory, no autoinit, increment, single mode */
 141 #define DMA_MODE_READ           0x44
 142 /* memory to I/O, no autoinit, increment, single mode */
 143 #define DMA_MODE_WRITE          0x48
 144 /* pass thru DREQ->HRQ, DACK<-HLDA only */
 145 #define DMA_MODE_CASCADE        0xC0
 146
 147 #define DMA_AUTOINIT            0x10
 148
 149
 150 #ifdef CONFIG_ISA_DMA_API
 151 extern spinlock_t  dma_spin_lock;
 152
 153 static inline unsigned long claim_dma_lock(void)
 154 {
 155         unsigned long flags;
 156         spin_lock_irqsave(&dma_spin_lock, flags);
 157         return flags;
 158 }
 159
 160 static inline void release_dma_lock(unsigned long flags)
 161 {
 162         spin_unlock_irqrestore(&dma_spin_lock, flags);
 163 }
 164 #endif /* CONFIG_ISA_DMA_API */
 165
 166 /* enable/disable a specific DMA channel */
 167 static inline void enable_dma(unsigned int dmanr)
 168 {
 169         if (dmanr <= 3)
 170                 dma_outb(dmanr, DMA1_MASK_REG);
 171         else
 172                 dma_outb(dmanr & 3, DMA2_MASK_REG);
 173 }
 174
 175 static inline void disable_dma(unsigned int dmanr)
 176 {
 177         if (dmanr <= 3)
 178                 dma_outb(dmanr | 4, DMA1_MASK_REG);
 179         else
 180                 dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
 181 }
 182
 183 /* Clear the 'DMA Pointer Flip Flop'.
 184  * Write 0 for LSB/MSB, 1 for MSB/LSB access.
 185  * Use this once to initialize the FF to a known state.
 186  * After that, keep track of it. :-)
 187  * --- In order to do that, the DMA routines below should ---
 188  * --- only be used while holding the DMA lock ! ---
 189  */
 190 static inline void clear_dma_ff(unsigned int dmanr)
 191 {
 192         if (dmanr <= 3)
 193                 dma_outb(0, DMA1_CLEAR_FF_REG);
 194         else
 195                 dma_outb(0, DMA2_CLEAR_FF_REG);
 196 }
 197
 198 /* set mode (above) for a specific DMA channel */
 199 static inline void set_dma_mode(unsigned int dmanr, char mode)
 200 {
 201         if (dmanr <= 3)
 202                 dma_outb(mode | dmanr, DMA1_MODE_REG);
 203         else
 204                 dma_outb(mode | (dmanr & 3), DMA2_MODE_REG);
 205 }
 206
 207 /* Set only the page register bits of the transfer address.
 208  * This is used for successive transfers when we know the contents of
 209  * the lower 16 bits of the DMA current address register, but a 64k boundary
 210  * may have been crossed.
 211  */
 212 static inline void set_dma_page(unsigned int dmanr, char pagenr)
 213 {
 214         switch (dmanr) {
 215         case 0:
 216                 dma_outb(pagenr, DMA_PAGE_0);
 217                 break;
 218         case 1:
 219                 dma_outb(pagenr, DMA_PAGE_1);
 220                 break;
 221         case 2:
 222                 dma_outb(pagenr, DMA_PAGE_2);
 223                 break;
 224         case 3:
 225                 dma_outb(pagenr, DMA_PAGE_3);
 226                 break;
 227         case 5:
 228                 dma_outb(pagenr & 0xfe, DMA_PAGE_5);
 229                 break;
 230         case 6:
 231                 dma_outb(pagenr & 0xfe, DMA_PAGE_6);
 232                 break;
 233         case 7:
 234                 dma_outb(pagenr & 0xfe, DMA_PAGE_7);
 235                 break;
 236         }
 237 }
 238
 239
 240 /* Set transfer address & page bits for specific DMA channel.
 241  * Assumes dma flipflop is clear.
 242  */
 243 static inline void set_dma_addr(unsigned int dmanr, unsigned int a)
 244 {
 245         set_dma_page(dmanr, a>>16);
 246         if (dmanr <= 3)  {
 247                 dma_outb(a & 0xff, ((dmanr & 3) << 1) + IO_DMA1_BASE);
 248                 dma_outb((a >> 8) & 0xff, ((dmanr & 3) << 1) + IO_DMA1_BASE);
 249         }  else  {
 250                 dma_outb((a >> 1) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
 251                 dma_outb((a >> 9) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
 252         }
 253 }
 254
 255
 256 /* Set transfer size (max 64k for DMA0..3, 128k for DMA5..7) for
 257  * a specific DMA channel.
 258  * You must ensure the parameters are valid.
 259  * NOTE: from a manual: "the number of transfers is one more
 260  * than the initial word count"! This is taken into account.
 261  * Assumes dma flip-flop is clear.
 262  * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
 263  */
 264 static inline void set_dma_count(unsigned int dmanr, unsigned int count)
 265 {
 266         count--;
 267         if (dmanr <= 3)  {
 268                 dma_outb(count & 0xff, ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
 269                 dma_outb((count >> 8) & 0xff,
 270                          ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
 271         } else {
 272                 dma_outb((count >> 1) & 0xff,
 273                          ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
 274                 dma_outb((count >> 9) & 0xff,
 275                          ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
 276         }
 277 }
 278
 279
 280 /* Get DMA residue count. After a DMA transfer, this
 281  * should return zero. Reading this while a DMA transfer is
 282  * still in progress will return unpredictable results.
 283  * If called before the channel has been used, it may return 1.
 284  * Otherwise, it returns the number of _bytes_ left to transfer.
 285  *
 286  * Assumes DMA flip-flop is clear.
 287  */
 288 static inline int get_dma_residue(unsigned int dmanr)
 289 {
 290         unsigned int io_port;
 291         /* using short to get 16-bit wrap around */
 292         unsigned short count;
 293
 294         io_port = (dmanr <= 3) ? ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE
 295                 : ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE;
 296
 297         count = 1 + dma_inb(io_port);
 298         count += dma_inb(io_port) << 8;
 299
 300         return (dmanr <= 3) ? count : (count << 1);
 301 }
 302
 303
 304 /* These are in kernel/dma.c because x86 uses CONFIG_GENERIC_ISA_DMA */
 305 #ifdef CONFIG_ISA_DMA_API
 306 extern int request_dma(unsigned int dmanr, const char *device_id);
 307 extern void free_dma(unsigned int dmanr);
 308 #endif
 309
 310 /* From PCI */
 311
 312 #ifdef CONFIG_PCI
 313 extern int isa_dma_bridge_buggy;
 314 #else
 315 #define isa_dma_bridge_buggy    (0)
 316 #endif
 317
 318 #endif /* _ASM_X86_DMA_H */