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1 /*
2 * Copyright (C) 1994 Linus Torvalds
3 *
4 * Pentium III FXSR, SSE support
5 * General FPU state handling cleanups
6 * Gareth Hughes <gareth@valinux.com>, May 2000
7 * x86-64 work by Andi Kleen 2002
8 */
9
10 #ifndef _ASM_X86_FPU_INTERNAL_H
11 #define _ASM_X86_FPU_INTERNAL_H
12
13 #include <linux/compat.h>
14 #include <linux/sched.h>
15 #include <linux/slab.h>
16
17 #include <asm/user.h>
18 #include <asm/fpu/api.h>
19 #include <asm/fpu/xstate.h>
20
21 /*
22 * High level FPU state handling functions:
23 */
24 extern void fpu__activate_curr(struct fpu *fpu);
25 extern void fpu__activate_fpstate_read(struct fpu *fpu);
26 extern void fpu__activate_fpstate_write(struct fpu *fpu);
27 extern void fpu__save(struct fpu *fpu);
28 extern void fpu__restore(struct fpu *fpu);
29 extern int fpu__restore_sig(void __user *buf, int ia32_frame);
30 extern void fpu__drop(struct fpu *fpu);
31 extern int fpu__copy(struct fpu *dst_fpu, struct fpu *src_fpu);
32 extern void fpu__clear(struct fpu *fpu);
33 extern int fpu__exception_code(struct fpu *fpu, int trap_nr);
34 extern int dump_fpu(struct pt_regs *ptregs, struct user_i387_struct *fpstate);
35
36 /*
37 * Boot time FPU initialization functions:
38 */
39 extern void fpu__init_cpu(void);
40 extern void fpu__init_system_xstate(void);
41 extern void fpu__init_cpu_xstate(void);
42 extern void fpu__init_system(struct cpuinfo_x86 *c);
43 extern void fpu__init_check_bugs(void);
44 extern void fpu__resume_cpu(void);
45 extern u64 fpu__get_supported_xfeatures_mask(void);
46
47 /*
48 * Debugging facility:
49 */
50 #ifdef CONFIG_X86_DEBUG_FPU
51 # define WARN_ON_FPU(x) WARN_ON_ONCE(x)
52 #else
53 # define WARN_ON_FPU(x) ({ (void)(x); 0; })
54 #endif
55
56 /*
57 * FPU related CPU feature flag helper routines:
58 */
59 static __always_inline __pure bool use_eager_fpu(void)
60 {
61 return static_cpu_has_safe(X86_FEATURE_EAGER_FPU);
62 }
63
64 static __always_inline __pure bool use_xsaveopt(void)
65 {
66 return static_cpu_has_safe(X86_FEATURE_XSAVEOPT);
67 }
68
69 static __always_inline __pure bool use_xsave(void)
70 {
71 return static_cpu_has_safe(X86_FEATURE_XSAVE);
72 }
73
74 static __always_inline __pure bool use_fxsr(void)
75 {
76 return static_cpu_has_safe(X86_FEATURE_FXSR);
77 }
78
79 /*
80 * fpstate handling functions:
81 */
82
83 extern union fpregs_state init_fpstate;
84
85 extern void fpstate_init(union fpregs_state *state);
86 #ifdef CONFIG_MATH_EMULATION
87 extern void fpstate_init_soft(struct swregs_state *soft);
88 #else
89 static inline void fpstate_init_soft(struct swregs_state *soft) {}
90 #endif
91 static inline void fpstate_init_fxstate(struct fxregs_state *fx)
92 {
93 fx->cwd = 0x37f;
94 fx->mxcsr = MXCSR_DEFAULT;
95 }
96 extern void fpstate_sanitize_xstate(struct fpu *fpu);
97
98 #define user_insn(insn, output, input...) \
99 ({ \
100 int err; \
101 asm volatile(ASM_STAC "\n" \
102 "1:" #insn "\n\t" \
103 "2: " ASM_CLAC "\n" \
104 ".section .fixup,\"ax\"\n" \
105 "3: movl $-1,%[err]\n" \
106 " jmp 2b\n" \
107 ".previous\n" \
108 _ASM_EXTABLE(1b, 3b) \
109 : [err] "=r" (err), output \
110 : "0"(0), input); \
111 err; \
112 })
113
114 #define check_insn(insn, output, input...) \
115 ({ \
116 int err; \
117 asm volatile("1:" #insn "\n\t" \
118 "2:\n" \
119 ".section .fixup,\"ax\"\n" \
120 "3: movl $-1,%[err]\n" \
121 " jmp 2b\n" \
122 ".previous\n" \
123 _ASM_EXTABLE(1b, 3b) \
124 : [err] "=r" (err), output \
125 : "0"(0), input); \
126 err; \
127 })
128
129 static inline int copy_fregs_to_user(struct fregs_state __user *fx)
130 {
131 return user_insn(fnsave %[fx]; fwait, [fx] "=m" (*fx), "m" (*fx));
132 }
133
134 static inline int copy_fxregs_to_user(struct fxregs_state __user *fx)
135 {
136 if (config_enabled(CONFIG_X86_32))
137 return user_insn(fxsave %[fx], [fx] "=m" (*fx), "m" (*fx));
138 else if (config_enabled(CONFIG_AS_FXSAVEQ))
139 return user_insn(fxsaveq %[fx], [fx] "=m" (*fx), "m" (*fx));
140
141 /* See comment in copy_fxregs_to_kernel() below. */
142 return user_insn(rex64/fxsave (%[fx]), "=m" (*fx), [fx] "R" (fx));
143 }
144
145 static inline void copy_kernel_to_fxregs(struct fxregs_state *fx)
146 {
147 int err;
148
149 if (config_enabled(CONFIG_X86_32)) {
150 err = check_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx));
151 } else {
152 if (config_enabled(CONFIG_AS_FXSAVEQ)) {
153 err = check_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx));
154 } else {
155 /* See comment in copy_fxregs_to_kernel() below. */
156 err = check_insn(rex64/fxrstor (%[fx]), "=m" (*fx), [fx] "R" (fx), "m" (*fx));
157 }
158 }
159 /* Copying from a kernel buffer to FPU registers should never fail: */
160 WARN_ON_FPU(err);
161 }
162
163 static inline int copy_user_to_fxregs(struct fxregs_state __user *fx)
164 {
165 if (config_enabled(CONFIG_X86_32))
166 return user_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx));
167 else if (config_enabled(CONFIG_AS_FXSAVEQ))
168 return user_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx));
169
170 /* See comment in copy_fxregs_to_kernel() below. */
171 return user_insn(rex64/fxrstor (%[fx]), "=m" (*fx), [fx] "R" (fx),
172 "m" (*fx));
173 }
174
175 static inline void copy_kernel_to_fregs(struct fregs_state *fx)
176 {
177 int err = check_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx));
178
179 WARN_ON_FPU(err);
180 }
181
182 static inline int copy_user_to_fregs(struct fregs_state __user *fx)
183 {
184 return user_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx));
185 }
186
187 static inline void copy_fxregs_to_kernel(struct fpu *fpu)
188 {
189 if (config_enabled(CONFIG_X86_32))
190 asm volatile( "fxsave %[fx]" : [fx] "=m" (fpu->state.fxsave));
191 else if (config_enabled(CONFIG_AS_FXSAVEQ))
192 asm volatile("fxsaveq %[fx]" : [fx] "=m" (fpu->state.fxsave));
193 else {
194 /* Using "rex64; fxsave %0" is broken because, if the memory
195 * operand uses any extended registers for addressing, a second
196 * REX prefix will be generated (to the assembler, rex64
197 * followed by semicolon is a separate instruction), and hence
198 * the 64-bitness is lost.
199 *
200 * Using "fxsaveq %0" would be the ideal choice, but is only
201 * supported starting with gas 2.16.
202 *
203 * Using, as a workaround, the properly prefixed form below
204 * isn't accepted by any binutils version so far released,
205 * complaining that the same type of prefix is used twice if
206 * an extended register is needed for addressing (fix submitted
207 * to mainline 2005-11-21).
208 *
209 * asm volatile("rex64/fxsave %0" : "=m" (fpu->state.fxsave));
210 *
211 * This, however, we can work around by forcing the compiler to
212 * select an addressing mode that doesn't require extended
213 * registers.
214 */
215 asm volatile( "rex64/fxsave (%[fx])"
216 : "=m" (fpu->state.fxsave)
217 : [fx] "R" (&fpu->state.fxsave));
218 }
219 }
220
221 /* These macros all use (%edi)/(%rdi) as the single memory argument. */
222 #define XSAVE ".byte " REX_PREFIX "0x0f,0xae,0x27"
223 #define XSAVEOPT ".byte " REX_PREFIX "0x0f,0xae,0x37"
224 #define XSAVES ".byte " REX_PREFIX "0x0f,0xc7,0x2f"
225 #define XRSTOR ".byte " REX_PREFIX "0x0f,0xae,0x2f"
226 #define XRSTORS ".byte " REX_PREFIX "0x0f,0xc7,0x1f"
227
228 #define XSTATE_OP(op, st, lmask, hmask, err) \
229 asm volatile("1:" op "\n\t" \
230 "xor %[err], %[err]\n" \
231 "2:\n\t" \
232 ".pushsection .fixup,\"ax\"\n\t" \
233 "3: movl $-2,%[err]\n\t" \
234 "jmp 2b\n\t" \
235 ".popsection\n\t" \
236 _ASM_EXTABLE(1b, 3b) \
237 : [err] "=r" (err) \
238 : "D" (st), "m" (*st), "a" (lmask), "d" (hmask) \
239 : "memory")
240
241 /*
242 * If XSAVES is enabled, it replaces XSAVEOPT because it supports a compact
243 * format and supervisor states in addition to modified optimization in
244 * XSAVEOPT.
245 *
246 * Otherwise, if XSAVEOPT is enabled, XSAVEOPT replaces XSAVE because XSAVEOPT
247 * supports modified optimization which is not supported by XSAVE.
248 *
249 * We use XSAVE as a fallback.
250 *
251 * The 661 label is defined in the ALTERNATIVE* macros as the address of the
252 * original instruction which gets replaced. We need to use it here as the
253 * address of the instruction where we might get an exception at.
254 */
255 #define XSTATE_XSAVE(st, lmask, hmask, err) \
256 asm volatile(ALTERNATIVE_2(XSAVE, \
257 XSAVEOPT, X86_FEATURE_XSAVEOPT, \
258 XSAVES, X86_FEATURE_XSAVES) \
259 "\n" \
260 "xor %[err], %[err]\n" \
261 "3:\n" \
262 ".pushsection .fixup,\"ax\"\n" \
263 "4: movl $-2, %[err]\n" \
264 "jmp 3b\n" \
265 ".popsection\n" \
266 _ASM_EXTABLE(661b, 4b) \
267 : [err] "=r" (err) \
268 : "D" (st), "m" (*st), "a" (lmask), "d" (hmask) \
269 : "memory")
270
271 /*
272 * Use XRSTORS to restore context if it is enabled. XRSTORS supports compact
273 * XSAVE area format.
274 */
275 #define XSTATE_XRESTORE(st, lmask, hmask, err) \
276 asm volatile(ALTERNATIVE(XRSTOR, \
277 XRSTORS, X86_FEATURE_XSAVES) \
278 "\n" \
279 "xor %[err], %[err]\n" \
280 "3:\n" \
281 ".pushsection .fixup,\"ax\"\n" \
282 "4: movl $-2, %[err]\n" \
283 "jmp 3b\n" \
284 ".popsection\n" \
285 _ASM_EXTABLE(661b, 4b) \
286 : [err] "=r" (err) \
287 : "D" (st), "m" (*st), "a" (lmask), "d" (hmask) \
288 : "memory")
289
290 /*
291 * This function is called only during boot time when x86 caps are not set
292 * up and alternative can not be used yet.
293 */
294 static inline void copy_xregs_to_kernel_booting(struct xregs_state *xstate)
295 {
296 u64 mask = -1;
297 u32 lmask = mask;
298 u32 hmask = mask >> 32;
299 int err;
300
301 WARN_ON(system_state != SYSTEM_BOOTING);
302
303 if (static_cpu_has_safe(X86_FEATURE_XSAVES))
304 XSTATE_OP(XSAVES, xstate, lmask, hmask, err);
305 else
306 XSTATE_OP(XSAVE, xstate, lmask, hmask, err);
307
308 /* We should never fault when copying to a kernel buffer: */
309 WARN_ON_FPU(err);
310 }
311
312 /*
313 * This function is called only during boot time when x86 caps are not set
314 * up and alternative can not be used yet.
315 */
316 static inline void copy_kernel_to_xregs_booting(struct xregs_state *xstate)
317 {
318 u64 mask = -1;
319 u32 lmask = mask;
320 u32 hmask = mask >> 32;
321 int err;
322
323 WARN_ON(system_state != SYSTEM_BOOTING);
324
325 if (static_cpu_has_safe(X86_FEATURE_XSAVES))
326 XSTATE_OP(XRSTORS, xstate, lmask, hmask, err);
327 else
328 XSTATE_OP(XRSTOR, xstate, lmask, hmask, err);
329
330 /* We should never fault when copying from a kernel buffer: */
331 WARN_ON_FPU(err);
332 }
333
334 /*
335 * Save processor xstate to xsave area.
336 */
337 static inline void copy_xregs_to_kernel(struct xregs_state *xstate)
338 {
339 u64 mask = -1;
340 u32 lmask = mask;
341 u32 hmask = mask >> 32;
342 int err;
343
344 WARN_ON(!alternatives_patched);
345
346 XSTATE_XSAVE(xstate, lmask, hmask, err);
347
348 /* We should never fault when copying to a kernel buffer: */
349 WARN_ON_FPU(err);
350 }
351
352 /*
353 * Restore processor xstate from xsave area.
354 */
355 static inline void copy_kernel_to_xregs(struct xregs_state *xstate, u64 mask)
356 {
357 u32 lmask = mask;
358 u32 hmask = mask >> 32;
359 int err;
360
361 XSTATE_XRESTORE(xstate, lmask, hmask, err);
362
363 /* We should never fault when copying from a kernel buffer: */
364 WARN_ON_FPU(err);
365 }
366
367 /*
368 * Save xstate to user space xsave area.
369 *
370 * We don't use modified optimization because xrstor/xrstors might track
371 * a different application.
372 *
373 * We don't use compacted format xsave area for
374 * backward compatibility for old applications which don't understand
375 * compacted format of xsave area.
376 */
377 static inline int copy_xregs_to_user(struct xregs_state __user *buf)
378 {
379 int err;
380
381 /*
382 * Clear the xsave header first, so that reserved fields are
383 * initialized to zero.
384 */
385 err = __clear_user(&buf->header, sizeof(buf->header));
386 if (unlikely(err))
387 return -EFAULT;
388
389 stac();
390 XSTATE_OP(XSAVE, buf, -1, -1, err);
391 clac();
392
393 return err;
394 }
395
396 /*
397 * Restore xstate from user space xsave area.
398 */
399 static inline int copy_user_to_xregs(struct xregs_state __user *buf, u64 mask)
400 {
401 struct xregs_state *xstate = ((__force struct xregs_state *)buf);
402 u32 lmask = mask;
403 u32 hmask = mask >> 32;
404 int err;
405
406 stac();
407 XSTATE_OP(XRSTOR, xstate, lmask, hmask, err);
408 clac();
409
410 return err;
411 }
412
413 /*
414 * These must be called with preempt disabled. Returns
415 * 'true' if the FPU state is still intact and we can
416 * keep registers active.
417 *
418 * The legacy FNSAVE instruction cleared all FPU state
419 * unconditionally, so registers are essentially destroyed.
420 * Modern FPU state can be kept in registers, if there are
421 * no pending FP exceptions.
422 */
423 static inline int copy_fpregs_to_fpstate(struct fpu *fpu)
424 {
425 if (likely(use_xsave())) {
426 copy_xregs_to_kernel(&fpu->state.xsave);
427 return 1;
428 }
429
430 if (likely(use_fxsr())) {
431 copy_fxregs_to_kernel(fpu);
432 return 1;
433 }
434
435 /*
436 * Legacy FPU register saving, FNSAVE always clears FPU registers,
437 * so we have to mark them inactive:
438 */
439 asm volatile("fnsave %[fp]; fwait" : [fp] "=m" (fpu->state.fsave));
440
441 return 0;
442 }
443
444 static inline void __copy_kernel_to_fpregs(union fpregs_state *fpstate)
445 {
446 if (use_xsave()) {
447 copy_kernel_to_xregs(&fpstate->xsave, -1);
448 } else {
449 if (use_fxsr())
450 copy_kernel_to_fxregs(&fpstate->fxsave);
451 else
452 copy_kernel_to_fregs(&fpstate->fsave);
453 }
454 }
455
456 static inline void copy_kernel_to_fpregs(union fpregs_state *fpstate)
457 {
458 /*
459 * AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception is
460 * pending. Clear the x87 state here by setting it to fixed values.
461 * "m" is a random variable that should be in L1.
462 */
463 if (unlikely(static_cpu_has_bug_safe(X86_BUG_FXSAVE_LEAK))) {
464 asm volatile(
465 "fnclex\n\t"
466 "emms\n\t"
467 "fildl %P[addr]" /* set F?P to defined value */
468 : : [addr] "m" (fpstate));
469 }
470
471 __copy_kernel_to_fpregs(fpstate);
472 }
473
474 extern int copy_fpstate_to_sigframe(void __user *buf, void __user *fp, int size);
475
476 /*
477 * FPU context switch related helper methods:
478 */
479
480 DECLARE_PER_CPU(struct fpu *, fpu_fpregs_owner_ctx);
481
482 /*
483 * Must be run with preemption disabled: this clears the fpu_fpregs_owner_ctx,
484 * on this CPU.
485 *
486 * This will disable any lazy FPU state restore of the current FPU state,
487 * but if the current thread owns the FPU, it will still be saved by.
488 */
489 static inline void __cpu_disable_lazy_restore(unsigned int cpu)
490 {
491 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
492 }
493
494 static inline int fpu_want_lazy_restore(struct fpu *fpu, unsigned int cpu)
495 {
496 return fpu == this_cpu_read_stable(fpu_fpregs_owner_ctx) && cpu == fpu->last_cpu;
497 }
498
499
500 /*
501 * Wrap lazy FPU TS handling in a 'hw fpregs activation/deactivation'
502 * idiom, which is then paired with the sw-flag (fpregs_active) later on:
503 */
504
505 static inline void __fpregs_activate_hw(void)
506 {
507 if (!use_eager_fpu())
508 clts();
509 }
510
511 static inline void __fpregs_deactivate_hw(void)
512 {
513 if (!use_eager_fpu())
514 stts();
515 }
516
517 /* Must be paired with an 'stts' (fpregs_deactivate_hw()) after! */
518 static inline void __fpregs_deactivate(struct fpu *fpu)
519 {
520 WARN_ON_FPU(!fpu->fpregs_active);
521
522 fpu->fpregs_active = 0;
523 this_cpu_write(fpu_fpregs_owner_ctx, NULL);
524 }
525
526 /* Must be paired with a 'clts' (fpregs_activate_hw()) before! */
527 static inline void __fpregs_activate(struct fpu *fpu)
528 {
529 WARN_ON_FPU(fpu->fpregs_active);
530
531 fpu->fpregs_active = 1;
532 this_cpu_write(fpu_fpregs_owner_ctx, fpu);
533 }
534
535 /*
536 * The question "does this thread have fpu access?"
537 * is slightly racy, since preemption could come in
538 * and revoke it immediately after the test.
539 *
540 * However, even in that very unlikely scenario,
541 * we can just assume we have FPU access - typically
542 * to save the FP state - we'll just take a #NM
543 * fault and get the FPU access back.
544 */
545 static inline int fpregs_active(void)
546 {
547 return current->thread.fpu.fpregs_active;
548 }
549
550 /*
551 * Encapsulate the CR0.TS handling together with the
552 * software flag.
553 *
554 * These generally need preemption protection to work,
555 * do try to avoid using these on their own.
556 */
557 static inline void fpregs_activate(struct fpu *fpu)
558 {
559 __fpregs_activate_hw();
560 __fpregs_activate(fpu);
561 }
562
563 static inline void fpregs_deactivate(struct fpu *fpu)
564 {
565 __fpregs_deactivate(fpu);
566 __fpregs_deactivate_hw();
567 }
568
569 /*
570 * FPU state switching for scheduling.
571 *
572 * This is a two-stage process:
573 *
574 * - switch_fpu_prepare() saves the old state and
575 * sets the new state of the CR0.TS bit. This is
576 * done within the context of the old process.
577 *
578 * - switch_fpu_finish() restores the new state as
579 * necessary.
580 */
581 typedef struct { int preload; } fpu_switch_t;
582
583 static inline fpu_switch_t
584 switch_fpu_prepare(struct fpu *old_fpu, struct fpu *new_fpu, int cpu)
585 {
586 fpu_switch_t fpu;
587
588 /*
589 * If the task has used the math, pre-load the FPU on xsave processors
590 * or if the past 5 consecutive context-switches used math.
591 */
592 fpu.preload = new_fpu->fpstate_active &&
593 (use_eager_fpu() || new_fpu->counter > 5);
594
595 if (old_fpu->fpregs_active) {
596 if (!copy_fpregs_to_fpstate(old_fpu))
597 old_fpu->last_cpu = -1;
598 else
599 old_fpu->last_cpu = cpu;
600
601 /* But leave fpu_fpregs_owner_ctx! */
602 old_fpu->fpregs_active = 0;
603
604 /* Don't change CR0.TS if we just switch! */
605 if (fpu.preload) {
606 new_fpu->counter++;
607 __fpregs_activate(new_fpu);
608 prefetch(&new_fpu->state);
609 } else {
610 __fpregs_deactivate_hw();
611 }
612 } else {
613 old_fpu->counter = 0;
614 old_fpu->last_cpu = -1;
615 if (fpu.preload) {
616 new_fpu->counter++;
617 if (fpu_want_lazy_restore(new_fpu, cpu))
618 fpu.preload = 0;
619 else
620 prefetch(&new_fpu->state);
621 fpregs_activate(new_fpu);
622 }
623 }
624 return fpu;
625 }
626
627 /*
628 * Misc helper functions:
629 */
630
631 /*
632 * By the time this gets called, we've already cleared CR0.TS and
633 * given the process the FPU if we are going to preload the FPU
634 * state - all we need to do is to conditionally restore the register
635 * state itself.
636 */
637 static inline void switch_fpu_finish(struct fpu *new_fpu, fpu_switch_t fpu_switch)
638 {
639 if (fpu_switch.preload)
640 copy_kernel_to_fpregs(&new_fpu->state);
641 }
642
643 /*
644 * Needs to be preemption-safe.
645 *
646 * NOTE! user_fpu_begin() must be used only immediately before restoring
647 * the save state. It does not do any saving/restoring on its own. In
648 * lazy FPU mode, it is just an optimization to avoid a #NM exception,
649 * the task can lose the FPU right after preempt_enable().
650 */
651 static inline void user_fpu_begin(void)
652 {
653 struct fpu *fpu = &current->thread.fpu;
654
655 preempt_disable();
656 if (!fpregs_active())
657 fpregs_activate(fpu);
658 preempt_enable();
659 }
660
661 /*
662 * MXCSR and XCR definitions:
663 */
664
665 extern unsigned int mxcsr_feature_mask;
666
667 #define XCR_XFEATURE_ENABLED_MASK 0x00000000
668
669 static inline u64 xgetbv(u32 index)
670 {
671 u32 eax, edx;
672
673 asm volatile(".byte 0x0f,0x01,0xd0" /* xgetbv */
674 : "=a" (eax), "=d" (edx)
675 : "c" (index));
676 return eax + ((u64)edx << 32);
677 }
678
679 static inline void xsetbv(u32 index, u64 value)
680 {
681 u32 eax = value;
682 u32 edx = value >> 32;
683
684 asm volatile(".byte 0x0f,0x01,0xd1" /* xsetbv */
685 : : "a" (eax), "d" (edx), "c" (index));
686 }
687
688 #endif /* _ASM_X86_FPU_INTERNAL_H */