arch/x86/include/asm/gart.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _ASM_X86_GART_H
   3 #define _ASM_X86_GART_H
   4
   5 #include <asm/e820/api.h>
   6
   7 extern void set_up_gart_resume(u32, u32);
   8
   9 extern int fallback_aper_order;
  10 extern int fallback_aper_force;
  11 extern int fix_aperture;
  12
  13 /* PTE bits. */
  14 #define GPTE_VALID      1
  15 #define GPTE_COHERENT   2
  16
  17 /* Aperture control register bits. */
  18 #define GARTEN          (1<<0)
  19 #define DISGARTCPU      (1<<4)
  20 #define DISGARTIO       (1<<5)
  21 #define DISTLBWALKPRB   (1<<6)
  22
  23 /* GART cache control register bits. */
  24 #define INVGART         (1<<0)
  25 #define GARTPTEERR      (1<<1)
  26
  27 /* K8 On-cpu GART registers */
  28 #define AMD64_GARTAPERTURECTL   0x90
  29 #define AMD64_GARTAPERTUREBASE  0x94
  30 #define AMD64_GARTTABLEBASE     0x98
  31 #define AMD64_GARTCACHECTL      0x9c
  32
  33 #ifdef CONFIG_GART_IOMMU
  34 extern int gart_iommu_aperture;
  35 extern int gart_iommu_aperture_allowed;
  36 extern int gart_iommu_aperture_disabled;
  37
  38 extern void early_gart_iommu_check(void);
  39 extern int gart_iommu_init(void);
  40 extern void __init gart_parse_options(char *);
  41 extern int gart_iommu_hole_init(void);
  42
  43 #else
  44 #define gart_iommu_aperture            0
  45 #define gart_iommu_aperture_allowed    0
  46 #define gart_iommu_aperture_disabled   1
  47
  48 static inline void early_gart_iommu_check(void)
  49 {
  50 }
  51 static inline void gart_parse_options(char *options)
  52 {
  53 }
  54 static inline int gart_iommu_hole_init(void)
  55 {
  56         return -ENODEV;
  57 }
  58 #endif
  59
  60 extern int agp_amd64_init(void);
  61
  62 static inline void gart_set_size_and_enable(struct pci_dev *dev, u32 order)
  63 {
  64         u32 ctl;
  65
  66         /*
  67          * Don't enable translation but enable GART IO and CPU accesses.
  68          * Also, set DISTLBWALKPRB since GART tables memory is UC.
  69          */
  70         ctl = order << 1;
  71
  72         pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
  73 }
  74
  75 static inline void enable_gart_translation(struct pci_dev *dev, u64 addr)
  76 {
  77         u32 tmp, ctl;
  78
  79         /* address of the mappings table */
  80         addr >>= 12;
  81         tmp = (u32) addr<<4;
  82         tmp &= ~0xf;
  83         pci_write_config_dword(dev, AMD64_GARTTABLEBASE, tmp);
  84
  85         /* Enable GART translation for this hammer. */
  86         pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl);
  87         ctl |= GARTEN | DISTLBWALKPRB;
  88         ctl &= ~(DISGARTCPU | DISGARTIO);
  89         pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
  90 }
  91
  92 static inline int aperture_valid(u64 aper_base, u32 aper_size, u32 min_size)
  93 {
  94         if (!aper_base)
  95                 return 0;
  96
  97         if (aper_base + aper_size > 0x100000000ULL) {
  98                 printk(KERN_INFO "Aperture beyond 4GB. Ignoring.\n");
  99                 return 0;
 100         }
 101         if (e820__mapped_any(aper_base, aper_base + aper_size, E820_TYPE_RAM)) {
 102                 printk(KERN_INFO "Aperture pointing to e820 RAM. Ignoring.\n");
 103                 return 0;
 104         }
 105         if (aper_size < min_size) {
 106                 printk(KERN_INFO "Aperture too small (%d MB) than (%d MB)\n",
 107                                  aper_size>>20, min_size>>20);
 108                 return 0;
 109         }
 110
 111         return 1;
 112 }
 113
 114 #endif /* _ASM_X86_GART_H */