arch/x86/include/asm/intel-mid.h

   1 /*
   2  * intel-mid.h: Intel MID specific setup code
   3  *
   4  * (C) Copyright 2009 Intel Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; version 2
   9  * of the License.
  10  */
  11 #ifndef _ASM_X86_INTEL_MID_H
  12 #define _ASM_X86_INTEL_MID_H
  13
  14 #include <linux/sfi.h>
  15
  16 extern int intel_mid_pci_init(void);
  17 extern int __init sfi_parse_mrtc(struct sfi_table_header *table);
  18 extern int sfi_mrtc_num;
  19 extern struct sfi_rtc_table_entry sfi_mrtc_array[];
  20
  21 /*
  22  * Medfield is the follow-up of Moorestown, it combines two chip solution into
  23  * one. Other than that it also added always-on and constant tsc and lapic
  24  * timers. Medfield is the platform name, and the chip name is called Penwell
  25  * we treat Medfield/Penwell as a variant of Moorestown. Penwell can be
  26  * identified via MSRs.
  27  */
  28 enum intel_mid_cpu_type {
  29         /* 1 was Moorestown */
  30         INTEL_MID_CPU_CHIP_PENWELL = 2,
  31 };
  32
  33 extern enum intel_mid_cpu_type __intel_mid_cpu_chip;
  34
  35 #ifdef CONFIG_X86_INTEL_MID
  36
  37 static inline enum intel_mid_cpu_type intel_mid_identify_cpu(void)
  38 {
  39         return __intel_mid_cpu_chip;
  40 }
  41
  42 #else /* !CONFIG_X86_INTEL_MID */
  43
  44 #define intel_mid_identify_cpu()    (0)
  45
  46 #endif /* !CONFIG_X86_INTEL_MID */
  47
  48 enum intel_mid_timer_options {
  49         INTEL_MID_TIMER_DEFAULT,
  50         INTEL_MID_TIMER_APBT_ONLY,
  51         INTEL_MID_TIMER_LAPIC_APBT,
  52 };
  53
  54 extern enum intel_mid_timer_options intel_mid_timer_options;
  55
  56 /*
  57  * Penwell uses spread spectrum clock, so the freq number is not exactly
  58  * the same as reported by MSR based on SDM.
  59  */
  60 #define PENWELL_FSB_FREQ_83SKU         83200
  61 #define PENWELL_FSB_FREQ_100SKU        99840
  62
  63 #define SFI_MTMR_MAX_NUM 8
  64 #define SFI_MRTC_MAX    8
  65
  66 extern struct console early_mrst_console;
  67 extern void mrst_early_console_init(void);
  68
  69 extern struct console early_hsu_console;
  70 extern void hsu_early_console_init(const char *);
  71
  72 extern void intel_scu_devices_create(void);
  73 extern void intel_scu_devices_destroy(void);
  74
  75 /* VRTC timer */
  76 #define MRST_VRTC_MAP_SZ        (1024)
  77 /*#define MRST_VRTC_PGOFFSET    (0xc00) */
  78
  79 extern void intel_mid_rtc_init(void);
  80
  81 #endif /* _ASM_X86_INTEL_MID_H */