arch/x86/include/asm/io.h

   1 #ifndef _ASM_X86_IO_H
   2 #define _ASM_X86_IO_H
   3
   4 /*
   5  * This file contains the definitions for the x86 IO instructions
   6  * inb/inw/inl/outb/outw/outl and the "string versions" of the same
   7  * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
   8  * versions of the single-IO instructions (inb_p/inw_p/..).
   9  *
  10  * This file is not meant to be obfuscating: it's just complicated
  11  * to (a) handle it all in a way that makes gcc able to optimize it
  12  * as well as possible and (b) trying to avoid writing the same thing
  13  * over and over again with slight variations and possibly making a
  14  * mistake somewhere.
  15  */
  16
  17 /*
  18  * Thanks to James van Artsdalen for a better timing-fix than
  19  * the two short jumps: using outb's to a nonexistent port seems
  20  * to guarantee better timings even on fast machines.
  21  *
  22  * On the other hand, I'd like to be sure of a non-existent port:
  23  * I feel a bit unsafe about using 0x80 (should be safe, though)
  24  *
  25  *              Linus
  26  */
  27
  28  /*
  29   *  Bit simplified and optimized by Jan Hubicka
  30   *  Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999.
  31   *
  32   *  isa_memset_io, isa_memcpy_fromio, isa_memcpy_toio added,
  33   *  isa_read[wl] and isa_write[wl] fixed
  34   *  - Arnaldo Carvalho de Melo <acme@conectiva.com.br>
  35   */
  36
  37 #define ARCH_HAS_IOREMAP_WC
  38 #define ARCH_HAS_IOREMAP_WT
  39
  40 #include <linux/string.h>
  41 #include <linux/compiler.h>
  42 #include <asm/page.h>
  43 #include <asm/early_ioremap.h>
  44 #include <asm/pgtable_types.h>
  45
  46 #define build_mmio_read(name, size, type, reg, barrier) \
  47 static inline type name(const volatile void __iomem *addr) \
  48 { type ret; asm volatile("mov" size " %1,%0":reg (ret) \
  49 :"m" (*(volatile type __force *)addr) barrier); return ret; }
  50
  51 #define build_mmio_write(name, size, type, reg, barrier) \
  52 static inline void name(type val, volatile void __iomem *addr) \
  53 { asm volatile("mov" size " %0,%1": :reg (val), \
  54 "m" (*(volatile type __force *)addr) barrier); }
  55
  56 build_mmio_read(readb, "b", unsigned char, "=q", :"memory")
  57 build_mmio_read(readw, "w", unsigned short, "=r", :"memory")
  58 build_mmio_read(readl, "l", unsigned int, "=r", :"memory")
  59
  60 build_mmio_read(__readb, "b", unsigned char, "=q", )
  61 build_mmio_read(__readw, "w", unsigned short, "=r", )
  62 build_mmio_read(__readl, "l", unsigned int, "=r", )
  63
  64 build_mmio_write(writeb, "b", unsigned char, "q", :"memory")
  65 build_mmio_write(writew, "w", unsigned short, "r", :"memory")
  66 build_mmio_write(writel, "l", unsigned int, "r", :"memory")
  67
  68 build_mmio_write(__writeb, "b", unsigned char, "q", )
  69 build_mmio_write(__writew, "w", unsigned short, "r", )
  70 build_mmio_write(__writel, "l", unsigned int, "r", )
  71
  72 #define readb_relaxed(a) __readb(a)
  73 #define readw_relaxed(a) __readw(a)
  74 #define readl_relaxed(a) __readl(a)
  75 #define __raw_readb __readb
  76 #define __raw_readw __readw
  77 #define __raw_readl __readl
  78
  79 #define writeb_relaxed(v, a) __writeb(v, a)
  80 #define writew_relaxed(v, a) __writew(v, a)
  81 #define writel_relaxed(v, a) __writel(v, a)
  82 #define __raw_writeb __writeb
  83 #define __raw_writew __writew
  84 #define __raw_writel __writel
  85
  86 #define mmiowb() barrier()
  87
  88 #ifdef CONFIG_X86_64
  89
  90 build_mmio_read(readq, "q", unsigned long, "=r", :"memory")
  91 build_mmio_write(writeq, "q", unsigned long, "r", :"memory")
  92
  93 #define readq_relaxed(a)        readq(a)
  94 #define writeq_relaxed(v, a)    writeq(v, a)
  95
  96 #define __raw_readq(a)          readq(a)
  97 #define __raw_writeq(val, addr) writeq(val, addr)
  98
  99 /* Let people know that we have them */
 100 #define readq                   readq
 101 #define writeq                  writeq
 102
 103 #endif
 104
 105 /**
 106  *      virt_to_phys    -       map virtual addresses to physical
 107  *      @address: address to remap
 108  *
 109  *      The returned physical address is the physical (CPU) mapping for
 110  *      the memory address given. It is only valid to use this function on
 111  *      addresses directly mapped or allocated via kmalloc.
 112  *
 113  *      This function does not give bus mappings for DMA transfers. In
 114  *      almost all conceivable cases a device driver should not be using
 115  *      this function
 116  */
 117
 118 static inline phys_addr_t virt_to_phys(volatile void *address)
 119 {
 120         return __pa(address);
 121 }
 122
 123 /**
 124  *      phys_to_virt    -       map physical address to virtual
 125  *      @address: address to remap
 126  *
 127  *      The returned virtual address is a current CPU mapping for
 128  *      the memory address given. It is only valid to use this function on
 129  *      addresses that have a kernel mapping
 130  *
 131  *      This function does not handle bus mappings for DMA transfers. In
 132  *      almost all conceivable cases a device driver should not be using
 133  *      this function
 134  */
 135
 136 static inline void *phys_to_virt(phys_addr_t address)
 137 {
 138         return __va(address);
 139 }
 140
 141 /*
 142  * Change "struct page" to physical address.
 143  */
 144 #define page_to_phys(page)    ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
 145
 146 /*
 147  * ISA I/O bus memory addresses are 1:1 with the physical address.
 148  * However, we truncate the address to unsigned int to avoid undesirable
 149  * promitions in legacy drivers.
 150  */
 151 static inline unsigned int isa_virt_to_bus(volatile void *address)
 152 {
 153         return (unsigned int)virt_to_phys(address);
 154 }
 155 #define isa_page_to_bus(page)   ((unsigned int)page_to_phys(page))
 156 #define isa_bus_to_virt         phys_to_virt
 157
 158 /*
 159  * However PCI ones are not necessarily 1:1 and therefore these interfaces
 160  * are forbidden in portable PCI drivers.
 161  *
 162  * Allow them on x86 for legacy drivers, though.
 163  */
 164 #define virt_to_bus virt_to_phys
 165 #define bus_to_virt phys_to_virt
 166
 167 /**
 168  * ioremap     -   map bus memory into CPU space
 169  * @offset:    bus address of the memory
 170  * @size:      size of the resource to map
 171  *
 172  * ioremap performs a platform specific sequence of operations to
 173  * make bus memory CPU accessible via the readb/readw/readl/writeb/
 174  * writew/writel functions and the other mmio helpers. The returned
 175  * address is not guaranteed to be usable directly as a virtual
 176  * address.
 177  *
 178  * If the area you are trying to map is a PCI BAR you should have a
 179  * look at pci_iomap().
 180  */
 181 extern void __iomem *ioremap_nocache(resource_size_t offset, unsigned long size);
 182 extern void __iomem *ioremap_uc(resource_size_t offset, unsigned long size);
 183 extern void __iomem *ioremap_cache(resource_size_t offset, unsigned long size);
 184 extern void __iomem *ioremap_prot(resource_size_t offset, unsigned long size,
 185                                 unsigned long prot_val);
 186
 187 /*
 188  * The default ioremap() behavior is non-cached:
 189  */
 190 static inline void __iomem *ioremap(resource_size_t offset, unsigned long size)
 191 {
 192         return ioremap_nocache(offset, size);
 193 }
 194
 195 extern void iounmap(volatile void __iomem *addr);
 196
 197 extern void set_iounmap_nonlazy(void);
 198
 199 #ifdef __KERNEL__
 200
 201 #include <asm-generic/iomap.h>
 202
 203 /*
 204  * Convert a virtual cached pointer to an uncached pointer
 205  */
 206 #define xlate_dev_kmem_ptr(p)   p
 207
 208 static inline void
 209 memset_io(volatile void __iomem *addr, unsigned char val, size_t count)
 210 {
 211         memset((void __force *)addr, val, count);
 212 }
 213
 214 static inline void
 215 memcpy_fromio(void *dst, const volatile void __iomem *src, size_t count)
 216 {
 217         memcpy(dst, (const void __force *)src, count);
 218 }
 219
 220 static inline void
 221 memcpy_toio(volatile void __iomem *dst, const void *src, size_t count)
 222 {
 223         memcpy((void __force *)dst, src, count);
 224 }
 225
 226 /*
 227  * ISA space is 'always mapped' on a typical x86 system, no need to
 228  * explicitly ioremap() it. The fact that the ISA IO space is mapped
 229  * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
 230  * are physical addresses. The following constant pointer can be
 231  * used as the IO-area pointer (it can be iounmapped as well, so the
 232  * analogy with PCI is quite large):
 233  */
 234 #define __ISA_IO_base ((char __iomem *)(PAGE_OFFSET))
 235
 236 /*
 237  *      Cache management
 238  *
 239  *      This needed for two cases
 240  *      1. Out of order aware processors
 241  *      2. Accidentally out of order processors (PPro errata #51)
 242  */
 243
 244 static inline void flush_write_buffers(void)
 245 {
 246 #if defined(CONFIG_X86_PPRO_FENCE)
 247         asm volatile("lock; addl $0,0(%%esp)": : :"memory");
 248 #endif
 249 }
 250
 251 static inline void __pmem *arch_memremap_pmem(resource_size_t offset,
 252         unsigned long size)
 253 {
 254         return (void __force __pmem *) ioremap_cache(offset, size);
 255 }
 256
 257 #endif /* __KERNEL__ */
 258
 259 extern void native_io_delay(void);
 260
 261 extern int io_delay_type;
 262 extern void io_delay_init(void);
 263
 264 #if defined(CONFIG_PARAVIRT)
 265 #include <asm/paravirt.h>
 266 #else
 267
 268 static inline void slow_down_io(void)
 269 {
 270         native_io_delay();
 271 #ifdef REALLY_SLOW_IO
 272         native_io_delay();
 273         native_io_delay();
 274         native_io_delay();
 275 #endif
 276 }
 277
 278 #endif
 279
 280 #define BUILDIO(bwl, bw, type)                                          \
 281 static inline void out##bwl(unsigned type value, int port)              \
 282 {                                                                       \
 283         asm volatile("out" #bwl " %" #bw "0, %w1"                       \
 284                      : : "a"(value), "Nd"(port));                       \
 285 }                                                                       \
 286                                                                         \
 287 static inline unsigned type in##bwl(int port)                           \
 288 {                                                                       \
 289         unsigned type value;                                            \
 290         asm volatile("in" #bwl " %w1, %" #bw "0"                        \
 291                      : "=a"(value) : "Nd"(port));                       \
 292         return value;                                                   \
 293 }                                                                       \
 294                                                                         \
 295 static inline void out##bwl##_p(unsigned type value, int port)          \
 296 {                                                                       \
 297         out##bwl(value, port);                                          \
 298         slow_down_io();                                                 \
 299 }                                                                       \
 300                                                                         \
 301 static inline unsigned type in##bwl##_p(int port)                       \
 302 {                                                                       \
 303         unsigned type value = in##bwl(port);                            \
 304         slow_down_io();                                                 \
 305         return value;                                                   \
 306 }                                                                       \
 307                                                                         \
 308 static inline void outs##bwl(int port, const void *addr, unsigned long count) \
 309 {                                                                       \
 310         asm volatile("rep; outs" #bwl                                   \
 311                      : "+S"(addr), "+c"(count) : "d"(port));            \
 312 }                                                                       \
 313                                                                         \
 314 static inline void ins##bwl(int port, void *addr, unsigned long count)  \
 315 {                                                                       \
 316         asm volatile("rep; ins" #bwl                                    \
 317                      : "+D"(addr), "+c"(count) : "d"(port));            \
 318 }
 319
 320 BUILDIO(b, b, char)
 321 BUILDIO(w, w, short)
 322 BUILDIO(l, , int)
 323
 324 extern void *xlate_dev_mem_ptr(phys_addr_t phys);
 325 extern void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr);
 326
 327 extern int ioremap_change_attr(unsigned long vaddr, unsigned long size,
 328                                 enum page_cache_mode pcm);
 329 extern void __iomem *ioremap_wc(resource_size_t offset, unsigned long size);
 330 extern void __iomem *ioremap_wt(resource_size_t offset, unsigned long size);
 331
 332 extern bool is_early_ioremap_ptep(pte_t *ptep);
 333
 334 #ifdef CONFIG_XEN
 335 #include <xen/xen.h>
 336 struct bio_vec;
 337
 338 extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1,
 339                                       const struct bio_vec *vec2);
 340
 341 #define BIOVEC_PHYS_MERGEABLE(vec1, vec2)                               \
 342         (__BIOVEC_PHYS_MERGEABLE(vec1, vec2) &&                         \
 343          (!xen_domain() || xen_biovec_phys_mergeable(vec1, vec2)))
 344 #endif  /* CONFIG_XEN */
 345
 346 #define IO_SPACE_LIMIT 0xffff
 347
 348 #ifdef CONFIG_MTRR
 349 extern int __must_check arch_phys_wc_index(int handle);
 350 #define arch_phys_wc_index arch_phys_wc_index
 351
 352 extern int __must_check arch_phys_wc_add(unsigned long base,
 353                                          unsigned long size);
 354 extern void arch_phys_wc_del(int handle);
 355 #define arch_phys_wc_add arch_phys_wc_add
 356 #endif
 357
 358 #endif /* _ASM_X86_IO_H */