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git.proxmox.com Git - mirror_ubuntu-eoan-kernel.git/blob - arch/x86/include/asm/mce.h
4 #include <linux/types.h>
5 #include <asm/ioctls.h>
8 * Machine Check support for x86
11 /* MCG_CAP register defines */
12 #define MCG_BANKCNT_MASK 0xff /* Number of Banks */
13 #define MCG_CTL_P (1ULL<<8) /* MCG_CTL register available */
14 #define MCG_EXT_P (1ULL<<9) /* Extended registers available */
15 #define MCG_CMCI_P (1ULL<<10) /* CMCI supported */
16 #define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */
17 #define MCG_EXT_CNT_SHIFT 16
18 #define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
19 #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
21 /* MCG_STATUS register defines */
22 #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
23 #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
24 #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
26 /* MCi_STATUS register defines */
27 #define MCI_STATUS_VAL (1ULL<<63) /* valid error */
28 #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
29 #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
30 #define MCI_STATUS_EN (1ULL<<60) /* error enabled */
31 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
32 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
33 #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
34 #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
35 #define MCI_STATUS_AR (1ULL<<55) /* Action required */
37 /* MCi_MISC register defines */
38 #define MCI_MISC_ADDR_LSB(m) ((m) & 0x3f)
39 #define MCI_MISC_ADDR_MODE(m) (((m) >> 6) & 7)
40 #define MCI_MISC_ADDR_SEGOFF 0 /* segment offset */
41 #define MCI_MISC_ADDR_LINEAR 1 /* linear address */
42 #define MCI_MISC_ADDR_PHYS 2 /* physical address */
43 #define MCI_MISC_ADDR_MEM 3 /* memory address */
44 #define MCI_MISC_ADDR_GENERIC 7 /* generic */
46 /* CTL2 register defines */
47 #define MCI_CTL2_CMCI_EN (1ULL << 30)
48 #define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL
50 #define MCJ_CTX_MASK 3
51 #define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK)
52 #define MCJ_CTX_RANDOM 0 /* inject context: random */
53 #define MCJ_CTX_PROCESS 0x1 /* inject context: process */
54 #define MCJ_CTX_IRQ 0x2 /* inject context: IRQ */
55 #define MCJ_NMI_BROADCAST 0x4 /* do NMI broadcasting */
56 #define MCJ_EXCEPTION 0x8 /* raise as exception */
57 #define MCJ_IRQ_BRAODCAST 0x10 /* do IRQ broadcasting */
59 /* Fields are zero when not available */
66 __u64 tsc
; /* cpu time stamp counter */
67 __u64 time
; /* wall time_t when error was detected */
68 __u8 cpuvendor
; /* cpu vendor as encoded in system.h */
69 __u8 inject_flags
; /* software inject flags */
71 __u32 cpuid
; /* CPUID 1 EAX */
72 __u8 cs
; /* code segment */
73 __u8 bank
; /* machine check bank */
74 __u8 cpu
; /* cpu number; obsolete; use extcpu now */
75 __u8 finished
; /* entry is valid */
76 __u32 extcpu
; /* linux cpu number that detected the error */
77 __u32 socketid
; /* CPU socket ID */
78 __u32 apicid
; /* CPU initial apic ID */
79 __u64 mcgcap
; /* MCGCAP MSR: machine check capabilities of CPU */
83 * This structure contains all data related to the MCE log. Also
84 * carries a signature to make it easier to find from external
85 * debugging tools. Each entry is only valid when its finished flag
89 #define MCE_LOG_LEN 32
92 char signature
[12]; /* "MACHINECHECK" */
93 unsigned len
; /* = MCE_LOG_LEN */
96 unsigned recordlen
; /* length of struct mce */
97 struct mce entry
[MCE_LOG_LEN
];
100 #define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */
102 #define MCE_LOG_SIGNATURE "MACHINECHECK"
104 #define MCE_GET_RECORD_LEN _IOR('M', 1, int)
105 #define MCE_GET_LOG_LEN _IOR('M', 2, int)
106 #define MCE_GETCLEAR_FLAGS _IOR('M', 3, int)
108 /* Software defined banks */
109 #define MCE_EXTENDED_BANK 128
110 #define MCE_THERMAL_BANK MCE_EXTENDED_BANK + 0
112 #define K8_MCE_THRESHOLD_BASE (MCE_EXTENDED_BANK + 1) /* MCE_AMD */
113 #define K8_MCE_THRESHOLD_BANK_0 (MCE_THRESHOLD_BASE + 0 * 9)
114 #define K8_MCE_THRESHOLD_BANK_1 (MCE_THRESHOLD_BASE + 1 * 9)
115 #define K8_MCE_THRESHOLD_BANK_2 (MCE_THRESHOLD_BASE + 2 * 9)
116 #define K8_MCE_THRESHOLD_BANK_3 (MCE_THRESHOLD_BASE + 3 * 9)
117 #define K8_MCE_THRESHOLD_BANK_4 (MCE_THRESHOLD_BASE + 4 * 9)
118 #define K8_MCE_THRESHOLD_BANK_5 (MCE_THRESHOLD_BASE + 5 * 9)
119 #define K8_MCE_THRESHOLD_DRAM_ECC (MCE_THRESHOLD_BANK_4 + 0)
124 extern void mce_register_decode_chain(struct notifier_block
*nb
);
125 extern void mce_unregister_decode_chain(struct notifier_block
*nb
);
127 #include <linux/percpu.h>
128 #include <linux/init.h>
129 #include <linux/atomic.h>
131 extern int mce_disabled
;
132 extern int mce_p5_enabled
;
134 #ifdef CONFIG_X86_MCE
135 int mcheck_init(void);
136 void mcheck_cpu_init(struct cpuinfo_x86
*c
);
138 static inline int mcheck_init(void) { return 0; }
139 static inline void mcheck_cpu_init(struct cpuinfo_x86
*c
) {}
142 #ifdef CONFIG_X86_ANCIENT_MCE
143 void intel_p5_mcheck_init(struct cpuinfo_x86
*c
);
144 void winchip_mcheck_init(struct cpuinfo_x86
*c
);
145 static inline void enable_p5_mce(void) { mce_p5_enabled
= 1; }
147 static inline void intel_p5_mcheck_init(struct cpuinfo_x86
*c
) {}
148 static inline void winchip_mcheck_init(struct cpuinfo_x86
*c
) {}
149 static inline void enable_p5_mce(void) {}
152 void mce_setup(struct mce
*m
);
153 void mce_log(struct mce
*m
);
154 DECLARE_PER_CPU(struct device
, mce_device
);
157 * Maximum banks number.
158 * This is the limit of the current register layout on
161 #define MAX_NR_BANKS 32
163 #ifdef CONFIG_X86_MCE_INTEL
164 extern int mce_cmci_disabled
;
165 extern int mce_ignore_ce
;
166 void mce_intel_feature_init(struct cpuinfo_x86
*c
);
167 void cmci_clear(void);
168 void cmci_reenable(void);
169 void cmci_rediscover(int dying
);
170 void cmci_recheck(void);
172 static inline void mce_intel_feature_init(struct cpuinfo_x86
*c
) { }
173 static inline void cmci_clear(void) {}
174 static inline void cmci_reenable(void) {}
175 static inline void cmci_rediscover(int dying
) {}
176 static inline void cmci_recheck(void) {}
179 #ifdef CONFIG_X86_MCE_AMD
180 void mce_amd_feature_init(struct cpuinfo_x86
*c
);
182 static inline void mce_amd_feature_init(struct cpuinfo_x86
*c
) { }
185 int mce_available(struct cpuinfo_x86
*c
);
187 DECLARE_PER_CPU(unsigned, mce_exception_count
);
188 DECLARE_PER_CPU(unsigned, mce_poll_count
);
190 extern atomic_t mce_entry
;
192 typedef DECLARE_BITMAP(mce_banks_t
, MAX_NR_BANKS
);
193 DECLARE_PER_CPU(mce_banks_t
, mce_poll_banks
);
196 MCP_TIMESTAMP
= (1 << 0), /* log time stamp */
197 MCP_UC
= (1 << 1), /* log uncorrected errors */
198 MCP_DONTLOG
= (1 << 2), /* only clear, don't log */
200 void machine_check_poll(enum mcp_flags flags
, mce_banks_t
*b
);
202 int mce_notify_irq(void);
203 void mce_notify_process(void);
205 DECLARE_PER_CPU(struct mce
, injectm
);
207 extern void register_mce_write_callback(ssize_t (*)(struct file
*filp
,
208 const char __user
*ubuf
,
209 size_t usize
, loff_t
*off
));
215 /* Call the installed machine check handler for this CPU setup. */
216 extern void (*machine_check_vector
)(struct pt_regs
*, long error_code
);
217 void do_machine_check(struct pt_regs
*, long);
223 extern void (*mce_threshold_vector
)(void);
224 extern void (*threshold_cpu_callback
)(unsigned long action
, unsigned int cpu
);
230 void intel_init_thermal(struct cpuinfo_x86
*c
);
232 void mce_log_therm_throt_event(__u64 status
);
234 /* Interrupt Handler for core thermal thresholds */
235 extern int (*platform_thermal_notify
)(__u64 msr_val
);
237 #ifdef CONFIG_X86_THERMAL_VECTOR
238 extern void mcheck_intel_therm_init(void);
240 static inline void mcheck_intel_therm_init(void) { }
244 * Used by APEI to report memory error via /dev/mcelog
247 struct cper_sec_mem_err
;
248 extern void apei_mce_report_mem_error(int corrected
,
249 struct cper_sec_mem_err
*mem_err
);
251 #endif /* __KERNEL__ */
252 #endif /* _ASM_X86_MCE_H */