arch/x86/include/asm/mce.h

   1 #ifndef _ASM_X86_MCE_H
   2 #define _ASM_X86_MCE_H
   3
   4 #include <linux/types.h>
   5 #include <asm/ioctls.h>
   6
   7 /*
   8  * Machine Check support for x86
   9  */
  10
  11 #define MCG_BANKCNT_MASK        0xff         /* Number of Banks */
  12 #define MCG_CTL_P               (1ULL<<8)    /* MCG_CTL register available */
  13 #define MCG_EXT_P               (1ULL<<9)    /* Extended registers available */
  14 #define MCG_CMCI_P              (1ULL<<10)   /* CMCI supported */
  15 #define MCG_EXT_CNT_MASK        0xff0000     /* Number of Extended registers */
  16 #define MCG_EXT_CNT_SHIFT       16
  17 #define MCG_EXT_CNT(c)          (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
  18 #define MCG_SER_P               (1ULL<<24)   /* MCA recovery/new status bits */
  19
  20 #define MCG_STATUS_RIPV  (1ULL<<0)   /* restart ip valid */
  21 #define MCG_STATUS_EIPV  (1ULL<<1)   /* ip points to correct instruction */
  22 #define MCG_STATUS_MCIP  (1ULL<<2)   /* machine check in progress */
  23
  24 #define MCI_STATUS_VAL   (1ULL<<63)  /* valid error */
  25 #define MCI_STATUS_OVER  (1ULL<<62)  /* previous errors lost */
  26 #define MCI_STATUS_UC    (1ULL<<61)  /* uncorrected error */
  27 #define MCI_STATUS_EN    (1ULL<<60)  /* error enabled */
  28 #define MCI_STATUS_MISCV (1ULL<<59)  /* misc error reg. valid */
  29 #define MCI_STATUS_ADDRV (1ULL<<58)  /* addr reg. valid */
  30 #define MCI_STATUS_PCC   (1ULL<<57)  /* processor context corrupt */
  31 #define MCI_STATUS_S     (1ULL<<56)  /* Signaled machine check */
  32 #define MCI_STATUS_AR    (1ULL<<55)  /* Action required */
  33
  34 /* MISC register defines */
  35 #define MCM_ADDR_SEGOFF  0      /* segment offset */
  36 #define MCM_ADDR_LINEAR  1      /* linear address */
  37 #define MCM_ADDR_PHYS    2      /* physical address */
  38 #define MCM_ADDR_MEM     3      /* memory address */
  39 #define MCM_ADDR_GENERIC 7      /* generic */
  40
  41 /* CTL2 register defines */
  42 #define MCI_CTL2_CMCI_EN                (1ULL << 30)
  43 #define MCI_CTL2_CMCI_THRESHOLD_MASK    0x7fffULL
  44
  45 #define MCJ_CTX_MASK            3
  46 #define MCJ_CTX(flags)          ((flags) & MCJ_CTX_MASK)
  47 #define MCJ_CTX_RANDOM          0    /* inject context: random */
  48 #define MCJ_CTX_PROCESS         1    /* inject context: process */
  49 #define MCJ_CTX_IRQ             2    /* inject context: IRQ */
  50 #define MCJ_NMI_BROADCAST       4    /* do NMI broadcasting */
  51 #define MCJ_EXCEPTION           8    /* raise as exception */
  52
  53 /* Fields are zero when not available */
  54 struct mce {
  55         __u64 status;
  56         __u64 misc;
  57         __u64 addr;
  58         __u64 mcgstatus;
  59         __u64 ip;
  60         __u64 tsc;      /* cpu time stamp counter */
  61         __u64 time;     /* wall time_t when error was detected */
  62         __u8  cpuvendor;        /* cpu vendor as encoded in system.h */
  63         __u8  inject_flags;     /* software inject flags */
  64         __u16  pad;
  65         __u32 cpuid;    /* CPUID 1 EAX */
  66         __u8  cs;               /* code segment */
  67         __u8  bank;     /* machine check bank */
  68         __u8  cpu;      /* cpu number; obsolete; use extcpu now */
  69         __u8  finished;   /* entry is valid */
  70         __u32 extcpu;   /* linux cpu number that detected the error */
  71         __u32 socketid; /* CPU socket ID */
  72         __u32 apicid;   /* CPU initial apic ID */
  73         __u64 mcgcap;   /* MCGCAP MSR: machine check capabilities of CPU */
  74 };
  75
  76 /*
  77  * This structure contains all data related to the MCE log.  Also
  78  * carries a signature to make it easier to find from external
  79  * debugging tools.  Each entry is only valid when its finished flag
  80  * is set.
  81  */
  82
  83 #define MCE_LOG_LEN 32
  84
  85 struct mce_log {
  86         char signature[12]; /* "MACHINECHECK" */
  87         unsigned len;       /* = MCE_LOG_LEN */
  88         unsigned next;
  89         unsigned flags;
  90         unsigned recordlen;     /* length of struct mce */
  91         struct mce entry[MCE_LOG_LEN];
  92 };
  93
  94 #define MCE_OVERFLOW 0          /* bit 0 in flags means overflow */
  95
  96 #define MCE_LOG_SIGNATURE       "MACHINECHECK"
  97
  98 #define MCE_GET_RECORD_LEN   _IOR('M', 1, int)
  99 #define MCE_GET_LOG_LEN      _IOR('M', 2, int)
 100 #define MCE_GETCLEAR_FLAGS   _IOR('M', 3, int)
 101
 102 /* Software defined banks */
 103 #define MCE_EXTENDED_BANK       128
 104 #define MCE_THERMAL_BANK        MCE_EXTENDED_BANK + 0
 105
 106 #define K8_MCE_THRESHOLD_BASE      (MCE_EXTENDED_BANK + 1)      /* MCE_AMD */
 107 #define K8_MCE_THRESHOLD_BANK_0    (MCE_THRESHOLD_BASE + 0 * 9)
 108 #define K8_MCE_THRESHOLD_BANK_1    (MCE_THRESHOLD_BASE + 1 * 9)
 109 #define K8_MCE_THRESHOLD_BANK_2    (MCE_THRESHOLD_BASE + 2 * 9)
 110 #define K8_MCE_THRESHOLD_BANK_3    (MCE_THRESHOLD_BASE + 3 * 9)
 111 #define K8_MCE_THRESHOLD_BANK_4    (MCE_THRESHOLD_BASE + 4 * 9)
 112 #define K8_MCE_THRESHOLD_BANK_5    (MCE_THRESHOLD_BASE + 5 * 9)
 113 #define K8_MCE_THRESHOLD_DRAM_ECC  (MCE_THRESHOLD_BANK_4 + 0)
 114
 115
 116 #ifdef __KERNEL__
 117
 118 extern struct atomic_notifier_head x86_mce_decoder_chain;
 119
 120 #include <linux/percpu.h>
 121 #include <linux/init.h>
 122 #include <asm/atomic.h>
 123
 124 extern int mce_disabled;
 125 extern int mce_p5_enabled;
 126
 127 #ifdef CONFIG_X86_MCE
 128 int mcheck_init(void);
 129 void mcheck_cpu_init(struct cpuinfo_x86 *c);
 130 #else
 131 static inline int mcheck_init(void) { return 0; }
 132 static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {}
 133 #endif
 134
 135 #ifdef CONFIG_X86_ANCIENT_MCE
 136 void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
 137 void winchip_mcheck_init(struct cpuinfo_x86 *c);
 138 static inline void enable_p5_mce(void) { mce_p5_enabled = 1; }
 139 #else
 140 static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {}
 141 static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {}
 142 static inline void enable_p5_mce(void) {}
 143 #endif
 144
 145 void mce_setup(struct mce *m);
 146 void mce_log(struct mce *m);
 147 DECLARE_PER_CPU(struct sys_device, mce_dev);
 148
 149 /*
 150  * Maximum banks number.
 151  * This is the limit of the current register layout on
 152  * Intel CPUs.
 153  */
 154 #define MAX_NR_BANKS 32
 155
 156 #ifdef CONFIG_X86_MCE_INTEL
 157 extern int mce_cmci_disabled;
 158 extern int mce_ignore_ce;
 159 void mce_intel_feature_init(struct cpuinfo_x86 *c);
 160 void cmci_clear(void);
 161 void cmci_reenable(void);
 162 void cmci_rediscover(int dying);
 163 void cmci_recheck(void);
 164 #else
 165 static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
 166 static inline void cmci_clear(void) {}
 167 static inline void cmci_reenable(void) {}
 168 static inline void cmci_rediscover(int dying) {}
 169 static inline void cmci_recheck(void) {}
 170 #endif
 171
 172 #ifdef CONFIG_X86_MCE_AMD
 173 void mce_amd_feature_init(struct cpuinfo_x86 *c);
 174 #else
 175 static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
 176 #endif
 177
 178 int mce_available(struct cpuinfo_x86 *c);
 179
 180 DECLARE_PER_CPU(unsigned, mce_exception_count);
 181 DECLARE_PER_CPU(unsigned, mce_poll_count);
 182
 183 extern atomic_t mce_entry;
 184
 185 typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
 186 DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);
 187
 188 enum mcp_flags {
 189         MCP_TIMESTAMP = (1 << 0),       /* log time stamp */
 190         MCP_UC = (1 << 1),              /* log uncorrected errors */
 191         MCP_DONTLOG = (1 << 2),         /* only clear, don't log */
 192 };
 193 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
 194
 195 int mce_notify_irq(void);
 196 void mce_notify_process(void);
 197
 198 DECLARE_PER_CPU(struct mce, injectm);
 199 extern struct file_operations mce_chrdev_ops;
 200
 201 /*
 202  * Exception handler
 203  */
 204
 205 /* Call the installed machine check handler for this CPU setup. */
 206 extern void (*machine_check_vector)(struct pt_regs *, long error_code);
 207 void do_machine_check(struct pt_regs *, long);
 208
 209 /*
 210  * Threshold handler
 211  */
 212
 213 extern void (*mce_threshold_vector)(void);
 214 extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
 215
 216 /*
 217  * Thermal handler
 218  */
 219
 220 void intel_init_thermal(struct cpuinfo_x86 *c);
 221
 222 void mce_log_therm_throt_event(__u64 status);
 223
 224 /* Interrupt Handler for core thermal thresholds */
 225 extern int (*platform_thermal_notify)(__u64 msr_val);
 226
 227 #ifdef CONFIG_X86_THERMAL_VECTOR
 228 extern void mcheck_intel_therm_init(void);
 229 #else
 230 static inline void mcheck_intel_therm_init(void) { }
 231 #endif
 232
 233 /*
 234  * Used by APEI to report memory error via /dev/mcelog
 235  */
 236
 237 struct cper_sec_mem_err;
 238 extern void apei_mce_report_mem_error(int corrected,
 239                                       struct cper_sec_mem_err *mem_err);
 240
 241 #endif /* __KERNEL__ */
 242 #endif /* _ASM_X86_MCE_H */