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1 #ifndef _ASM_X86_MWAIT_H
2 #define _ASM_X86_MWAIT_H
4 #include <linux/sched.h>
5 #include <linux/sched/idle.h>
7 #include <asm/cpufeature.h>
8 #include <asm/spec_ctrl.h>
9 #include <asm/microcode.h>
11 #define MWAIT_SUBSTATE_MASK 0xf
12 #define MWAIT_CSTATE_MASK 0xf
13 #define MWAIT_SUBSTATE_SIZE 4
14 #define MWAIT_HINT2CSTATE(hint) (((hint) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK)
15 #define MWAIT_HINT2SUBSTATE(hint) ((hint) & MWAIT_CSTATE_MASK)
17 #define CPUID_MWAIT_LEAF 5
18 #define CPUID5_ECX_EXTENSIONS_SUPPORTED 0x1
19 #define CPUID5_ECX_INTERRUPT_BREAK 0x2
21 #define MWAIT_ECX_INTERRUPT_BREAK 0x1
22 #define MWAITX_ECX_TIMER_ENABLE BIT(1)
23 #define MWAITX_MAX_LOOPS ((u32)-1)
24 #define MWAITX_DISABLE_CSTATES 0xf
26 static inline void __monitor(const void *eax
, unsigned long ecx
,
29 /* "monitor %eax, %ecx, %edx;" */
30 asm volatile(".byte 0x0f, 0x01, 0xc8;"
31 :: "a" (eax
), "c" (ecx
), "d"(edx
));
34 static inline void __monitorx(const void *eax
, unsigned long ecx
,
37 /* "monitorx %eax, %ecx, %edx;" */
38 asm volatile(".byte 0x0f, 0x01, 0xfa;"
39 :: "a" (eax
), "c" (ecx
), "d"(edx
));
42 static inline void __mwait(unsigned long eax
, unsigned long ecx
)
44 /* "mwait %eax, %ecx;" */
45 asm volatile(".byte 0x0f, 0x01, 0xc9;"
46 :: "a" (eax
), "c" (ecx
));
50 * MWAITX allows for a timer expiration to get the core out a wait state in
51 * addition to the default MWAIT exit condition of a store appearing at a
52 * monitored virtual address.
56 * MWAITX ECX[1]: enable timer if set
57 * MWAITX EBX[31:0]: max wait time expressed in SW P0 clocks. The software P0
58 * frequency is the same as the TSC frequency.
60 * Below is a comparison between MWAIT and MWAITX on AMD processors:
63 * opcode 0f 01 c9 | 0f 01 fb
64 * ECX[0] value of RFLAGS.IF seen by instruction
65 * ECX[1] unused/#GP if set | enable timer if set
66 * ECX[31:2] unused/#GP if set
67 * EAX unused (reserve for hint)
68 * EBX[31:0] unused | max wait time (P0 clocks)
71 * opcode 0f 01 c8 | 0f 01 fa
72 * EAX (logical) address to monitor
75 static inline void __mwaitx(unsigned long eax
, unsigned long ebx
,
78 /* "mwaitx %eax, %ebx, %ecx;" */
79 asm volatile(".byte 0x0f, 0x01, 0xfb;"
80 :: "a" (eax
), "b" (ebx
), "c" (ecx
));
83 static inline void __sti_mwait(unsigned long eax
, unsigned long ecx
)
86 /* "mwait %eax, %ecx;" */
87 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
88 :: "a" (eax
), "c" (ecx
));
92 * This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
93 * which can obviate IPI to trigger checking of need_resched.
94 * We execute MONITOR against need_resched and enter optimized wait state
95 * through MWAIT. Whenever someone changes need_resched, we would be woken
96 * up from MWAIT (without an IPI).
98 * New with Core Duo processors, MWAIT can take some hints based on CPU
101 static inline void mwait_idle_with_hints(unsigned long eax
, unsigned long ecx
)
103 if (static_cpu_has_bug(X86_BUG_MONITOR
) || !current_set_polling_and_test()) {
104 if (static_cpu_has_bug(X86_BUG_CLFLUSH_MONITOR
)) {
106 clflush((void *)¤t_thread_info()->flags
);
110 if (boot_cpu_has(X86_FEATURE_SPEC_CTRL
))
111 native_wrmsrl(MSR_IA32_SPEC_CTRL
, 0);
113 __monitor((void *)¤t_thread_info()->flags
, 0, 0);
117 if (boot_cpu_has(X86_FEATURE_SPEC_CTRL
))
118 native_wrmsrl(MSR_IA32_SPEC_CTRL
, FEATURE_ENABLE_IBRS
);
120 current_clr_polling();
123 #endif /* _ASM_X86_MWAIT_H */