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1 #ifndef _ASM_X86_PGTABLE_DEFS_H
2 #define _ASM_X86_PGTABLE_DEFS_H
3
4 #include <linux/const.h>
5 #include <asm/page_types.h>
6
7 #define FIRST_USER_ADDRESS 0UL
8
9 #define _PAGE_BIT_PRESENT 0 /* is present */
10 #define _PAGE_BIT_RW 1 /* writeable */
11 #define _PAGE_BIT_USER 2 /* userspace addressable */
12 #define _PAGE_BIT_PWT 3 /* page write through */
13 #define _PAGE_BIT_PCD 4 /* page cache disabled */
14 #define _PAGE_BIT_ACCESSED 5 /* was accessed (raised by CPU) */
15 #define _PAGE_BIT_DIRTY 6 /* was written to (raised by CPU) */
16 #define _PAGE_BIT_PSE 7 /* 4 MB (or 2MB) page */
17 #define _PAGE_BIT_PAT 7 /* on 4KB pages */
18 #define _PAGE_BIT_GLOBAL 8 /* Global TLB entry PPro+ */
19 #define _PAGE_BIT_SOFTW1 9 /* available for programmer */
20 #define _PAGE_BIT_SOFTW2 10 /* " */
21 #define _PAGE_BIT_SOFTW3 11 /* " */
22 #define _PAGE_BIT_PAT_LARGE 12 /* On 2MB or 1GB pages */
23 #define _PAGE_BIT_SPECIAL _PAGE_BIT_SOFTW1
24 #define _PAGE_BIT_CPA_TEST _PAGE_BIT_SOFTW1
25 #define _PAGE_BIT_HIDDEN _PAGE_BIT_SOFTW3 /* hidden by kmemcheck */
26 #define _PAGE_BIT_SOFT_DIRTY _PAGE_BIT_SOFTW3 /* software dirty tracking */
27 #define _PAGE_BIT_SOFTW4 58 /* available for programmer */
28 #define _PAGE_BIT_DEVMAP _PAGE_BIT_SOFTW4
29 #define _PAGE_BIT_NX 63 /* No execute: only valid after cpuid check */
30
31 /* If _PAGE_BIT_PRESENT is clear, we use these: */
32 /* - if the user mapped it with PROT_NONE; pte_present gives true */
33 #define _PAGE_BIT_PROTNONE _PAGE_BIT_GLOBAL
34
35 #define _PAGE_PRESENT (_AT(pteval_t, 1) << _PAGE_BIT_PRESENT)
36 #define _PAGE_RW (_AT(pteval_t, 1) << _PAGE_BIT_RW)
37 #define _PAGE_USER (_AT(pteval_t, 1) << _PAGE_BIT_USER)
38 #define _PAGE_PWT (_AT(pteval_t, 1) << _PAGE_BIT_PWT)
39 #define _PAGE_PCD (_AT(pteval_t, 1) << _PAGE_BIT_PCD)
40 #define _PAGE_ACCESSED (_AT(pteval_t, 1) << _PAGE_BIT_ACCESSED)
41 #define _PAGE_DIRTY (_AT(pteval_t, 1) << _PAGE_BIT_DIRTY)
42 #define _PAGE_PSE (_AT(pteval_t, 1) << _PAGE_BIT_PSE)
43 #define _PAGE_GLOBAL (_AT(pteval_t, 1) << _PAGE_BIT_GLOBAL)
44 #define _PAGE_SOFTW1 (_AT(pteval_t, 1) << _PAGE_BIT_SOFTW1)
45 #define _PAGE_SOFTW2 (_AT(pteval_t, 1) << _PAGE_BIT_SOFTW2)
46 #define _PAGE_PAT (_AT(pteval_t, 1) << _PAGE_BIT_PAT)
47 #define _PAGE_PAT_LARGE (_AT(pteval_t, 1) << _PAGE_BIT_PAT_LARGE)
48 #define _PAGE_SPECIAL (_AT(pteval_t, 1) << _PAGE_BIT_SPECIAL)
49 #define _PAGE_CPA_TEST (_AT(pteval_t, 1) << _PAGE_BIT_CPA_TEST)
50 #define __HAVE_ARCH_PTE_SPECIAL
51
52 #ifdef CONFIG_KMEMCHECK
53 #define _PAGE_HIDDEN (_AT(pteval_t, 1) << _PAGE_BIT_HIDDEN)
54 #else
55 #define _PAGE_HIDDEN (_AT(pteval_t, 0))
56 #endif
57
58 /*
59 * The same hidden bit is used by kmemcheck, but since kmemcheck
60 * works on kernel pages while soft-dirty engine on user space,
61 * they do not conflict with each other.
62 */
63
64 #ifdef CONFIG_MEM_SOFT_DIRTY
65 #define _PAGE_SOFT_DIRTY (_AT(pteval_t, 1) << _PAGE_BIT_SOFT_DIRTY)
66 #else
67 #define _PAGE_SOFT_DIRTY (_AT(pteval_t, 0))
68 #endif
69
70 /*
71 * Tracking soft dirty bit when a page goes to a swap is tricky.
72 * We need a bit which can be stored in pte _and_ not conflict
73 * with swap entry format. On x86 bits 6 and 7 are *not* involved
74 * into swap entry computation, but bit 6 is used for nonlinear
75 * file mapping, so we borrow bit 7 for soft dirty tracking.
76 *
77 * Please note that this bit must be treated as swap dirty page
78 * mark if and only if the PTE has present bit clear!
79 */
80 #ifdef CONFIG_MEM_SOFT_DIRTY
81 #define _PAGE_SWP_SOFT_DIRTY _PAGE_PSE
82 #else
83 #define _PAGE_SWP_SOFT_DIRTY (_AT(pteval_t, 0))
84 #endif
85
86 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
87 #define _PAGE_NX (_AT(pteval_t, 1) << _PAGE_BIT_NX)
88 #define _PAGE_DEVMAP (_AT(u64, 1) << _PAGE_BIT_DEVMAP)
89 #define __HAVE_ARCH_PTE_DEVMAP
90 #else
91 #define _PAGE_NX (_AT(pteval_t, 0))
92 #define _PAGE_DEVMAP (_AT(pteval_t, 0))
93 #endif
94
95 #define _PAGE_PROTNONE (_AT(pteval_t, 1) << _PAGE_BIT_PROTNONE)
96
97 #define _PAGE_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | \
98 _PAGE_ACCESSED | _PAGE_DIRTY)
99 #define _KERNPG_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | \
100 _PAGE_DIRTY)
101
102 /* Set of bits not changed in pte_modify */
103 #define _PAGE_CHG_MASK (PTE_PFN_MASK | _PAGE_PCD | _PAGE_PWT | \
104 _PAGE_SPECIAL | _PAGE_ACCESSED | _PAGE_DIRTY | \
105 _PAGE_SOFT_DIRTY)
106 #define _HPAGE_CHG_MASK (_PAGE_CHG_MASK | _PAGE_PSE)
107
108 /*
109 * The cache modes defined here are used to translate between pure SW usage
110 * and the HW defined cache mode bits and/or PAT entries.
111 *
112 * The resulting bits for PWT, PCD and PAT should be chosen in a way
113 * to have the WB mode at index 0 (all bits clear). This is the default
114 * right now and likely would break too much if changed.
115 */
116 #ifndef __ASSEMBLY__
117 enum page_cache_mode {
118 _PAGE_CACHE_MODE_WB = 0,
119 _PAGE_CACHE_MODE_WC = 1,
120 _PAGE_CACHE_MODE_UC_MINUS = 2,
121 _PAGE_CACHE_MODE_UC = 3,
122 _PAGE_CACHE_MODE_WT = 4,
123 _PAGE_CACHE_MODE_WP = 5,
124 _PAGE_CACHE_MODE_NUM = 8
125 };
126 #endif
127
128 #define _PAGE_CACHE_MASK (_PAGE_PAT | _PAGE_PCD | _PAGE_PWT)
129 #define _PAGE_NOCACHE (cachemode2protval(_PAGE_CACHE_MODE_UC))
130
131 #define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_ACCESSED)
132 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | \
133 _PAGE_ACCESSED | _PAGE_NX)
134
135 #define PAGE_SHARED_EXEC __pgprot(_PAGE_PRESENT | _PAGE_RW | \
136 _PAGE_USER | _PAGE_ACCESSED)
137 #define PAGE_COPY_NOEXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | \
138 _PAGE_ACCESSED | _PAGE_NX)
139 #define PAGE_COPY_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | \
140 _PAGE_ACCESSED)
141 #define PAGE_COPY PAGE_COPY_NOEXEC
142 #define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | \
143 _PAGE_ACCESSED | _PAGE_NX)
144 #define PAGE_READONLY_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | \
145 _PAGE_ACCESSED)
146
147 #define __PAGE_KERNEL_EXEC \
148 (_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_GLOBAL)
149 #define __PAGE_KERNEL (__PAGE_KERNEL_EXEC | _PAGE_NX)
150
151 #define __PAGE_KERNEL_RO (__PAGE_KERNEL & ~_PAGE_RW)
152 #define __PAGE_KERNEL_RX (__PAGE_KERNEL_EXEC & ~_PAGE_RW)
153 #define __PAGE_KERNEL_NOCACHE (__PAGE_KERNEL | _PAGE_NOCACHE)
154 #define __PAGE_KERNEL_VSYSCALL (__PAGE_KERNEL_RX | _PAGE_USER)
155 #define __PAGE_KERNEL_VVAR (__PAGE_KERNEL_RO | _PAGE_USER)
156 #define __PAGE_KERNEL_LARGE (__PAGE_KERNEL | _PAGE_PSE)
157 #define __PAGE_KERNEL_LARGE_EXEC (__PAGE_KERNEL_EXEC | _PAGE_PSE)
158
159 #define __PAGE_KERNEL_IO (__PAGE_KERNEL)
160 #define __PAGE_KERNEL_IO_NOCACHE (__PAGE_KERNEL_NOCACHE)
161
162 #define PAGE_KERNEL __pgprot(__PAGE_KERNEL)
163 #define PAGE_KERNEL_RO __pgprot(__PAGE_KERNEL_RO)
164 #define PAGE_KERNEL_EXEC __pgprot(__PAGE_KERNEL_EXEC)
165 #define PAGE_KERNEL_RX __pgprot(__PAGE_KERNEL_RX)
166 #define PAGE_KERNEL_NOCACHE __pgprot(__PAGE_KERNEL_NOCACHE)
167 #define PAGE_KERNEL_LARGE __pgprot(__PAGE_KERNEL_LARGE)
168 #define PAGE_KERNEL_LARGE_EXEC __pgprot(__PAGE_KERNEL_LARGE_EXEC)
169 #define PAGE_KERNEL_VSYSCALL __pgprot(__PAGE_KERNEL_VSYSCALL)
170 #define PAGE_KERNEL_VVAR __pgprot(__PAGE_KERNEL_VVAR)
171
172 #define PAGE_KERNEL_IO __pgprot(__PAGE_KERNEL_IO)
173 #define PAGE_KERNEL_IO_NOCACHE __pgprot(__PAGE_KERNEL_IO_NOCACHE)
174
175 /* xwr */
176 #define __P000 PAGE_NONE
177 #define __P001 PAGE_READONLY
178 #define __P010 PAGE_COPY
179 #define __P011 PAGE_COPY
180 #define __P100 PAGE_READONLY_EXEC
181 #define __P101 PAGE_READONLY_EXEC
182 #define __P110 PAGE_COPY_EXEC
183 #define __P111 PAGE_COPY_EXEC
184
185 #define __S000 PAGE_NONE
186 #define __S001 PAGE_READONLY
187 #define __S010 PAGE_SHARED
188 #define __S011 PAGE_SHARED
189 #define __S100 PAGE_READONLY_EXEC
190 #define __S101 PAGE_READONLY_EXEC
191 #define __S110 PAGE_SHARED_EXEC
192 #define __S111 PAGE_SHARED_EXEC
193
194 /*
195 * early identity mapping pte attrib macros.
196 */
197 #ifdef CONFIG_X86_64
198 #define __PAGE_KERNEL_IDENT_LARGE_EXEC __PAGE_KERNEL_LARGE_EXEC
199 #else
200 #define PTE_IDENT_ATTR 0x003 /* PRESENT+RW */
201 #define PDE_IDENT_ATTR 0x063 /* PRESENT+RW+DIRTY+ACCESSED */
202 #define PGD_IDENT_ATTR 0x001 /* PRESENT (no other attributes) */
203 #endif
204
205 #ifdef CONFIG_X86_32
206 # include <asm/pgtable_32_types.h>
207 #else
208 # include <asm/pgtable_64_types.h>
209 #endif
210
211 #ifndef __ASSEMBLY__
212
213 #include <linux/types.h>
214
215 /* Extracts the PFN from a (pte|pmd|pud|pgd)val_t of a 4KB page */
216 #define PTE_PFN_MASK ((pteval_t)PHYSICAL_PAGE_MASK)
217
218 /* Extracts the flags from a (pte|pmd|pud|pgd)val_t of a 4KB page */
219 #define PTE_FLAGS_MASK (~PTE_PFN_MASK)
220
221 typedef struct pgprot { pgprotval_t pgprot; } pgprot_t;
222
223 typedef struct { pgdval_t pgd; } pgd_t;
224
225 static inline pgd_t native_make_pgd(pgdval_t val)
226 {
227 return (pgd_t) { val };
228 }
229
230 static inline pgdval_t native_pgd_val(pgd_t pgd)
231 {
232 return pgd.pgd;
233 }
234
235 static inline pgdval_t pgd_flags(pgd_t pgd)
236 {
237 return native_pgd_val(pgd) & PTE_FLAGS_MASK;
238 }
239
240 #if CONFIG_PGTABLE_LEVELS > 3
241 typedef struct { pudval_t pud; } pud_t;
242
243 static inline pud_t native_make_pud(pmdval_t val)
244 {
245 return (pud_t) { val };
246 }
247
248 static inline pudval_t native_pud_val(pud_t pud)
249 {
250 return pud.pud;
251 }
252 #else
253 #include <asm-generic/pgtable-nopud.h>
254
255 static inline pudval_t native_pud_val(pud_t pud)
256 {
257 return native_pgd_val(pud.pgd);
258 }
259 #endif
260
261 #if CONFIG_PGTABLE_LEVELS > 2
262 typedef struct { pmdval_t pmd; } pmd_t;
263
264 static inline pmd_t native_make_pmd(pmdval_t val)
265 {
266 return (pmd_t) { val };
267 }
268
269 static inline pmdval_t native_pmd_val(pmd_t pmd)
270 {
271 return pmd.pmd;
272 }
273 #else
274 #include <asm-generic/pgtable-nopmd.h>
275
276 static inline pmdval_t native_pmd_val(pmd_t pmd)
277 {
278 return native_pgd_val(pmd.pud.pgd);
279 }
280 #endif
281
282 static inline pudval_t pud_pfn_mask(pud_t pud)
283 {
284 if (native_pud_val(pud) & _PAGE_PSE)
285 return PHYSICAL_PUD_PAGE_MASK;
286 else
287 return PTE_PFN_MASK;
288 }
289
290 static inline pudval_t pud_flags_mask(pud_t pud)
291 {
292 return ~pud_pfn_mask(pud);
293 }
294
295 static inline pudval_t pud_flags(pud_t pud)
296 {
297 return native_pud_val(pud) & pud_flags_mask(pud);
298 }
299
300 static inline pmdval_t pmd_pfn_mask(pmd_t pmd)
301 {
302 if (native_pmd_val(pmd) & _PAGE_PSE)
303 return PHYSICAL_PMD_PAGE_MASK;
304 else
305 return PTE_PFN_MASK;
306 }
307
308 static inline pmdval_t pmd_flags_mask(pmd_t pmd)
309 {
310 return ~pmd_pfn_mask(pmd);
311 }
312
313 static inline pmdval_t pmd_flags(pmd_t pmd)
314 {
315 return native_pmd_val(pmd) & pmd_flags_mask(pmd);
316 }
317
318 static inline pte_t native_make_pte(pteval_t val)
319 {
320 return (pte_t) { .pte = val };
321 }
322
323 static inline pteval_t native_pte_val(pte_t pte)
324 {
325 return pte.pte;
326 }
327
328 static inline pteval_t pte_flags(pte_t pte)
329 {
330 return native_pte_val(pte) & PTE_FLAGS_MASK;
331 }
332
333 #define pgprot_val(x) ((x).pgprot)
334 #define __pgprot(x) ((pgprot_t) { (x) } )
335
336 extern uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM];
337 extern uint8_t __pte2cachemode_tbl[8];
338
339 #define __pte2cm_idx(cb) \
340 ((((cb) >> (_PAGE_BIT_PAT - 2)) & 4) | \
341 (((cb) >> (_PAGE_BIT_PCD - 1)) & 2) | \
342 (((cb) >> _PAGE_BIT_PWT) & 1))
343 #define __cm_idx2pte(i) \
344 ((((i) & 4) << (_PAGE_BIT_PAT - 2)) | \
345 (((i) & 2) << (_PAGE_BIT_PCD - 1)) | \
346 (((i) & 1) << _PAGE_BIT_PWT))
347
348 static inline unsigned long cachemode2protval(enum page_cache_mode pcm)
349 {
350 if (likely(pcm == 0))
351 return 0;
352 return __cachemode2pte_tbl[pcm];
353 }
354 static inline pgprot_t cachemode2pgprot(enum page_cache_mode pcm)
355 {
356 return __pgprot(cachemode2protval(pcm));
357 }
358 static inline enum page_cache_mode pgprot2cachemode(pgprot_t pgprot)
359 {
360 unsigned long masked;
361
362 masked = pgprot_val(pgprot) & _PAGE_CACHE_MASK;
363 if (likely(masked == 0))
364 return 0;
365 return __pte2cachemode_tbl[__pte2cm_idx(masked)];
366 }
367 static inline pgprot_t pgprot_4k_2_large(pgprot_t pgprot)
368 {
369 pgprot_t new;
370 unsigned long val;
371
372 val = pgprot_val(pgprot);
373 pgprot_val(new) = (val & ~(_PAGE_PAT | _PAGE_PAT_LARGE)) |
374 ((val & _PAGE_PAT) << (_PAGE_BIT_PAT_LARGE - _PAGE_BIT_PAT));
375 return new;
376 }
377 static inline pgprot_t pgprot_large_2_4k(pgprot_t pgprot)
378 {
379 pgprot_t new;
380 unsigned long val;
381
382 val = pgprot_val(pgprot);
383 pgprot_val(new) = (val & ~(_PAGE_PAT | _PAGE_PAT_LARGE)) |
384 ((val & _PAGE_PAT_LARGE) >>
385 (_PAGE_BIT_PAT_LARGE - _PAGE_BIT_PAT));
386 return new;
387 }
388
389
390 typedef struct page *pgtable_t;
391
392 extern pteval_t __supported_pte_mask;
393 extern void set_nx(void);
394 extern int nx_enabled;
395
396 #define pgprot_writecombine pgprot_writecombine
397 extern pgprot_t pgprot_writecombine(pgprot_t prot);
398
399 #define pgprot_writethrough pgprot_writethrough
400 extern pgprot_t pgprot_writethrough(pgprot_t prot);
401
402 /* Indicate that x86 has its own track and untrack pfn vma functions */
403 #define __HAVE_PFNMAP_TRACKING
404
405 #define __HAVE_PHYS_MEM_ACCESS_PROT
406 struct file;
407 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
408 unsigned long size, pgprot_t vma_prot);
409 int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn,
410 unsigned long size, pgprot_t *vma_prot);
411
412 /* Install a pte for a particular vaddr in kernel space. */
413 void set_pte_vaddr(unsigned long vaddr, pte_t pte);
414
415 #ifdef CONFIG_X86_32
416 extern void native_pagetable_init(void);
417 #else
418 #define native_pagetable_init paging_init
419 #endif
420
421 struct seq_file;
422 extern void arch_report_meminfo(struct seq_file *m);
423
424 enum pg_level {
425 PG_LEVEL_NONE,
426 PG_LEVEL_4K,
427 PG_LEVEL_2M,
428 PG_LEVEL_1G,
429 PG_LEVEL_NUM
430 };
431
432 #ifdef CONFIG_PROC_FS
433 extern void update_page_count(int level, unsigned long pages);
434 #else
435 static inline void update_page_count(int level, unsigned long pages) { }
436 #endif
437
438 /*
439 * Helper function that returns the kernel pagetable entry controlling
440 * the virtual address 'address'. NULL means no pagetable entry present.
441 * NOTE: the return type is pte_t but if the pmd is PSE then we return it
442 * as a pte too.
443 */
444 extern pte_t *lookup_address(unsigned long address, unsigned int *level);
445 extern pte_t *lookup_address_in_pgd(pgd_t *pgd, unsigned long address,
446 unsigned int *level);
447 extern pmd_t *lookup_pmd_address(unsigned long address);
448 extern phys_addr_t slow_virt_to_phys(void *__address);
449 extern int kernel_map_pages_in_pgd(pgd_t *pgd, u64 pfn, unsigned long address,
450 unsigned numpages, unsigned long page_flags);
451 void kernel_unmap_pages_in_pgd(pgd_t *root, unsigned long address,
452 unsigned numpages);
453 #endif /* !__ASSEMBLY__ */
454
455 #endif /* _ASM_X86_PGTABLE_DEFS_H */