arch/x86/include/asm/processor.h

   1 #ifndef _ASM_X86_PROCESSOR_H
   2 #define _ASM_X86_PROCESSOR_H
   3
   4 #include <asm/processor-flags.h>
   5
   6 /* Forward declaration, a strange C thing */
   7 struct task_struct;
   8 struct mm_struct;
   9
  10 #include <asm/vm86.h>
  11 #include <asm/math_emu.h>
  12 #include <asm/segment.h>
  13 #include <asm/types.h>
  14 #include <asm/sigcontext.h>
  15 #include <asm/current.h>
  16 #include <asm/cpufeature.h>
  17 #include <asm/page.h>
  18 #include <asm/pgtable_types.h>
  19 #include <asm/percpu.h>
  20 #include <asm/msr.h>
  21 #include <asm/desc_defs.h>
  22 #include <asm/nops.h>
  23 #include <asm/special_insns.h>
  24
  25 #include <linux/personality.h>
  26 #include <linux/cpumask.h>
  27 #include <linux/cache.h>
  28 #include <linux/threads.h>
  29 #include <linux/math64.h>
  30 #include <linux/init.h>
  31 #include <linux/err.h>
  32 #include <linux/irqflags.h>
  33
  34 /*
  35  * We handle most unaligned accesses in hardware.  On the other hand
  36  * unaligned DMA can be quite expensive on some Nehalem processors.
  37  *
  38  * Based on this we disable the IP header alignment in network drivers.
  39  */
  40 #define NET_IP_ALIGN    0
  41
  42 #define HBP_NUM 4
  43 /*
  44  * Default implementation of macro that returns current
  45  * instruction pointer ("program counter").
  46  */
  47 static inline void *current_text_addr(void)
  48 {
  49         void *pc;
  50
  51         asm volatile("mov $1f, %0; 1:":"=r" (pc));
  52
  53         return pc;
  54 }
  55
  56 #ifdef CONFIG_X86_VSMP
  57 # define ARCH_MIN_TASKALIGN             (1 << INTERNODE_CACHE_SHIFT)
  58 # define ARCH_MIN_MMSTRUCT_ALIGN        (1 << INTERNODE_CACHE_SHIFT)
  59 #else
  60 # define ARCH_MIN_TASKALIGN             16
  61 # define ARCH_MIN_MMSTRUCT_ALIGN        0
  62 #endif
  63
  64 enum tlb_infos {
  65         ENTRIES,
  66         NR_INFO
  67 };
  68
  69 extern u16 __read_mostly tlb_lli_4k[NR_INFO];
  70 extern u16 __read_mostly tlb_lli_2m[NR_INFO];
  71 extern u16 __read_mostly tlb_lli_4m[NR_INFO];
  72 extern u16 __read_mostly tlb_lld_4k[NR_INFO];
  73 extern u16 __read_mostly tlb_lld_2m[NR_INFO];
  74 extern u16 __read_mostly tlb_lld_4m[NR_INFO];
  75 extern u16 __read_mostly tlb_lld_1g[NR_INFO];
  76 extern s8  __read_mostly tlb_flushall_shift;
  77
  78 /*
  79  *  CPU type and hardware bug flags. Kept separately for each CPU.
  80  *  Members of this structure are referenced in head.S, so think twice
  81  *  before touching them. [mj]
  82  */
  83
  84 struct cpuinfo_x86 {
  85         __u8                    x86;            /* CPU family */
  86         __u8                    x86_vendor;     /* CPU vendor */
  87         __u8                    x86_model;
  88         __u8                    x86_mask;
  89 #ifdef CONFIG_X86_32
  90         char                    wp_works_ok;    /* It doesn't on 386's */
  91
  92         /* Problems on some 486Dx4's and old 386's: */
  93         char                    rfu;
  94         char                    pad0;
  95         char                    pad1;
  96 #else
  97         /* Number of 4K pages in DTLB/ITLB combined(in pages): */
  98         int                     x86_tlbsize;
  99 #endif
 100         __u8                    x86_virt_bits;
 101         __u8                    x86_phys_bits;
 102         /* CPUID returned core id bits: */
 103         __u8                    x86_coreid_bits;
 104         /* Max extended CPUID function supported: */
 105         __u32                   extended_cpuid_level;
 106         /* Maximum supported CPUID level, -1=no CPUID: */
 107         int                     cpuid_level;
 108         __u32                   x86_capability[NCAPINTS + NBUGINTS];
 109         char                    x86_vendor_id[16];
 110         char                    x86_model_id[64];
 111         /* in KB - valid for CPUS which support this call: */
 112         int                     x86_cache_size;
 113         int                     x86_cache_alignment;    /* In bytes */
 114         int                     x86_power;
 115         unsigned long           loops_per_jiffy;
 116         /* cpuid returned max cores value: */
 117         u16                      x86_max_cores;
 118         u16                     apicid;
 119         u16                     initial_apicid;
 120         u16                     x86_clflush_size;
 121         /* number of cores as seen by the OS: */
 122         u16                     booted_cores;
 123         /* Physical processor id: */
 124         u16                     phys_proc_id;
 125         /* Core id: */
 126         u16                     cpu_core_id;
 127         /* Compute unit id */
 128         u8                      compute_unit_id;
 129         /* Index into per_cpu list: */
 130         u16                     cpu_index;
 131         u32                     microcode;
 132 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
 133
 134 #define X86_VENDOR_INTEL        0
 135 #define X86_VENDOR_CYRIX        1
 136 #define X86_VENDOR_AMD          2
 137 #define X86_VENDOR_UMC          3
 138 #define X86_VENDOR_CENTAUR      5
 139 #define X86_VENDOR_TRANSMETA    7
 140 #define X86_VENDOR_NSC          8
 141 #define X86_VENDOR_NUM          9
 142
 143 #define X86_VENDOR_UNKNOWN      0xff
 144
 145 /*
 146  * capabilities of CPUs
 147  */
 148 extern struct cpuinfo_x86       boot_cpu_data;
 149 extern struct cpuinfo_x86       new_cpu_data;
 150
 151 extern struct tss_struct        doublefault_tss;
 152 extern __u32                    cpu_caps_cleared[NCAPINTS];
 153 extern __u32                    cpu_caps_set[NCAPINTS];
 154
 155 #ifdef CONFIG_SMP
 156 DECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
 157 #define cpu_data(cpu)           per_cpu(cpu_info, cpu)
 158 #else
 159 #define cpu_info                boot_cpu_data
 160 #define cpu_data(cpu)           boot_cpu_data
 161 #endif
 162
 163 extern const struct seq_operations cpuinfo_op;
 164
 165 #define cache_line_size()       (boot_cpu_data.x86_cache_alignment)
 166
 167 extern void cpu_detect(struct cpuinfo_x86 *c);
 168 extern void fpu_detect(struct cpuinfo_x86 *c);
 169
 170 extern void early_cpu_init(void);
 171 extern void identify_boot_cpu(void);
 172 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
 173 extern void print_cpu_info(struct cpuinfo_x86 *);
 174 void print_cpu_msr(struct cpuinfo_x86 *);
 175 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
 176 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
 177 extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);
 178
 179 extern void detect_extended_topology(struct cpuinfo_x86 *c);
 180 extern void detect_ht(struct cpuinfo_x86 *c);
 181
 182 #ifdef CONFIG_X86_32
 183 extern int have_cpuid_p(void);
 184 #else
 185 static inline int have_cpuid_p(void)
 186 {
 187         return 1;
 188 }
 189 #endif
 190 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
 191                                 unsigned int *ecx, unsigned int *edx)
 192 {
 193         /* ecx is often an input as well as an output. */
 194         asm volatile("cpuid"
 195             : "=a" (*eax),
 196               "=b" (*ebx),
 197               "=c" (*ecx),
 198               "=d" (*edx)
 199             : "0" (*eax), "2" (*ecx)
 200             : "memory");
 201 }
 202
 203 static inline void load_cr3(pgd_t *pgdir)
 204 {
 205         write_cr3(__pa(pgdir));
 206 }
 207
 208 #ifdef CONFIG_X86_32
 209 /* This is the TSS defined by the hardware. */
 210 struct x86_hw_tss {
 211         unsigned short          back_link, __blh;
 212         unsigned long           sp0;
 213         unsigned short          ss0, __ss0h;
 214         unsigned long           sp1;
 215         /* ss1 caches MSR_IA32_SYSENTER_CS: */
 216         unsigned short          ss1, __ss1h;
 217         unsigned long           sp2;
 218         unsigned short          ss2, __ss2h;
 219         unsigned long           __cr3;
 220         unsigned long           ip;
 221         unsigned long           flags;
 222         unsigned long           ax;
 223         unsigned long           cx;
 224         unsigned long           dx;
 225         unsigned long           bx;
 226         unsigned long           sp;
 227         unsigned long           bp;
 228         unsigned long           si;
 229         unsigned long           di;
 230         unsigned short          es, __esh;
 231         unsigned short          cs, __csh;
 232         unsigned short          ss, __ssh;
 233         unsigned short          ds, __dsh;
 234         unsigned short          fs, __fsh;
 235         unsigned short          gs, __gsh;
 236         unsigned short          ldt, __ldth;
 237         unsigned short          trace;
 238         unsigned short          io_bitmap_base;
 239
 240 } __attribute__((packed));
 241 #else
 242 struct x86_hw_tss {
 243         u32                     reserved1;
 244         u64                     sp0;
 245         u64                     sp1;
 246         u64                     sp2;
 247         u64                     reserved2;
 248         u64                     ist[7];
 249         u32                     reserved3;
 250         u32                     reserved4;
 251         u16                     reserved5;
 252         u16                     io_bitmap_base;
 253
 254 } __attribute__((packed)) ____cacheline_aligned;
 255 #endif
 256
 257 /*
 258  * IO-bitmap sizes:
 259  */
 260 #define IO_BITMAP_BITS                  65536
 261 #define IO_BITMAP_BYTES                 (IO_BITMAP_BITS/8)
 262 #define IO_BITMAP_LONGS                 (IO_BITMAP_BYTES/sizeof(long))
 263 #define IO_BITMAP_OFFSET                offsetof(struct tss_struct, io_bitmap)
 264 #define INVALID_IO_BITMAP_OFFSET        0x8000
 265
 266 struct tss_struct {
 267         /*
 268          * The hardware state:
 269          */
 270         struct x86_hw_tss       x86_tss;
 271
 272         /*
 273          * The extra 1 is there because the CPU will access an
 274          * additional byte beyond the end of the IO permission
 275          * bitmap. The extra byte must be all 1 bits, and must
 276          * be within the limit.
 277          */
 278         unsigned long           io_bitmap[IO_BITMAP_LONGS + 1];
 279
 280         /*
 281          * .. and then another 0x100 bytes for the emergency kernel stack:
 282          */
 283         unsigned long           stack[64];
 284
 285 } ____cacheline_aligned;
 286
 287 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss);
 288
 289 /*
 290  * Save the original ist values for checking stack pointers during debugging
 291  */
 292 struct orig_ist {
 293         unsigned long           ist[7];
 294 };
 295
 296 #define MXCSR_DEFAULT           0x1f80
 297
 298 struct i387_fsave_struct {
 299         u32                     cwd;    /* FPU Control Word             */
 300         u32                     swd;    /* FPU Status Word              */
 301         u32                     twd;    /* FPU Tag Word                 */
 302         u32                     fip;    /* FPU IP Offset                */
 303         u32                     fcs;    /* FPU IP Selector              */
 304         u32                     foo;    /* FPU Operand Pointer Offset   */
 305         u32                     fos;    /* FPU Operand Pointer Selector */
 306
 307         /* 8*10 bytes for each FP-reg = 80 bytes:                       */
 308         u32                     st_space[20];
 309
 310         /* Software status information [not touched by FSAVE ]:         */
 311         u32                     status;
 312 };
 313
 314 struct i387_fxsave_struct {
 315         u16                     cwd; /* Control Word                    */
 316         u16                     swd; /* Status Word                     */
 317         u16                     twd; /* Tag Word                        */
 318         u16                     fop; /* Last Instruction Opcode         */
 319         union {
 320                 struct {
 321                         u64     rip; /* Instruction Pointer             */
 322                         u64     rdp; /* Data Pointer                    */
 323                 };
 324                 struct {
 325                         u32     fip; /* FPU IP Offset                   */
 326                         u32     fcs; /* FPU IP Selector                 */
 327                         u32     foo; /* FPU Operand Offset              */
 328                         u32     fos; /* FPU Operand Selector            */
 329                 };
 330         };
 331         u32                     mxcsr;          /* MXCSR Register State */
 332         u32                     mxcsr_mask;     /* MXCSR Mask           */
 333
 334         /* 8*16 bytes for each FP-reg = 128 bytes:                      */
 335         u32                     st_space[32];
 336
 337         /* 16*16 bytes for each XMM-reg = 256 bytes:                    */
 338         u32                     xmm_space[64];
 339
 340         u32                     padding[12];
 341
 342         union {
 343                 u32             padding1[12];
 344                 u32             sw_reserved[12];
 345         };
 346
 347 } __attribute__((aligned(16)));
 348
 349 struct i387_soft_struct {
 350         u32                     cwd;
 351         u32                     swd;
 352         u32                     twd;
 353         u32                     fip;
 354         u32                     fcs;
 355         u32                     foo;
 356         u32                     fos;
 357         /* 8*10 bytes for each FP-reg = 80 bytes: */
 358         u32                     st_space[20];
 359         u8                      ftop;
 360         u8                      changed;
 361         u8                      lookahead;
 362         u8                      no_update;
 363         u8                      rm;
 364         u8                      alimit;
 365         struct math_emu_info    *info;
 366         u32                     entry_eip;
 367 };
 368
 369 struct ymmh_struct {
 370         /* 16 * 16 bytes for each YMMH-reg = 256 bytes */
 371         u32 ymmh_space[64];
 372 };
 373
 374 struct xsave_hdr_struct {
 375         u64 xstate_bv;
 376         u64 reserved1[2];
 377         u64 reserved2[5];
 378 } __attribute__((packed));
 379
 380 struct xsave_struct {
 381         struct i387_fxsave_struct i387;
 382         struct xsave_hdr_struct xsave_hdr;
 383         struct ymmh_struct ymmh;
 384         /* new processor state extensions will go here */
 385 } __attribute__ ((packed, aligned (64)));
 386
 387 union thread_xstate {
 388         struct i387_fsave_struct        fsave;
 389         struct i387_fxsave_struct       fxsave;
 390         struct i387_soft_struct         soft;
 391         struct xsave_struct             xsave;
 392 };
 393
 394 struct fpu {
 395         unsigned int last_cpu;
 396         unsigned int has_fpu;
 397         union thread_xstate *state;
 398 };
 399
 400 #ifdef CONFIG_X86_64
 401 DECLARE_PER_CPU(struct orig_ist, orig_ist);
 402
 403 union irq_stack_union {
 404         char irq_stack[IRQ_STACK_SIZE];
 405         /*
 406          * GCC hardcodes the stack canary as %gs:40.  Since the
 407          * irq_stack is the object at %gs:0, we reserve the bottom
 408          * 48 bytes of the irq stack for the canary.
 409          */
 410         struct {
 411                 char gs_base[40];
 412                 unsigned long stack_canary;
 413         };
 414 };
 415
 416 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union) __visible;
 417 DECLARE_INIT_PER_CPU(irq_stack_union);
 418
 419 DECLARE_PER_CPU(char *, irq_stack_ptr);
 420 DECLARE_PER_CPU(unsigned int, irq_count);
 421 extern asmlinkage void ignore_sysret(void);
 422 #else   /* X86_64 */
 423 #ifdef CONFIG_CC_STACKPROTECTOR
 424 /*
 425  * Make sure stack canary segment base is cached-aligned:
 426  *   "For Intel Atom processors, avoid non zero segment base address
 427  *    that is not aligned to cache line boundary at all cost."
 428  * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
 429  */
 430 struct stack_canary {
 431         char __pad[20];         /* canary at %gs:20 */
 432         unsigned long canary;
 433 };
 434 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
 435 #endif
 436 #endif  /* X86_64 */
 437
 438 extern unsigned int xstate_size;
 439 extern void free_thread_xstate(struct task_struct *);
 440 extern struct kmem_cache *task_xstate_cachep;
 441
 442 struct perf_event;
 443
 444 struct thread_struct {
 445         /* Cached TLS descriptors: */
 446         struct desc_struct      tls_array[GDT_ENTRY_TLS_ENTRIES];
 447         unsigned long           sp0;
 448         unsigned long           sp;
 449 #ifdef CONFIG_X86_32
 450         unsigned long           sysenter_cs;
 451 #else
 452         unsigned long           usersp; /* Copy from PDA */
 453         unsigned short          es;
 454         unsigned short          ds;
 455         unsigned short          fsindex;
 456         unsigned short          gsindex;
 457 #endif
 458 #ifdef CONFIG_X86_32
 459         unsigned long           ip;
 460 #endif
 461 #ifdef CONFIG_X86_64
 462         unsigned long           fs;
 463 #endif
 464         unsigned long           gs;
 465         /* Save middle states of ptrace breakpoints */
 466         struct perf_event       *ptrace_bps[HBP_NUM];
 467         /* Debug status used for traps, single steps, etc... */
 468         unsigned long           debugreg6;
 469         /* Keep track of the exact dr7 value set by the user */
 470         unsigned long           ptrace_dr7;
 471         /* Fault info: */
 472         unsigned long           cr2;
 473         unsigned long           trap_nr;
 474         unsigned long           error_code;
 475         /* floating point and extended processor state */
 476         struct fpu              fpu;
 477 #ifdef CONFIG_X86_32
 478         /* Virtual 86 mode info */
 479         struct vm86_struct __user *vm86_info;
 480         unsigned long           screen_bitmap;
 481         unsigned long           v86flags;
 482         unsigned long           v86mask;
 483         unsigned long           saved_sp0;
 484         unsigned int            saved_fs;
 485         unsigned int            saved_gs;
 486 #endif
 487         /* IO permissions: */
 488         unsigned long           *io_bitmap_ptr;
 489         unsigned long           iopl;
 490         /* Max allowed port in the bitmap, in bytes: */
 491         unsigned                io_bitmap_max;
 492         /*
 493          * fpu_counter contains the number of consecutive context switches
 494          * that the FPU is used. If this is over a threshold, the lazy fpu
 495          * saving becomes unlazy to save the trap. This is an unsigned char
 496          * so that after 256 times the counter wraps and the behavior turns
 497          * lazy again; this to deal with bursty apps that only use FPU for
 498          * a short time
 499          */
 500         unsigned char fpu_counter;
 501 };
 502
 503 /*
 504  * Set IOPL bits in EFLAGS from given mask
 505  */
 506 static inline void native_set_iopl_mask(unsigned mask)
 507 {
 508 #ifdef CONFIG_X86_32
 509         unsigned int reg;
 510
 511         asm volatile ("pushfl;"
 512                       "popl %0;"
 513                       "andl %1, %0;"
 514                       "orl %2, %0;"
 515                       "pushl %0;"
 516                       "popfl"
 517                       : "=&r" (reg)
 518                       : "i" (~X86_EFLAGS_IOPL), "r" (mask));
 519 #endif
 520 }
 521
 522 static inline void
 523 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
 524 {
 525         tss->x86_tss.sp0 = thread->sp0;
 526 #ifdef CONFIG_X86_32
 527         /* Only happens when SEP is enabled, no need to test "SEP"arately: */
 528         if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
 529                 tss->x86_tss.ss1 = thread->sysenter_cs;
 530                 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
 531         }
 532 #endif
 533 }
 534
 535 static inline void native_swapgs(void)
 536 {
 537 #ifdef CONFIG_X86_64
 538         asm volatile("swapgs" ::: "memory");
 539 #endif
 540 }
 541
 542 #ifdef CONFIG_PARAVIRT
 543 #include <asm/paravirt.h>
 544 #else
 545 #define __cpuid                 native_cpuid
 546 #define paravirt_enabled()      0
 547
 548 static inline void load_sp0(struct tss_struct *tss,
 549                             struct thread_struct *thread)
 550 {
 551         native_load_sp0(tss, thread);
 552 }
 553
 554 #define set_iopl_mask native_set_iopl_mask
 555 #endif /* CONFIG_PARAVIRT */
 556
 557 /*
 558  * Save the cr4 feature set we're using (ie
 559  * Pentium 4MB enable and PPro Global page
 560  * enable), so that any CPU's that boot up
 561  * after us can get the correct flags.
 562  */
 563 extern unsigned long mmu_cr4_features;
 564 extern u32 *trampoline_cr4_features;
 565
 566 static inline void set_in_cr4(unsigned long mask)
 567 {
 568         unsigned long cr4;
 569
 570         mmu_cr4_features |= mask;
 571         if (trampoline_cr4_features)
 572                 *trampoline_cr4_features = mmu_cr4_features;
 573         cr4 = read_cr4();
 574         cr4 |= mask;
 575         write_cr4(cr4);
 576 }
 577
 578 static inline void clear_in_cr4(unsigned long mask)
 579 {
 580         unsigned long cr4;
 581
 582         mmu_cr4_features &= ~mask;
 583         if (trampoline_cr4_features)
 584                 *trampoline_cr4_features = mmu_cr4_features;
 585         cr4 = read_cr4();
 586         cr4 &= ~mask;
 587         write_cr4(cr4);
 588 }
 589
 590 typedef struct {
 591         unsigned long           seg;
 592 } mm_segment_t;
 593
 594
 595 /* Free all resources held by a thread. */
 596 extern void release_thread(struct task_struct *);
 597
 598 unsigned long get_wchan(struct task_struct *p);
 599
 600 /*
 601  * Generic CPUID function
 602  * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
 603  * resulting in stale register contents being returned.
 604  */
 605 static inline void cpuid(unsigned int op,
 606                          unsigned int *eax, unsigned int *ebx,
 607                          unsigned int *ecx, unsigned int *edx)
 608 {
 609         *eax = op;
 610         *ecx = 0;
 611         __cpuid(eax, ebx, ecx, edx);
 612 }
 613
 614 /* Some CPUID calls want 'count' to be placed in ecx */
 615 static inline void cpuid_count(unsigned int op, int count,
 616                                unsigned int *eax, unsigned int *ebx,
 617                                unsigned int *ecx, unsigned int *edx)
 618 {
 619         *eax = op;
 620         *ecx = count;
 621         __cpuid(eax, ebx, ecx, edx);
 622 }
 623
 624 /*
 625  * CPUID functions returning a single datum
 626  */
 627 static inline unsigned int cpuid_eax(unsigned int op)
 628 {
 629         unsigned int eax, ebx, ecx, edx;
 630
 631         cpuid(op, &eax, &ebx, &ecx, &edx);
 632
 633         return eax;
 634 }
 635
 636 static inline unsigned int cpuid_ebx(unsigned int op)
 637 {
 638         unsigned int eax, ebx, ecx, edx;
 639
 640         cpuid(op, &eax, &ebx, &ecx, &edx);
 641
 642         return ebx;
 643 }
 644
 645 static inline unsigned int cpuid_ecx(unsigned int op)
 646 {
 647         unsigned int eax, ebx, ecx, edx;
 648
 649         cpuid(op, &eax, &ebx, &ecx, &edx);
 650
 651         return ecx;
 652 }
 653
 654 static inline unsigned int cpuid_edx(unsigned int op)
 655 {
 656         unsigned int eax, ebx, ecx, edx;
 657
 658         cpuid(op, &eax, &ebx, &ecx, &edx);
 659
 660         return edx;
 661 }
 662
 663 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
 664 static inline void rep_nop(void)
 665 {
 666         asm volatile("rep; nop" ::: "memory");
 667 }
 668
 669 static inline void cpu_relax(void)
 670 {
 671         rep_nop();
 672 }
 673
 674 /* Stop speculative execution and prefetching of modified code. */
 675 static inline void sync_core(void)
 676 {
 677         int tmp;
 678
 679 #ifdef CONFIG_M486
 680         /*
 681          * Do a CPUID if available, otherwise do a jump.  The jump
 682          * can conveniently enough be the jump around CPUID.
 683          */
 684         asm volatile("cmpl %2,%1\n\t"
 685                      "jl 1f\n\t"
 686                      "cpuid\n"
 687                      "1:"
 688                      : "=a" (tmp)
 689                      : "rm" (boot_cpu_data.cpuid_level), "ri" (0), "0" (1)
 690                      : "ebx", "ecx", "edx", "memory");
 691 #else
 692         /*
 693          * CPUID is a barrier to speculative execution.
 694          * Prefetched instructions are automatically
 695          * invalidated when modified.
 696          */
 697         asm volatile("cpuid"
 698                      : "=a" (tmp)
 699                      : "0" (1)
 700                      : "ebx", "ecx", "edx", "memory");
 701 #endif
 702 }
 703
 704 static inline void __monitor(const void *eax, unsigned long ecx,
 705                              unsigned long edx)
 706 {
 707         /* "monitor %eax, %ecx, %edx;" */
 708         asm volatile(".byte 0x0f, 0x01, 0xc8;"
 709                      :: "a" (eax), "c" (ecx), "d"(edx));
 710 }
 711
 712 static inline void __mwait(unsigned long eax, unsigned long ecx)
 713 {
 714         /* "mwait %eax, %ecx;" */
 715         asm volatile(".byte 0x0f, 0x01, 0xc9;"
 716                      :: "a" (eax), "c" (ecx));
 717 }
 718
 719 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
 720 {
 721         trace_hardirqs_on();
 722         /* "mwait %eax, %ecx;" */
 723         asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
 724                      :: "a" (eax), "c" (ecx));
 725 }
 726
 727 extern void select_idle_routine(const struct cpuinfo_x86 *c);
 728 extern void init_amd_e400_c1e_mask(void);
 729
 730 extern unsigned long            boot_option_idle_override;
 731 extern bool                     amd_e400_c1e_detected;
 732
 733 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
 734                          IDLE_POLL};
 735
 736 extern void enable_sep_cpu(void);
 737 extern int sysenter_setup(void);
 738
 739 extern void early_trap_init(void);
 740 void early_trap_pf_init(void);
 741
 742 /* Defined in head.S */
 743 extern struct desc_ptr          early_gdt_descr;
 744
 745 extern void cpu_set_gdt(int);
 746 extern void switch_to_new_gdt(int);
 747 extern void load_percpu_segment(int);
 748 extern void cpu_init(void);
 749
 750 static inline unsigned long get_debugctlmsr(void)
 751 {
 752         unsigned long debugctlmsr = 0;
 753
 754 #ifndef CONFIG_X86_DEBUGCTLMSR
 755         if (boot_cpu_data.x86 < 6)
 756                 return 0;
 757 #endif
 758         rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
 759
 760         return debugctlmsr;
 761 }
 762
 763 static inline void update_debugctlmsr(unsigned long debugctlmsr)
 764 {
 765 #ifndef CONFIG_X86_DEBUGCTLMSR
 766         if (boot_cpu_data.x86 < 6)
 767                 return;
 768 #endif
 769         wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
 770 }
 771
 772 extern void set_task_blockstep(struct task_struct *task, bool on);
 773
 774 /*
 775  * from system description table in BIOS. Mostly for MCA use, but
 776  * others may find it useful:
 777  */
 778 extern unsigned int             machine_id;
 779 extern unsigned int             machine_submodel_id;
 780 extern unsigned int             BIOS_revision;
 781
 782 /* Boot loader type from the setup header: */
 783 extern int                      bootloader_type;
 784 extern int                      bootloader_version;
 785
 786 extern char                     ignore_fpu_irq;
 787
 788 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
 789 #define ARCH_HAS_PREFETCHW
 790 #define ARCH_HAS_SPINLOCK_PREFETCH
 791
 792 #ifdef CONFIG_X86_32
 793 # define BASE_PREFETCH          ASM_NOP4
 794 # define ARCH_HAS_PREFETCH
 795 #else
 796 # define BASE_PREFETCH          "prefetcht0 (%1)"
 797 #endif
 798
 799 /*
 800  * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
 801  *
 802  * It's not worth to care about 3dnow prefetches for the K6
 803  * because they are microcoded there and very slow.
 804  */
 805 static inline void prefetch(const void *x)
 806 {
 807         alternative_input(BASE_PREFETCH,
 808                           "prefetchnta (%1)",
 809                           X86_FEATURE_XMM,
 810                           "r" (x));
 811 }
 812
 813 /*
 814  * 3dnow prefetch to get an exclusive cache line.
 815  * Useful for spinlocks to avoid one state transition in the
 816  * cache coherency protocol:
 817  */
 818 static inline void prefetchw(const void *x)
 819 {
 820         alternative_input(BASE_PREFETCH,
 821                           "prefetchw (%1)",
 822                           X86_FEATURE_3DNOW,
 823                           "r" (x));
 824 }
 825
 826 static inline void spin_lock_prefetch(const void *x)
 827 {
 828         prefetchw(x);
 829 }
 830
 831 #ifdef CONFIG_X86_32
 832 /*
 833  * User space process size: 3GB (default).
 834  */
 835 #define TASK_SIZE               PAGE_OFFSET
 836 #define TASK_SIZE_MAX           TASK_SIZE
 837 #define STACK_TOP               TASK_SIZE
 838 #define STACK_TOP_MAX           STACK_TOP
 839
 840 #define INIT_THREAD  {                                                    \
 841         .sp0                    = sizeof(init_stack) + (long)&init_stack, \
 842         .vm86_info              = NULL,                                   \
 843         .sysenter_cs            = __KERNEL_CS,                            \
 844         .io_bitmap_ptr          = NULL,                                   \
 845 }
 846
 847 /*
 848  * Note that the .io_bitmap member must be extra-big. This is because
 849  * the CPU will access an additional byte beyond the end of the IO
 850  * permission bitmap. The extra byte must be all 1 bits, and must
 851  * be within the limit.
 852  */
 853 #define INIT_TSS  {                                                       \
 854         .x86_tss = {                                                      \
 855                 .sp0            = sizeof(init_stack) + (long)&init_stack, \
 856                 .ss0            = __KERNEL_DS,                            \
 857                 .ss1            = __KERNEL_CS,                            \
 858                 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,               \
 859          },                                                               \
 860         .io_bitmap              = { [0 ... IO_BITMAP_LONGS] = ~0 },       \
 861 }
 862
 863 extern unsigned long thread_saved_pc(struct task_struct *tsk);
 864
 865 #define THREAD_SIZE_LONGS      (THREAD_SIZE/sizeof(unsigned long))
 866 #define KSTK_TOP(info)                                                 \
 867 ({                                                                     \
 868        unsigned long *__ptr = (unsigned long *)(info);                 \
 869        (unsigned long)(&__ptr[THREAD_SIZE_LONGS]);                     \
 870 })
 871
 872 /*
 873  * The below -8 is to reserve 8 bytes on top of the ring0 stack.
 874  * This is necessary to guarantee that the entire "struct pt_regs"
 875  * is accessible even if the CPU haven't stored the SS/ESP registers
 876  * on the stack (interrupt gate does not save these registers
 877  * when switching to the same priv ring).
 878  * Therefore beware: accessing the ss/esp fields of the
 879  * "struct pt_regs" is possible, but they may contain the
 880  * completely wrong values.
 881  */
 882 #define task_pt_regs(task)                                             \
 883 ({                                                                     \
 884        struct pt_regs *__regs__;                                       \
 885        __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
 886        __regs__ - 1;                                                   \
 887 })
 888
 889 #define KSTK_ESP(task)          (task_pt_regs(task)->sp)
 890
 891 #else
 892 /*
 893  * User space process size. 47bits minus one guard page.
 894  */
 895 #define TASK_SIZE_MAX   ((1UL << 47) - PAGE_SIZE)
 896
 897 /* This decides where the kernel will search for a free chunk of vm
 898  * space during mmap's.
 899  */
 900 #define IA32_PAGE_OFFSET        ((current->personality & ADDR_LIMIT_3GB) ? \
 901                                         0xc0000000 : 0xFFFFe000)
 902
 903 #define TASK_SIZE               (test_thread_flag(TIF_ADDR32) ? \
 904                                         IA32_PAGE_OFFSET : TASK_SIZE_MAX)
 905 #define TASK_SIZE_OF(child)     ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \
 906                                         IA32_PAGE_OFFSET : TASK_SIZE_MAX)
 907
 908 #define STACK_TOP               TASK_SIZE
 909 #define STACK_TOP_MAX           TASK_SIZE_MAX
 910
 911 #define INIT_THREAD  { \
 912         .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
 913 }
 914
 915 #define INIT_TSS  { \
 916         .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
 917 }
 918
 919 /*
 920  * Return saved PC of a blocked thread.
 921  * What is this good for? it will be always the scheduler or ret_from_fork.
 922  */
 923 #define thread_saved_pc(t)      (*(unsigned long *)((t)->thread.sp - 8))
 924
 925 #define task_pt_regs(tsk)       ((struct pt_regs *)(tsk)->thread.sp0 - 1)
 926 extern unsigned long KSTK_ESP(struct task_struct *task);
 927
 928 /*
 929  * User space RSP while inside the SYSCALL fast path
 930  */
 931 DECLARE_PER_CPU(unsigned long, old_rsp);
 932
 933 #endif /* CONFIG_X86_64 */
 934
 935 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
 936                                                unsigned long new_sp);
 937
 938 /*
 939  * This decides where the kernel will search for a free chunk of vm
 940  * space during mmap's.
 941  */
 942 #define TASK_UNMAPPED_BASE      (PAGE_ALIGN(TASK_SIZE / 3))
 943
 944 #define KSTK_EIP(task)          (task_pt_regs(task)->ip)
 945
 946 /* Get/set a process' ability to use the timestamp counter instruction */
 947 #define GET_TSC_CTL(adr)        get_tsc_mode((adr))
 948 #define SET_TSC_CTL(val)        set_tsc_mode((val))
 949
 950 extern int get_tsc_mode(unsigned long adr);
 951 extern int set_tsc_mode(unsigned int val);
 952
 953 extern u16 amd_get_nb_id(int cpu);
 954
 955 static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves)
 956 {
 957         uint32_t base, eax, signature[3];
 958
 959         for (base = 0x40000000; base < 0x40010000; base += 0x100) {
 960                 cpuid(base, &eax, &signature[0], &signature[1], &signature[2]);
 961
 962                 if (!memcmp(sig, signature, 12) &&
 963                     (leaves == 0 || ((eax - base) >= leaves)))
 964                         return base;
 965         }
 966
 967         return 0;
 968 }
 969
 970 extern unsigned long arch_align_stack(unsigned long sp);
 971 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
 972
 973 void default_idle(void);
 974 #ifdef  CONFIG_XEN
 975 bool xen_set_default_idle(void);
 976 #else
 977 #define xen_set_default_idle 0
 978 #endif
 979
 980 void stop_this_cpu(void *dummy);
 981 void df_debug(struct pt_regs *regs, long error_code);
 982 #endif /* _ASM_X86_PROCESSOR_H */