arch/x86/include/asm/processor.h

   1 #ifndef _ASM_X86_PROCESSOR_H
   2 #define _ASM_X86_PROCESSOR_H
   3
   4 #include <asm/processor-flags.h>
   5
   6 /* Forward declaration, a strange C thing */
   7 struct task_struct;
   8 struct mm_struct;
   9
  10 #include <asm/vm86.h>
  11 #include <asm/math_emu.h>
  12 #include <asm/segment.h>
  13 #include <asm/types.h>
  14 #include <asm/sigcontext.h>
  15 #include <asm/current.h>
  16 #include <asm/cpufeature.h>
  17 #include <asm/system.h>
  18 #include <asm/page.h>
  19 #include <asm/percpu.h>
  20 #include <asm/msr.h>
  21 #include <asm/desc_defs.h>
  22 #include <asm/nops.h>
  23 #include <asm/ds.h>
  24
  25 #include <linux/personality.h>
  26 #include <linux/cpumask.h>
  27 #include <linux/cache.h>
  28 #include <linux/threads.h>
  29 #include <linux/init.h>
  30
  31 /*
  32  * Default implementation of macro that returns current
  33  * instruction pointer ("program counter").
  34  */
  35 static inline void *current_text_addr(void)
  36 {
  37         void *pc;
  38
  39         asm volatile("mov $1f, %0; 1:":"=r" (pc));
  40
  41         return pc;
  42 }
  43
  44 #ifdef CONFIG_X86_VSMP
  45 # define ARCH_MIN_TASKALIGN             (1 << INTERNODE_CACHE_SHIFT)
  46 # define ARCH_MIN_MMSTRUCT_ALIGN        (1 << INTERNODE_CACHE_SHIFT)
  47 #else
  48 # define ARCH_MIN_TASKALIGN             16
  49 # define ARCH_MIN_MMSTRUCT_ALIGN        0
  50 #endif
  51
  52 /*
  53  *  CPU type and hardware bug flags. Kept separately for each CPU.
  54  *  Members of this structure are referenced in head.S, so think twice
  55  *  before touching them. [mj]
  56  */
  57
  58 struct cpuinfo_x86 {
  59         __u8                    x86;            /* CPU family */
  60         __u8                    x86_vendor;     /* CPU vendor */
  61         __u8                    x86_model;
  62         __u8                    x86_mask;
  63 #ifdef CONFIG_X86_32
  64         char                    wp_works_ok;    /* It doesn't on 386's */
  65
  66         /* Problems on some 486Dx4's and old 386's: */
  67         char                    hlt_works_ok;
  68         char                    hard_math;
  69         char                    rfu;
  70         char                    fdiv_bug;
  71         char                    f00f_bug;
  72         char                    coma_bug;
  73         char                    pad0;
  74 #else
  75         /* Number of 4K pages in DTLB/ITLB combined(in pages): */
  76         int                      x86_tlbsize;
  77         __u8                    x86_virt_bits;
  78         __u8                    x86_phys_bits;
  79 #endif
  80         /* CPUID returned core id bits: */
  81         __u8                    x86_coreid_bits;
  82         /* Max extended CPUID function supported: */
  83         __u32                   extended_cpuid_level;
  84         /* Maximum supported CPUID level, -1=no CPUID: */
  85         int                     cpuid_level;
  86         __u32                   x86_capability[NCAPINTS];
  87         char                    x86_vendor_id[16];
  88         char                    x86_model_id[64];
  89         /* in KB - valid for CPUS which support this call: */
  90         int                     x86_cache_size;
  91         int                     x86_cache_alignment;    /* In bytes */
  92         int                     x86_power;
  93         unsigned long           loops_per_jiffy;
  94 #ifdef CONFIG_SMP
  95         /* cpus sharing the last level cache: */
  96         cpumask_t               llc_shared_map;
  97 #endif
  98         /* cpuid returned max cores value: */
  99         u16                      x86_max_cores;
 100         u16                     apicid;
 101         u16                     initial_apicid;
 102         u16                     x86_clflush_size;
 103 #ifdef CONFIG_SMP
 104         /* number of cores as seen by the OS: */
 105         u16                     booted_cores;
 106         /* Physical processor id: */
 107         u16                     phys_proc_id;
 108         /* Core id: */
 109         u16                     cpu_core_id;
 110         /* Index into per_cpu list: */
 111         u16                     cpu_index;
 112 #endif
 113         unsigned int            x86_hyper_vendor;
 114 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
 115
 116 #define X86_VENDOR_INTEL        0
 117 #define X86_VENDOR_CYRIX        1
 118 #define X86_VENDOR_AMD          2
 119 #define X86_VENDOR_UMC          3
 120 #define X86_VENDOR_CENTAUR      5
 121 #define X86_VENDOR_TRANSMETA    7
 122 #define X86_VENDOR_NSC          8
 123 #define X86_VENDOR_NUM          9
 124
 125 #define X86_VENDOR_UNKNOWN      0xff
 126
 127 #define X86_HYPER_VENDOR_NONE  0
 128 #define X86_HYPER_VENDOR_VMWARE 1
 129
 130 /*
 131  * capabilities of CPUs
 132  */
 133 extern struct cpuinfo_x86       boot_cpu_data;
 134 extern struct cpuinfo_x86       new_cpu_data;
 135
 136 extern struct tss_struct        doublefault_tss;
 137 extern __u32                    cleared_cpu_caps[NCAPINTS];
 138
 139 #ifdef CONFIG_SMP
 140 DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info);
 141 #define cpu_data(cpu)           per_cpu(cpu_info, cpu)
 142 #define current_cpu_data        __get_cpu_var(cpu_info)
 143 #else
 144 #define cpu_data(cpu)           boot_cpu_data
 145 #define current_cpu_data        boot_cpu_data
 146 #endif
 147
 148 extern const struct seq_operations cpuinfo_op;
 149
 150 static inline int hlt_works(int cpu)
 151 {
 152 #ifdef CONFIG_X86_32
 153         return cpu_data(cpu).hlt_works_ok;
 154 #else
 155         return 1;
 156 #endif
 157 }
 158
 159 #define cache_line_size()       (boot_cpu_data.x86_cache_alignment)
 160
 161 extern void cpu_detect(struct cpuinfo_x86 *c);
 162
 163 extern struct pt_regs *idle_regs(struct pt_regs *);
 164
 165 extern void early_cpu_init(void);
 166 extern void identify_boot_cpu(void);
 167 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
 168 extern void print_cpu_info(struct cpuinfo_x86 *);
 169 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
 170 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
 171 extern unsigned short num_cache_leaves;
 172
 173 extern void detect_extended_topology(struct cpuinfo_x86 *c);
 174 extern void detect_ht(struct cpuinfo_x86 *c);
 175
 176 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
 177                                 unsigned int *ecx, unsigned int *edx)
 178 {
 179         /* ecx is often an input as well as an output. */
 180         asm("cpuid"
 181             : "=a" (*eax),
 182               "=b" (*ebx),
 183               "=c" (*ecx),
 184               "=d" (*edx)
 185             : "0" (*eax), "2" (*ecx));
 186 }
 187
 188 static inline void load_cr3(pgd_t *pgdir)
 189 {
 190         write_cr3(__pa(pgdir));
 191 }
 192
 193 #ifdef CONFIG_X86_32
 194 /* This is the TSS defined by the hardware. */
 195 struct x86_hw_tss {
 196         unsigned short          back_link, __blh;
 197         unsigned long           sp0;
 198         unsigned short          ss0, __ss0h;
 199         unsigned long           sp1;
 200         /* ss1 caches MSR_IA32_SYSENTER_CS: */
 201         unsigned short          ss1, __ss1h;
 202         unsigned long           sp2;
 203         unsigned short          ss2, __ss2h;
 204         unsigned long           __cr3;
 205         unsigned long           ip;
 206         unsigned long           flags;
 207         unsigned long           ax;
 208         unsigned long           cx;
 209         unsigned long           dx;
 210         unsigned long           bx;
 211         unsigned long           sp;
 212         unsigned long           bp;
 213         unsigned long           si;
 214         unsigned long           di;
 215         unsigned short          es, __esh;
 216         unsigned short          cs, __csh;
 217         unsigned short          ss, __ssh;
 218         unsigned short          ds, __dsh;
 219         unsigned short          fs, __fsh;
 220         unsigned short          gs, __gsh;
 221         unsigned short          ldt, __ldth;
 222         unsigned short          trace;
 223         unsigned short          io_bitmap_base;
 224
 225 } __attribute__((packed));
 226 #else
 227 struct x86_hw_tss {
 228         u32                     reserved1;
 229         u64                     sp0;
 230         u64                     sp1;
 231         u64                     sp2;
 232         u64                     reserved2;
 233         u64                     ist[7];
 234         u32                     reserved3;
 235         u32                     reserved4;
 236         u16                     reserved5;
 237         u16                     io_bitmap_base;
 238
 239 } __attribute__((packed)) ____cacheline_aligned;
 240 #endif
 241
 242 /*
 243  * IO-bitmap sizes:
 244  */
 245 #define IO_BITMAP_BITS                  65536
 246 #define IO_BITMAP_BYTES                 (IO_BITMAP_BITS/8)
 247 #define IO_BITMAP_LONGS                 (IO_BITMAP_BYTES/sizeof(long))
 248 #define IO_BITMAP_OFFSET                offsetof(struct tss_struct, io_bitmap)
 249 #define INVALID_IO_BITMAP_OFFSET        0x8000
 250 #define INVALID_IO_BITMAP_OFFSET_LAZY   0x9000
 251
 252 struct tss_struct {
 253         /*
 254          * The hardware state:
 255          */
 256         struct x86_hw_tss       x86_tss;
 257
 258         /*
 259          * The extra 1 is there because the CPU will access an
 260          * additional byte beyond the end of the IO permission
 261          * bitmap. The extra byte must be all 1 bits, and must
 262          * be within the limit.
 263          */
 264         unsigned long           io_bitmap[IO_BITMAP_LONGS + 1];
 265         /*
 266          * Cache the current maximum and the last task that used the bitmap:
 267          */
 268         unsigned long           io_bitmap_max;
 269         struct thread_struct    *io_bitmap_owner;
 270
 271         /*
 272          * .. and then another 0x100 bytes for the emergency kernel stack:
 273          */
 274         unsigned long           stack[64];
 275
 276 } ____cacheline_aligned;
 277
 278 DECLARE_PER_CPU(struct tss_struct, init_tss);
 279
 280 /*
 281  * Save the original ist values for checking stack pointers during debugging
 282  */
 283 struct orig_ist {
 284         unsigned long           ist[7];
 285 };
 286
 287 #define MXCSR_DEFAULT           0x1f80
 288
 289 struct i387_fsave_struct {
 290         u32                     cwd;    /* FPU Control Word             */
 291         u32                     swd;    /* FPU Status Word              */
 292         u32                     twd;    /* FPU Tag Word                 */
 293         u32                     fip;    /* FPU IP Offset                */
 294         u32                     fcs;    /* FPU IP Selector              */
 295         u32                     foo;    /* FPU Operand Pointer Offset   */
 296         u32                     fos;    /* FPU Operand Pointer Selector */
 297
 298         /* 8*10 bytes for each FP-reg = 80 bytes:                       */
 299         u32                     st_space[20];
 300
 301         /* Software status information [not touched by FSAVE ]:         */
 302         u32                     status;
 303 };
 304
 305 struct i387_fxsave_struct {
 306         u16                     cwd; /* Control Word                    */
 307         u16                     swd; /* Status Word                     */
 308         u16                     twd; /* Tag Word                        */
 309         u16                     fop; /* Last Instruction Opcode         */
 310         union {
 311                 struct {
 312                         u64     rip; /* Instruction Pointer             */
 313                         u64     rdp; /* Data Pointer                    */
 314                 };
 315                 struct {
 316                         u32     fip; /* FPU IP Offset                   */
 317                         u32     fcs; /* FPU IP Selector                 */
 318                         u32     foo; /* FPU Operand Offset              */
 319                         u32     fos; /* FPU Operand Selector            */
 320                 };
 321         };
 322         u32                     mxcsr;          /* MXCSR Register State */
 323         u32                     mxcsr_mask;     /* MXCSR Mask           */
 324
 325         /* 8*16 bytes for each FP-reg = 128 bytes:                      */
 326         u32                     st_space[32];
 327
 328         /* 16*16 bytes for each XMM-reg = 256 bytes:                    */
 329         u32                     xmm_space[64];
 330
 331         u32                     padding[12];
 332
 333         union {
 334                 u32             padding1[12];
 335                 u32             sw_reserved[12];
 336         };
 337
 338 } __attribute__((aligned(16)));
 339
 340 struct i387_soft_struct {
 341         u32                     cwd;
 342         u32                     swd;
 343         u32                     twd;
 344         u32                     fip;
 345         u32                     fcs;
 346         u32                     foo;
 347         u32                     fos;
 348         /* 8*10 bytes for each FP-reg = 80 bytes: */
 349         u32                     st_space[20];
 350         u8                      ftop;
 351         u8                      changed;
 352         u8                      lookahead;
 353         u8                      no_update;
 354         u8                      rm;
 355         u8                      alimit;
 356         struct math_emu_info    *info;
 357         u32                     entry_eip;
 358 };
 359
 360 struct xsave_hdr_struct {
 361         u64 xstate_bv;
 362         u64 reserved1[2];
 363         u64 reserved2[5];
 364 } __attribute__((packed));
 365
 366 struct xsave_struct {
 367         struct i387_fxsave_struct i387;
 368         struct xsave_hdr_struct xsave_hdr;
 369         /* new processor state extensions will go here */
 370 } __attribute__ ((packed, aligned (64)));
 371
 372 union thread_xstate {
 373         struct i387_fsave_struct        fsave;
 374         struct i387_fxsave_struct       fxsave;
 375         struct i387_soft_struct         soft;
 376         struct xsave_struct             xsave;
 377 };
 378
 379 #ifdef CONFIG_X86_64
 380 DECLARE_PER_CPU(struct orig_ist, orig_ist);
 381
 382 union irq_stack_union {
 383         char irq_stack[IRQ_STACK_SIZE];
 384         /*
 385          * GCC hardcodes the stack canary as %gs:40.  Since the
 386          * irq_stack is the object at %gs:0, we reserve the bottom
 387          * 48 bytes of the irq stack for the canary.
 388          */
 389         struct {
 390                 char gs_base[40];
 391                 unsigned long stack_canary;
 392         };
 393 };
 394
 395 DECLARE_PER_CPU(union irq_stack_union, irq_stack_union);
 396 DECLARE_INIT_PER_CPU(irq_stack_union);
 397
 398 DECLARE_PER_CPU(char *, irq_stack_ptr);
 399 #else   /* X86_64 */
 400 #ifdef CONFIG_CC_STACKPROTECTOR
 401 DECLARE_PER_CPU(unsigned long, stack_canary);
 402 #endif
 403 #endif  /* X86_64 */
 404
 405 extern void print_cpu_info(struct cpuinfo_x86 *);
 406 extern unsigned int xstate_size;
 407 extern void free_thread_xstate(struct task_struct *);
 408 extern struct kmem_cache *task_xstate_cachep;
 409 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
 410 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
 411 extern unsigned short num_cache_leaves;
 412
 413 struct thread_struct {
 414         /* Cached TLS descriptors: */
 415         struct desc_struct      tls_array[GDT_ENTRY_TLS_ENTRIES];
 416         unsigned long           sp0;
 417         unsigned long           sp;
 418 #ifdef CONFIG_X86_32
 419         unsigned long           sysenter_cs;
 420 #else
 421         unsigned long           usersp; /* Copy from PDA */
 422         unsigned short          es;
 423         unsigned short          ds;
 424         unsigned short          fsindex;
 425         unsigned short          gsindex;
 426 #endif
 427         unsigned long           ip;
 428         unsigned long           fs;
 429         unsigned long           gs;
 430         /* Hardware debugging registers: */
 431         unsigned long           debugreg0;
 432         unsigned long           debugreg1;
 433         unsigned long           debugreg2;
 434         unsigned long           debugreg3;
 435         unsigned long           debugreg6;
 436         unsigned long           debugreg7;
 437         /* Fault info: */
 438         unsigned long           cr2;
 439         unsigned long           trap_no;
 440         unsigned long           error_code;
 441         /* floating point and extended processor state */
 442         union thread_xstate     *xstate;
 443 #ifdef CONFIG_X86_32
 444         /* Virtual 86 mode info */
 445         struct vm86_struct __user *vm86_info;
 446         unsigned long           screen_bitmap;
 447         unsigned long           v86flags;
 448         unsigned long           v86mask;
 449         unsigned long           saved_sp0;
 450         unsigned int            saved_fs;
 451         unsigned int            saved_gs;
 452 #endif
 453         /* IO permissions: */
 454         unsigned long           *io_bitmap_ptr;
 455         unsigned long           iopl;
 456         /* Max allowed port in the bitmap, in bytes: */
 457         unsigned                io_bitmap_max;
 458 /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set.  */
 459         unsigned long   debugctlmsr;
 460 #ifdef CONFIG_X86_DS
 461 /* Debug Store context; see include/asm-x86/ds.h; goes into MSR_IA32_DS_AREA */
 462         struct ds_context       *ds_ctx;
 463 #endif /* CONFIG_X86_DS */
 464 #ifdef CONFIG_X86_PTRACE_BTS
 465 /* the signal to send on a bts buffer overflow */
 466         unsigned int    bts_ovfl_signal;
 467 #endif /* CONFIG_X86_PTRACE_BTS */
 468 };
 469
 470 static inline unsigned long native_get_debugreg(int regno)
 471 {
 472         unsigned long val = 0;  /* Damn you, gcc! */
 473
 474         switch (regno) {
 475         case 0:
 476                 asm("mov %%db0, %0" :"=r" (val));
 477                 break;
 478         case 1:
 479                 asm("mov %%db1, %0" :"=r" (val));
 480                 break;
 481         case 2:
 482                 asm("mov %%db2, %0" :"=r" (val));
 483                 break;
 484         case 3:
 485                 asm("mov %%db3, %0" :"=r" (val));
 486                 break;
 487         case 6:
 488                 asm("mov %%db6, %0" :"=r" (val));
 489                 break;
 490         case 7:
 491                 asm("mov %%db7, %0" :"=r" (val));
 492                 break;
 493         default:
 494                 BUG();
 495         }
 496         return val;
 497 }
 498
 499 static inline void native_set_debugreg(int regno, unsigned long value)
 500 {
 501         switch (regno) {
 502         case 0:
 503                 asm("mov %0, %%db0"     ::"r" (value));
 504                 break;
 505         case 1:
 506                 asm("mov %0, %%db1"     ::"r" (value));
 507                 break;
 508         case 2:
 509                 asm("mov %0, %%db2"     ::"r" (value));
 510                 break;
 511         case 3:
 512                 asm("mov %0, %%db3"     ::"r" (value));
 513                 break;
 514         case 6:
 515                 asm("mov %0, %%db6"     ::"r" (value));
 516                 break;
 517         case 7:
 518                 asm("mov %0, %%db7"     ::"r" (value));
 519                 break;
 520         default:
 521                 BUG();
 522         }
 523 }
 524
 525 /*
 526  * Set IOPL bits in EFLAGS from given mask
 527  */
 528 static inline void native_set_iopl_mask(unsigned mask)
 529 {
 530 #ifdef CONFIG_X86_32
 531         unsigned int reg;
 532
 533         asm volatile ("pushfl;"
 534                       "popl %0;"
 535                       "andl %1, %0;"
 536                       "orl %2, %0;"
 537                       "pushl %0;"
 538                       "popfl"
 539                       : "=&r" (reg)
 540                       : "i" (~X86_EFLAGS_IOPL), "r" (mask));
 541 #endif
 542 }
 543
 544 static inline void
 545 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
 546 {
 547         tss->x86_tss.sp0 = thread->sp0;
 548 #ifdef CONFIG_X86_32
 549         /* Only happens when SEP is enabled, no need to test "SEP"arately: */
 550         if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
 551                 tss->x86_tss.ss1 = thread->sysenter_cs;
 552                 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
 553         }
 554 #endif
 555 }
 556
 557 static inline void native_swapgs(void)
 558 {
 559 #ifdef CONFIG_X86_64
 560         asm volatile("swapgs" ::: "memory");
 561 #endif
 562 }
 563
 564 #ifdef CONFIG_PARAVIRT
 565 #include <asm/paravirt.h>
 566 #else
 567 #define __cpuid                 native_cpuid
 568 #define paravirt_enabled()      0
 569
 570 /*
 571  * These special macros can be used to get or set a debugging register
 572  */
 573 #define get_debugreg(var, register)                             \
 574         (var) = native_get_debugreg(register)
 575 #define set_debugreg(value, register)                           \
 576         native_set_debugreg(register, value)
 577
 578 static inline void load_sp0(struct tss_struct *tss,
 579                             struct thread_struct *thread)
 580 {
 581         native_load_sp0(tss, thread);
 582 }
 583
 584 #define set_iopl_mask native_set_iopl_mask
 585 #endif /* CONFIG_PARAVIRT */
 586
 587 /*
 588  * Save the cr4 feature set we're using (ie
 589  * Pentium 4MB enable and PPro Global page
 590  * enable), so that any CPU's that boot up
 591  * after us can get the correct flags.
 592  */
 593 extern unsigned long            mmu_cr4_features;
 594
 595 static inline void set_in_cr4(unsigned long mask)
 596 {
 597         unsigned cr4;
 598
 599         mmu_cr4_features |= mask;
 600         cr4 = read_cr4();
 601         cr4 |= mask;
 602         write_cr4(cr4);
 603 }
 604
 605 static inline void clear_in_cr4(unsigned long mask)
 606 {
 607         unsigned cr4;
 608
 609         mmu_cr4_features &= ~mask;
 610         cr4 = read_cr4();
 611         cr4 &= ~mask;
 612         write_cr4(cr4);
 613 }
 614
 615 typedef struct {
 616         unsigned long           seg;
 617 } mm_segment_t;
 618
 619
 620 /*
 621  * create a kernel thread without removing it from tasklists
 622  */
 623 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
 624
 625 /* Free all resources held by a thread. */
 626 extern void release_thread(struct task_struct *);
 627
 628 /* Prepare to copy thread state - unlazy all lazy state */
 629 extern void prepare_to_copy(struct task_struct *tsk);
 630
 631 unsigned long get_wchan(struct task_struct *p);
 632
 633 /*
 634  * Generic CPUID function
 635  * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
 636  * resulting in stale register contents being returned.
 637  */
 638 static inline void cpuid(unsigned int op,
 639                          unsigned int *eax, unsigned int *ebx,
 640                          unsigned int *ecx, unsigned int *edx)
 641 {
 642         *eax = op;
 643         *ecx = 0;
 644         __cpuid(eax, ebx, ecx, edx);
 645 }
 646
 647 /* Some CPUID calls want 'count' to be placed in ecx */
 648 static inline void cpuid_count(unsigned int op, int count,
 649                                unsigned int *eax, unsigned int *ebx,
 650                                unsigned int *ecx, unsigned int *edx)
 651 {
 652         *eax = op;
 653         *ecx = count;
 654         __cpuid(eax, ebx, ecx, edx);
 655 }
 656
 657 /*
 658  * CPUID functions returning a single datum
 659  */
 660 static inline unsigned int cpuid_eax(unsigned int op)
 661 {
 662         unsigned int eax, ebx, ecx, edx;
 663
 664         cpuid(op, &eax, &ebx, &ecx, &edx);
 665
 666         return eax;
 667 }
 668
 669 static inline unsigned int cpuid_ebx(unsigned int op)
 670 {
 671         unsigned int eax, ebx, ecx, edx;
 672
 673         cpuid(op, &eax, &ebx, &ecx, &edx);
 674
 675         return ebx;
 676 }
 677
 678 static inline unsigned int cpuid_ecx(unsigned int op)
 679 {
 680         unsigned int eax, ebx, ecx, edx;
 681
 682         cpuid(op, &eax, &ebx, &ecx, &edx);
 683
 684         return ecx;
 685 }
 686
 687 static inline unsigned int cpuid_edx(unsigned int op)
 688 {
 689         unsigned int eax, ebx, ecx, edx;
 690
 691         cpuid(op, &eax, &ebx, &ecx, &edx);
 692
 693         return edx;
 694 }
 695
 696 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
 697 static inline void rep_nop(void)
 698 {
 699         asm volatile("rep; nop" ::: "memory");
 700 }
 701
 702 static inline void cpu_relax(void)
 703 {
 704         rep_nop();
 705 }
 706
 707 /* Stop speculative execution: */
 708 static inline void sync_core(void)
 709 {
 710         int tmp;
 711
 712         asm volatile("cpuid" : "=a" (tmp) : "0" (1)
 713                      : "ebx", "ecx", "edx", "memory");
 714 }
 715
 716 static inline void __monitor(const void *eax, unsigned long ecx,
 717                              unsigned long edx)
 718 {
 719         /* "monitor %eax, %ecx, %edx;" */
 720         asm volatile(".byte 0x0f, 0x01, 0xc8;"
 721                      :: "a" (eax), "c" (ecx), "d"(edx));
 722 }
 723
 724 static inline void __mwait(unsigned long eax, unsigned long ecx)
 725 {
 726         /* "mwait %eax, %ecx;" */
 727         asm volatile(".byte 0x0f, 0x01, 0xc9;"
 728                      :: "a" (eax), "c" (ecx));
 729 }
 730
 731 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
 732 {
 733         trace_hardirqs_on();
 734         /* "mwait %eax, %ecx;" */
 735         asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
 736                      :: "a" (eax), "c" (ecx));
 737 }
 738
 739 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
 740
 741 extern void select_idle_routine(const struct cpuinfo_x86 *c);
 742
 743 extern unsigned long            boot_option_idle_override;
 744 extern unsigned long            idle_halt;
 745 extern unsigned long            idle_nomwait;
 746
 747 /*
 748  * on systems with caches, caches must be flashed as the absolute
 749  * last instruction before going into a suspended halt.  Otherwise,
 750  * dirty data can linger in the cache and become stale on resume,
 751  * leading to strange errors.
 752  *
 753  * perform a variety of operations to guarantee that the compiler
 754  * will not reorder instructions.  wbinvd itself is serializing
 755  * so the processor will not reorder.
 756  *
 757  * Systems without cache can just go into halt.
 758  */
 759 static inline void wbinvd_halt(void)
 760 {
 761         mb();
 762         /* check for clflush to determine if wbinvd is legal */
 763         if (cpu_has_clflush)
 764                 asm volatile("cli; wbinvd; 1: hlt; jmp 1b" : : : "memory");
 765         else
 766                 while (1)
 767                         halt();
 768 }
 769
 770 extern void enable_sep_cpu(void);
 771 extern int sysenter_setup(void);
 772
 773 /* Defined in head.S */
 774 extern struct desc_ptr          early_gdt_descr;
 775
 776 extern void cpu_set_gdt(int);
 777 extern void switch_to_new_gdt(int);
 778 extern void load_percpu_segment(int);
 779 extern void cpu_init(void);
 780
 781 static inline unsigned long get_debugctlmsr(void)
 782 {
 783     unsigned long debugctlmsr = 0;
 784
 785 #ifndef CONFIG_X86_DEBUGCTLMSR
 786         if (boot_cpu_data.x86 < 6)
 787                 return 0;
 788 #endif
 789         rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
 790
 791     return debugctlmsr;
 792 }
 793
 794 static inline void update_debugctlmsr(unsigned long debugctlmsr)
 795 {
 796 #ifndef CONFIG_X86_DEBUGCTLMSR
 797         if (boot_cpu_data.x86 < 6)
 798                 return;
 799 #endif
 800         wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
 801 }
 802
 803 /*
 804  * from system description table in BIOS. Mostly for MCA use, but
 805  * others may find it useful:
 806  */
 807 extern unsigned int             machine_id;
 808 extern unsigned int             machine_submodel_id;
 809 extern unsigned int             BIOS_revision;
 810
 811 /* Boot loader type from the setup header: */
 812 extern int                      bootloader_type;
 813
 814 extern char                     ignore_fpu_irq;
 815
 816 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
 817 #define ARCH_HAS_PREFETCHW
 818 #define ARCH_HAS_SPINLOCK_PREFETCH
 819
 820 #ifdef CONFIG_X86_32
 821 # define BASE_PREFETCH          ASM_NOP4
 822 # define ARCH_HAS_PREFETCH
 823 #else
 824 # define BASE_PREFETCH          "prefetcht0 (%1)"
 825 #endif
 826
 827 /*
 828  * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
 829  *
 830  * It's not worth to care about 3dnow prefetches for the K6
 831  * because they are microcoded there and very slow.
 832  */
 833 static inline void prefetch(const void *x)
 834 {
 835         alternative_input(BASE_PREFETCH,
 836                           "prefetchnta (%1)",
 837                           X86_FEATURE_XMM,
 838                           "r" (x));
 839 }
 840
 841 /*
 842  * 3dnow prefetch to get an exclusive cache line.
 843  * Useful for spinlocks to avoid one state transition in the
 844  * cache coherency protocol:
 845  */
 846 static inline void prefetchw(const void *x)
 847 {
 848         alternative_input(BASE_PREFETCH,
 849                           "prefetchw (%1)",
 850                           X86_FEATURE_3DNOW,
 851                           "r" (x));
 852 }
 853
 854 static inline void spin_lock_prefetch(const void *x)
 855 {
 856         prefetchw(x);
 857 }
 858
 859 #ifdef CONFIG_X86_32
 860 /*
 861  * User space process size: 3GB (default).
 862  */
 863 #define TASK_SIZE               PAGE_OFFSET
 864 #define STACK_TOP               TASK_SIZE
 865 #define STACK_TOP_MAX           STACK_TOP
 866
 867 #define INIT_THREAD  {                                                    \
 868         .sp0                    = sizeof(init_stack) + (long)&init_stack, \
 869         .vm86_info              = NULL,                                   \
 870         .sysenter_cs            = __KERNEL_CS,                            \
 871         .io_bitmap_ptr          = NULL,                                   \
 872         .fs                     = __KERNEL_PERCPU,                        \
 873 }
 874
 875 /*
 876  * Note that the .io_bitmap member must be extra-big. This is because
 877  * the CPU will access an additional byte beyond the end of the IO
 878  * permission bitmap. The extra byte must be all 1 bits, and must
 879  * be within the limit.
 880  */
 881 #define INIT_TSS  {                                                       \
 882         .x86_tss = {                                                      \
 883                 .sp0            = sizeof(init_stack) + (long)&init_stack, \
 884                 .ss0            = __KERNEL_DS,                            \
 885                 .ss1            = __KERNEL_CS,                            \
 886                 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,               \
 887          },                                                               \
 888         .io_bitmap              = { [0 ... IO_BITMAP_LONGS] = ~0 },       \
 889 }
 890
 891 extern unsigned long thread_saved_pc(struct task_struct *tsk);
 892
 893 #define THREAD_SIZE_LONGS      (THREAD_SIZE/sizeof(unsigned long))
 894 #define KSTK_TOP(info)                                                 \
 895 ({                                                                     \
 896        unsigned long *__ptr = (unsigned long *)(info);                 \
 897        (unsigned long)(&__ptr[THREAD_SIZE_LONGS]);                     \
 898 })
 899
 900 /*
 901  * The below -8 is to reserve 8 bytes on top of the ring0 stack.
 902  * This is necessary to guarantee that the entire "struct pt_regs"
 903  * is accessable even if the CPU haven't stored the SS/ESP registers
 904  * on the stack (interrupt gate does not save these registers
 905  * when switching to the same priv ring).
 906  * Therefore beware: accessing the ss/esp fields of the
 907  * "struct pt_regs" is possible, but they may contain the
 908  * completely wrong values.
 909  */
 910 #define task_pt_regs(task)                                             \
 911 ({                                                                     \
 912        struct pt_regs *__regs__;                                       \
 913        __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
 914        __regs__ - 1;                                                   \
 915 })
 916
 917 #define KSTK_ESP(task)          (task_pt_regs(task)->sp)
 918
 919 #else
 920 /*
 921  * User space process size. 47bits minus one guard page.
 922  */
 923 #define TASK_SIZE64     ((1UL << 47) - PAGE_SIZE)
 924
 925 /* This decides where the kernel will search for a free chunk of vm
 926  * space during mmap's.
 927  */
 928 #define IA32_PAGE_OFFSET        ((current->personality & ADDR_LIMIT_3GB) ? \
 929                                         0xc0000000 : 0xFFFFe000)
 930
 931 #define TASK_SIZE               (test_thread_flag(TIF_IA32) ? \
 932                                         IA32_PAGE_OFFSET : TASK_SIZE64)
 933 #define TASK_SIZE_OF(child)     ((test_tsk_thread_flag(child, TIF_IA32)) ? \
 934                                         IA32_PAGE_OFFSET : TASK_SIZE64)
 935
 936 #define STACK_TOP               TASK_SIZE
 937 #define STACK_TOP_MAX           TASK_SIZE64
 938
 939 #define INIT_THREAD  { \
 940         .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
 941 }
 942
 943 #define INIT_TSS  { \
 944         .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
 945 }
 946
 947 /*
 948  * Return saved PC of a blocked thread.
 949  * What is this good for? it will be always the scheduler or ret_from_fork.
 950  */
 951 #define thread_saved_pc(t)      (*(unsigned long *)((t)->thread.sp - 8))
 952
 953 #define task_pt_regs(tsk)       ((struct pt_regs *)(tsk)->thread.sp0 - 1)
 954 #define KSTK_ESP(tsk)           -1 /* sorry. doesn't work for syscall. */
 955 #endif /* CONFIG_X86_64 */
 956
 957 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
 958                                                unsigned long new_sp);
 959
 960 /*
 961  * This decides where the kernel will search for a free chunk of vm
 962  * space during mmap's.
 963  */
 964 #define TASK_UNMAPPED_BASE      (PAGE_ALIGN(TASK_SIZE / 3))
 965
 966 #define KSTK_EIP(task)          (task_pt_regs(task)->ip)
 967
 968 /* Get/set a process' ability to use the timestamp counter instruction */
 969 #define GET_TSC_CTL(adr)        get_tsc_mode((adr))
 970 #define SET_TSC_CTL(val)        set_tsc_mode((val))
 971
 972 extern int get_tsc_mode(unsigned long adr);
 973 extern int set_tsc_mode(unsigned int val);
 974
 975 #endif /* _ASM_X86_PROCESSOR_H */