1 #ifndef _ASM_X86_PROCESSOR_H
2 #define _ASM_X86_PROCESSOR_H
4 #include <asm/processor-flags.h>
6 /* Forward declaration, a strange C thing */
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
13 #include <asm/types.h>
14 #include <uapi/asm/sigcontext.h>
15 #include <asm/current.h>
16 #include <asm/cpufeatures.h>
18 #include <asm/pgtable_types.h>
19 #include <asm/percpu.h>
21 #include <asm/desc_defs.h>
23 #include <asm/special_insns.h>
24 #include <asm/fpu/types.h>
26 #include <linux/personality.h>
27 #include <linux/cache.h>
28 #include <linux/threads.h>
29 #include <linux/math64.h>
30 #include <linux/err.h>
31 #include <linux/irqflags.h>
34 * We handle most unaligned accesses in hardware. On the other hand
35 * unaligned DMA can be quite expensive on some Nehalem processors.
37 * Based on this we disable the IP header alignment in network drivers.
39 #define NET_IP_ALIGN 0
43 * Default implementation of macro that returns current
44 * instruction pointer ("program counter").
46 static inline void *current_text_addr(void)
50 asm volatile("mov $1f, %0; 1:":"=r" (pc
));
56 * These alignment constraints are for performance in the vSMP case,
57 * but in the task_struct case we must also meet hardware imposed
58 * alignment requirements of the FPU state:
60 #ifdef CONFIG_X86_VSMP
61 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
62 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
64 # define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state)
65 # define ARCH_MIN_MMSTRUCT_ALIGN 0
73 extern u16 __read_mostly tlb_lli_4k
[NR_INFO
];
74 extern u16 __read_mostly tlb_lli_2m
[NR_INFO
];
75 extern u16 __read_mostly tlb_lli_4m
[NR_INFO
];
76 extern u16 __read_mostly tlb_lld_4k
[NR_INFO
];
77 extern u16 __read_mostly tlb_lld_2m
[NR_INFO
];
78 extern u16 __read_mostly tlb_lld_4m
[NR_INFO
];
79 extern u16 __read_mostly tlb_lld_1g
[NR_INFO
];
82 * CPU type and hardware bug flags. Kept separately for each CPU.
83 * Members of this structure are referenced in head_32.S, so think twice
84 * before touching them. [mj]
88 __u8 x86
; /* CPU family */
89 __u8 x86_vendor
; /* CPU vendor */
93 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
98 /* CPUID returned core id bits: */
101 /* Max extended CPUID function supported: */
102 __u32 extended_cpuid_level
;
103 /* Maximum supported CPUID level, -1=no CPUID: */
105 __u32 x86_capability
[NCAPINTS
+ NBUGINTS
];
106 char x86_vendor_id
[16];
107 char x86_model_id
[64];
108 /* in KB - valid for CPUS which support this call: */
110 int x86_cache_alignment
; /* In bytes */
111 /* Cache QoS architectural values: */
112 int x86_cache_max_rmid
; /* max index */
113 int x86_cache_occ_scale
; /* scale to bytes */
115 unsigned long loops_per_jiffy
;
116 /* cpuid returned max cores value: */
120 u16 x86_clflush_size
;
121 /* number of cores as seen by the OS: */
123 /* Physical processor id: */
125 /* Logical processor id: */
129 /* Index into per_cpu list: */
132 } __randomize_layout
;
135 u32 eax
, ebx
, ecx
, edx
;
138 enum cpuid_regs_idx
{
145 #define X86_VENDOR_INTEL 0
146 #define X86_VENDOR_CYRIX 1
147 #define X86_VENDOR_AMD 2
148 #define X86_VENDOR_UMC 3
149 #define X86_VENDOR_CENTAUR 5
150 #define X86_VENDOR_TRANSMETA 7
151 #define X86_VENDOR_NSC 8
152 #define X86_VENDOR_NUM 9
154 #define X86_VENDOR_UNKNOWN 0xff
157 * capabilities of CPUs
159 extern struct cpuinfo_x86 boot_cpu_data
;
160 extern struct cpuinfo_x86 new_cpu_data
;
162 #include <linux/thread_info.h>
164 extern struct tss_struct doublefault_tss
;
165 extern __u32 cpu_caps_cleared
[NCAPINTS
];
166 extern __u32 cpu_caps_set
[NCAPINTS
];
169 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86
, cpu_info
);
170 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
172 #define cpu_info boot_cpu_data
173 #define cpu_data(cpu) boot_cpu_data
176 extern const struct seq_operations cpuinfo_op
;
178 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
180 extern void cpu_detect(struct cpuinfo_x86
*c
);
182 extern void early_cpu_init(void);
183 extern void identify_boot_cpu(void);
184 extern void identify_secondary_cpu(struct cpuinfo_x86
*);
185 extern void print_cpu_info(struct cpuinfo_x86
*);
186 void print_cpu_msr(struct cpuinfo_x86
*);
187 extern void init_scattered_cpuid_features(struct cpuinfo_x86
*c
);
188 extern u32
get_scattered_cpuid_leaf(unsigned int level
,
189 unsigned int sub_leaf
,
190 enum cpuid_regs_idx reg
);
191 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86
*c
);
192 extern void init_amd_cacheinfo(struct cpuinfo_x86
*c
);
194 extern void detect_extended_topology(struct cpuinfo_x86
*c
);
195 extern void detect_ht(struct cpuinfo_x86
*c
);
198 extern int have_cpuid_p(void);
200 static inline int have_cpuid_p(void)
205 static inline void native_cpuid(unsigned int *eax
, unsigned int *ebx
,
206 unsigned int *ecx
, unsigned int *edx
)
208 /* ecx is often an input as well as an output. */
214 : "0" (*eax
), "2" (*ecx
)
218 #define native_cpuid_reg(reg) \
219 static inline unsigned int native_cpuid_##reg(unsigned int op) \
221 unsigned int eax = op, ebx, ecx = 0, edx; \
223 native_cpuid(&eax, &ebx, &ecx, &edx); \
229 * Native CPUID functions returning a single datum.
231 native_cpuid_reg(eax
)
232 native_cpuid_reg(ebx
)
233 native_cpuid_reg(ecx
)
234 native_cpuid_reg(edx
)
237 * Friendlier CR3 helpers.
239 static inline unsigned long read_cr3_pa(void)
241 return __read_cr3() & CR3_ADDR_MASK
;
244 static inline void load_cr3(pgd_t
*pgdir
)
246 write_cr3(__pa(pgdir
));
250 /* This is the TSS defined by the hardware. */
252 unsigned short back_link
, __blh
;
254 unsigned short ss0
, __ss0h
;
258 * We don't use ring 1, so ss1 is a convenient scratch space in
259 * the same cacheline as sp0. We use ss1 to cache the value in
260 * MSR_IA32_SYSENTER_CS. When we context switch
261 * MSR_IA32_SYSENTER_CS, we first check if the new value being
262 * written matches ss1, and, if it's not, then we wrmsr the new
263 * value and update ss1.
265 * The only reason we context switch MSR_IA32_SYSENTER_CS is
266 * that we set it to zero in vm86 tasks to avoid corrupting the
267 * stack if we were to go through the sysenter path from vm86
270 unsigned short ss1
; /* MSR_IA32_SYSENTER_CS */
272 unsigned short __ss1h
;
274 unsigned short ss2
, __ss2h
;
286 unsigned short es
, __esh
;
287 unsigned short cs
, __csh
;
288 unsigned short ss
, __ssh
;
289 unsigned short ds
, __dsh
;
290 unsigned short fs
, __fsh
;
291 unsigned short gs
, __gsh
;
292 unsigned short ldt
, __ldth
;
293 unsigned short trace
;
294 unsigned short io_bitmap_base
;
296 } __attribute__((packed
));
310 } __attribute__((packed
));
316 #define IO_BITMAP_BITS 65536
317 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
318 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
319 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
320 #define INVALID_IO_BITMAP_OFFSET 0x8000
324 * The hardware state:
326 struct x86_hw_tss x86_tss
;
329 * The extra 1 is there because the CPU will access an
330 * additional byte beyond the end of the IO permission
331 * bitmap. The extra byte must be all 1 bits, and must
332 * be within the limit.
334 unsigned long io_bitmap
[IO_BITMAP_LONGS
+ 1];
338 * Space for the temporary SYSENTER stack.
340 unsigned long SYSENTER_stack_canary
;
341 unsigned long SYSENTER_stack
[64];
344 } ____cacheline_aligned
;
346 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct
, cpu_tss
);
349 * sizeof(unsigned long) coming from an extra "long" at the end
352 * -1? seg base+limit should be pointing to the address of the
355 #define __KERNEL_TSS_LIMIT \
356 (IO_BITMAP_OFFSET + IO_BITMAP_BYTES + sizeof(unsigned long) - 1)
359 DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack
);
363 * Save the original ist values for checking stack pointers during debugging
366 unsigned long ist
[7];
370 DECLARE_PER_CPU(struct orig_ist
, orig_ist
);
372 union irq_stack_union
{
373 char irq_stack
[IRQ_STACK_SIZE
];
375 * GCC hardcodes the stack canary as %gs:40. Since the
376 * irq_stack is the object at %gs:0, we reserve the bottom
377 * 48 bytes of the irq stack for the canary.
381 unsigned long stack_canary
;
385 DECLARE_PER_CPU_FIRST(union irq_stack_union
, irq_stack_union
) __visible
;
386 DECLARE_INIT_PER_CPU(irq_stack_union
);
388 DECLARE_PER_CPU(char *, irq_stack_ptr
);
389 DECLARE_PER_CPU(unsigned int, irq_count
);
390 extern asmlinkage
void ignore_sysret(void);
392 #ifdef CONFIG_CC_STACKPROTECTOR
394 * Make sure stack canary segment base is cached-aligned:
395 * "For Intel Atom processors, avoid non zero segment base address
396 * that is not aligned to cache line boundary at all cost."
397 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
399 struct stack_canary
{
400 char __pad
[20]; /* canary at %gs:20 */
401 unsigned long canary
;
403 DECLARE_PER_CPU_ALIGNED(struct stack_canary
, stack_canary
);
406 * per-CPU IRQ handling stacks
409 u32 stack
[THREAD_SIZE
/sizeof(u32
)];
410 } __aligned(THREAD_SIZE
);
412 DECLARE_PER_CPU(struct irq_stack
*, hardirq_stack
);
413 DECLARE_PER_CPU(struct irq_stack
*, softirq_stack
);
416 extern unsigned int fpu_kernel_xstate_size
;
417 extern unsigned int fpu_user_xstate_size
;
425 struct thread_struct
{
426 /* Cached TLS descriptors: */
427 struct desc_struct tls_array
[GDT_ENTRY_TLS_ENTRIES
];
433 unsigned long sysenter_cs
;
437 unsigned short fsindex
;
438 unsigned short gsindex
;
441 u32 status
; /* thread synchronous flags */
444 unsigned long fsbase
;
445 unsigned long gsbase
;
448 * XXX: this could presumably be unsigned short. Alternatively,
449 * 32-bit kernels could be taught to use fsindex instead.
455 /* Save middle states of ptrace breakpoints */
456 struct perf_event
*ptrace_bps
[HBP_NUM
];
457 /* Debug status used for traps, single steps, etc... */
458 unsigned long debugreg6
;
459 /* Keep track of the exact dr7 value set by the user */
460 unsigned long ptrace_dr7
;
463 unsigned long trap_nr
;
464 unsigned long error_code
;
466 /* Virtual 86 mode info */
469 /* IO permissions: */
470 unsigned long *io_bitmap_ptr
;
472 /* Max allowed port in the bitmap, in bytes: */
473 unsigned io_bitmap_max
;
475 mm_segment_t addr_limit
;
477 unsigned int sig_on_uaccess_err
:1;
478 unsigned int uaccess_err
:1; /* uaccess failed */
480 /* Floating point and extended processor state */
483 * WARNING: 'fpu' is dynamically-sized. It *MUST* be at
489 * Thread-synchronous status.
491 * This is different from the flags in that nobody else
492 * ever touches our thread-synchronous status, so we don't
493 * have to worry about atomic accesses.
495 #define TS_COMPAT 0x0002 /* 32bit syscall active (64BIT)*/
498 * Set IOPL bits in EFLAGS from given mask
500 static inline void native_set_iopl_mask(unsigned mask
)
505 asm volatile ("pushfl;"
512 : "i" (~X86_EFLAGS_IOPL
), "r" (mask
));
517 native_load_sp0(unsigned long sp0
)
519 this_cpu_write(cpu_tss
.x86_tss
.sp0
, sp0
);
522 static inline void native_swapgs(void)
525 asm volatile("swapgs" ::: "memory");
529 static inline unsigned long current_top_of_stack(void)
532 return this_cpu_read_stable(cpu_tss
.x86_tss
.sp0
);
534 /* sp0 on x86_32 is special in and around vm86 mode. */
535 return this_cpu_read_stable(cpu_current_top_of_stack
);
539 static inline bool on_thread_stack(void)
541 return (unsigned long)(current_top_of_stack() -
542 current_stack_pointer()) < THREAD_SIZE
;
545 #ifdef CONFIG_PARAVIRT
546 #include <asm/paravirt.h>
548 #define __cpuid native_cpuid
550 static inline void load_sp0(unsigned long sp0
)
552 native_load_sp0(sp0
);
555 #define set_iopl_mask native_set_iopl_mask
556 #endif /* CONFIG_PARAVIRT */
558 /* Free all resources held by a thread. */
559 extern void release_thread(struct task_struct
*);
561 unsigned long get_wchan(struct task_struct
*p
);
564 * Generic CPUID function
565 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
566 * resulting in stale register contents being returned.
568 static inline void cpuid(unsigned int op
,
569 unsigned int *eax
, unsigned int *ebx
,
570 unsigned int *ecx
, unsigned int *edx
)
574 __cpuid(eax
, ebx
, ecx
, edx
);
577 /* Some CPUID calls want 'count' to be placed in ecx */
578 static inline void cpuid_count(unsigned int op
, int count
,
579 unsigned int *eax
, unsigned int *ebx
,
580 unsigned int *ecx
, unsigned int *edx
)
584 __cpuid(eax
, ebx
, ecx
, edx
);
588 * CPUID functions returning a single datum
590 static inline unsigned int cpuid_eax(unsigned int op
)
592 unsigned int eax
, ebx
, ecx
, edx
;
594 cpuid(op
, &eax
, &ebx
, &ecx
, &edx
);
599 static inline unsigned int cpuid_ebx(unsigned int op
)
601 unsigned int eax
, ebx
, ecx
, edx
;
603 cpuid(op
, &eax
, &ebx
, &ecx
, &edx
);
608 static inline unsigned int cpuid_ecx(unsigned int op
)
610 unsigned int eax
, ebx
, ecx
, edx
;
612 cpuid(op
, &eax
, &ebx
, &ecx
, &edx
);
617 static inline unsigned int cpuid_edx(unsigned int op
)
619 unsigned int eax
, ebx
, ecx
, edx
;
621 cpuid(op
, &eax
, &ebx
, &ecx
, &edx
);
626 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
627 static __always_inline
void rep_nop(void)
629 asm volatile("rep; nop" ::: "memory");
632 static __always_inline
void cpu_relax(void)
638 * This function forces the icache and prefetched instruction stream to
639 * catch up with reality in two very specific cases:
641 * a) Text was modified using one virtual address and is about to be executed
642 * from the same physical page at a different virtual address.
644 * b) Text was modified on a different CPU, may subsequently be
645 * executed on this CPU, and you want to make sure the new version
646 * gets executed. This generally means you're calling this in a IPI.
648 * If you're calling this for a different reason, you're probably doing
651 static inline void sync_core(void)
654 * There are quite a few ways to do this. IRET-to-self is nice
655 * because it works on every CPU, at any CPL (so it's compatible
656 * with paravirtualization), and it never exits to a hypervisor.
657 * The only down sides are that it's a bit slow (it seems to be
658 * a bit more than 2x slower than the fastest options) and that
659 * it unmasks NMIs. The "push %cs" is needed because, in
660 * paravirtual environments, __KERNEL_CS may not be a valid CS
661 * value when we do IRET directly.
663 * In case NMI unmasking or performance ever becomes a problem,
664 * the next best option appears to be MOV-to-CR2 and an
665 * unconditional jump. That sequence also works on all CPUs,
666 * but it will fault at CPL3 (i.e. Xen PV and lguest).
668 * CPUID is the conventional way, but it's nasty: it doesn't
669 * exist on some 486-like CPUs, and it usually exits to a
672 * Like all of Linux's memory ordering operations, this is a
673 * compiler barrier as well.
675 register void *__sp
asm(_ASM_SP
);
684 : "+r" (__sp
) : : "memory");
692 "addq $8, (%%rsp)\n\t"
699 : "=&r" (tmp
), "+r" (__sp
) : : "cc", "memory");
703 extern void select_idle_routine(const struct cpuinfo_x86
*c
);
704 extern void amd_e400_c1e_apic_setup(void);
706 extern unsigned long boot_option_idle_override
;
708 enum idle_boot_override
{IDLE_NO_OVERRIDE
=0, IDLE_HALT
, IDLE_NOMWAIT
,
711 extern void enable_sep_cpu(void);
712 extern int sysenter_setup(void);
714 extern void early_trap_init(void);
715 void early_trap_pf_init(void);
717 /* Defined in head.S */
718 extern struct desc_ptr early_gdt_descr
;
720 extern void cpu_set_gdt(int);
721 extern void switch_to_new_gdt(int);
722 extern void load_direct_gdt(int);
723 extern void load_fixmap_gdt(int);
724 extern void load_percpu_segment(int);
725 extern void cpu_init(void);
727 static inline unsigned long get_debugctlmsr(void)
729 unsigned long debugctlmsr
= 0;
731 #ifndef CONFIG_X86_DEBUGCTLMSR
732 if (boot_cpu_data
.x86
< 6)
735 rdmsrl(MSR_IA32_DEBUGCTLMSR
, debugctlmsr
);
740 static inline void update_debugctlmsr(unsigned long debugctlmsr
)
742 #ifndef CONFIG_X86_DEBUGCTLMSR
743 if (boot_cpu_data
.x86
< 6)
746 wrmsrl(MSR_IA32_DEBUGCTLMSR
, debugctlmsr
);
749 extern void set_task_blockstep(struct task_struct
*task
, bool on
);
751 /* Boot loader type from the setup header: */
752 extern int bootloader_type
;
753 extern int bootloader_version
;
755 extern char ignore_fpu_irq
;
757 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
758 #define ARCH_HAS_PREFETCHW
759 #define ARCH_HAS_SPINLOCK_PREFETCH
762 # define BASE_PREFETCH ""
763 # define ARCH_HAS_PREFETCH
765 # define BASE_PREFETCH "prefetcht0 %P1"
769 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
771 * It's not worth to care about 3dnow prefetches for the K6
772 * because they are microcoded there and very slow.
774 static inline void prefetch(const void *x
)
776 alternative_input(BASE_PREFETCH
, "prefetchnta %P1",
778 "m" (*(const char *)x
));
782 * 3dnow prefetch to get an exclusive cache line.
783 * Useful for spinlocks to avoid one state transition in the
784 * cache coherency protocol:
786 static inline void prefetchw(const void *x
)
788 alternative_input(BASE_PREFETCH
, "prefetchw %P1",
789 X86_FEATURE_3DNOWPREFETCH
,
790 "m" (*(const char *)x
));
793 static inline void spin_lock_prefetch(const void *x
)
798 #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \
799 TOP_OF_KERNEL_STACK_PADDING)
801 #define task_top_of_stack(task) ((unsigned long)(task_pt_regs(task) + 1))
803 #define task_pt_regs(task) \
805 unsigned long __ptr = (unsigned long)task_stack_page(task); \
806 __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \
807 ((struct pt_regs *)__ptr) - 1; \
812 * User space process size: 3GB (default).
814 #define IA32_PAGE_OFFSET PAGE_OFFSET
815 #define TASK_SIZE PAGE_OFFSET
816 #define TASK_SIZE_MAX TASK_SIZE
817 #define STACK_TOP TASK_SIZE
818 #define STACK_TOP_MAX STACK_TOP
820 #define INIT_THREAD { \
821 .sp0 = TOP_OF_INIT_STACK, \
822 .sysenter_cs = __KERNEL_CS, \
823 .io_bitmap_ptr = NULL, \
824 .addr_limit = KERNEL_DS, \
827 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
831 * User space process size. 47bits minus one guard page. The guard
832 * page is necessary on Intel CPUs: if a SYSCALL instruction is at
833 * the highest possible canonical userspace address, then that
834 * syscall will enter the kernel with a non-canonical return
835 * address, and SYSRET will explode dangerously. We avoid this
836 * particular problem by preventing anything from being mapped
837 * at the maximum canonical address.
839 #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE)
841 /* This decides where the kernel will search for a free chunk of vm
842 * space during mmap's.
844 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
845 0xc0000000 : 0xFFFFe000)
847 #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \
848 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
849 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \
850 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
852 #define STACK_TOP TASK_SIZE
853 #define STACK_TOP_MAX TASK_SIZE_MAX
855 #define INIT_THREAD { \
856 .addr_limit = KERNEL_DS, \
859 extern unsigned long KSTK_ESP(struct task_struct
*task
);
861 #endif /* CONFIG_X86_64 */
863 extern void start_thread(struct pt_regs
*regs
, unsigned long new_ip
,
864 unsigned long new_sp
);
867 * This decides where the kernel will search for a free chunk of vm
868 * space during mmap's.
870 #define __TASK_UNMAPPED_BASE(task_size) (PAGE_ALIGN(task_size / 3))
871 #define TASK_UNMAPPED_BASE __TASK_UNMAPPED_BASE(TASK_SIZE)
873 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
875 /* Get/set a process' ability to use the timestamp counter instruction */
876 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
877 #define SET_TSC_CTL(val) set_tsc_mode((val))
879 extern int get_tsc_mode(unsigned long adr
);
880 extern int set_tsc_mode(unsigned int val
);
882 DECLARE_PER_CPU(u64
, msr_misc_features_shadow
);
884 /* Register/unregister a process' MPX related resource */
885 #define MPX_ENABLE_MANAGEMENT() mpx_enable_management()
886 #define MPX_DISABLE_MANAGEMENT() mpx_disable_management()
888 #ifdef CONFIG_X86_INTEL_MPX
889 extern int mpx_enable_management(void);
890 extern int mpx_disable_management(void);
892 static inline int mpx_enable_management(void)
896 static inline int mpx_disable_management(void)
900 #endif /* CONFIG_X86_INTEL_MPX */
902 #ifdef CONFIG_CPU_SUP_AMD
903 extern u16
amd_get_nb_id(int cpu
);
904 extern u32
amd_get_nodes_per_socket(void);
906 static inline u16
amd_get_nb_id(int cpu
) { return 0; }
907 static inline u32
amd_get_nodes_per_socket(void) { return 0; }
910 static inline uint32_t hypervisor_cpuid_base(const char *sig
, uint32_t leaves
)
912 uint32_t base
, eax
, signature
[3];
914 for (base
= 0x40000000; base
< 0x40010000; base
+= 0x100) {
915 cpuid(base
, &eax
, &signature
[0], &signature
[1], &signature
[2]);
917 if (!memcmp(sig
, signature
, 12) &&
918 (leaves
== 0 || ((eax
- base
) >= leaves
)))
925 extern unsigned long arch_align_stack(unsigned long sp
);
926 extern void free_init_pages(char *what
, unsigned long begin
, unsigned long end
);
928 void default_idle(void);
930 bool xen_set_default_idle(void);
932 #define xen_set_default_idle 0
935 void stop_this_cpu(void *dummy
);
936 void df_debug(struct pt_regs
*regs
, long error_code
);
937 #endif /* _ASM_X86_PROCESSOR_H */