arch/x86/include/asm/processor.h

   1 #ifndef _ASM_X86_PROCESSOR_H
   2 #define _ASM_X86_PROCESSOR_H
   3
   4 #include <asm/processor-flags.h>
   5
   6 /* Forward declaration, a strange C thing */
   7 struct task_struct;
   8 struct mm_struct;
   9
  10 #include <asm/vm86.h>
  11 #include <asm/math_emu.h>
  12 #include <asm/segment.h>
  13 #include <asm/types.h>
  14 #include <asm/sigcontext.h>
  15 #include <asm/current.h>
  16 #include <asm/cpufeature.h>
  17 #include <asm/system.h>
  18 #include <asm/page.h>
  19 #include <asm/pgtable_types.h>
  20 #include <asm/percpu.h>
  21 #include <asm/msr.h>
  22 #include <asm/desc_defs.h>
  23 #include <asm/nops.h>
  24
  25 #include <linux/personality.h>
  26 #include <linux/cpumask.h>
  27 #include <linux/cache.h>
  28 #include <linux/threads.h>
  29 #include <linux/math64.h>
  30 #include <linux/init.h>
  31 #include <linux/err.h>
  32
  33 #define HBP_NUM 4
  34 /*
  35  * Default implementation of macro that returns current
  36  * instruction pointer ("program counter").
  37  */
  38 static inline void *current_text_addr(void)
  39 {
  40         void *pc;
  41
  42         asm volatile("mov $1f, %0; 1:":"=r" (pc));
  43
  44         return pc;
  45 }
  46
  47 #ifdef CONFIG_X86_VSMP
  48 # define ARCH_MIN_TASKALIGN             (1 << INTERNODE_CACHE_SHIFT)
  49 # define ARCH_MIN_MMSTRUCT_ALIGN        (1 << INTERNODE_CACHE_SHIFT)
  50 #else
  51 # define ARCH_MIN_TASKALIGN             16
  52 # define ARCH_MIN_MMSTRUCT_ALIGN        0
  53 #endif
  54
  55 /*
  56  *  CPU type and hardware bug flags. Kept separately for each CPU.
  57  *  Members of this structure are referenced in head.S, so think twice
  58  *  before touching them. [mj]
  59  */
  60
  61 struct cpuinfo_x86 {
  62         __u8                    x86;            /* CPU family */
  63         __u8                    x86_vendor;     /* CPU vendor */
  64         __u8                    x86_model;
  65         __u8                    x86_mask;
  66 #ifdef CONFIG_X86_32
  67         char                    wp_works_ok;    /* It doesn't on 386's */
  68
  69         /* Problems on some 486Dx4's and old 386's: */
  70         char                    hlt_works_ok;
  71         char                    hard_math;
  72         char                    rfu;
  73         char                    fdiv_bug;
  74         char                    f00f_bug;
  75         char                    coma_bug;
  76         char                    pad0;
  77 #else
  78         /* Number of 4K pages in DTLB/ITLB combined(in pages): */
  79         int                     x86_tlbsize;
  80 #endif
  81         __u8                    x86_virt_bits;
  82         __u8                    x86_phys_bits;
  83         /* CPUID returned core id bits: */
  84         __u8                    x86_coreid_bits;
  85         /* Max extended CPUID function supported: */
  86         __u32                   extended_cpuid_level;
  87         /* Maximum supported CPUID level, -1=no CPUID: */
  88         int                     cpuid_level;
  89         __u32                   x86_capability[NCAPINTS];
  90         char                    x86_vendor_id[16];
  91         char                    x86_model_id[64];
  92         /* in KB - valid for CPUS which support this call: */
  93         int                     x86_cache_size;
  94         int                     x86_cache_alignment;    /* In bytes */
  95         int                     x86_power;
  96         unsigned long           loops_per_jiffy;
  97         /* cpuid returned max cores value: */
  98         u16                      x86_max_cores;
  99         u16                     apicid;
 100         u16                     initial_apicid;
 101         u16                     x86_clflush_size;
 102         /* number of cores as seen by the OS: */
 103         u16                     booted_cores;
 104         /* Physical processor id: */
 105         u16                     phys_proc_id;
 106         /* Core id: */
 107         u16                     cpu_core_id;
 108         /* Compute unit id */
 109         u8                      compute_unit_id;
 110         /* Index into per_cpu list: */
 111         u16                     cpu_index;
 112         u32                     microcode;
 113 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
 114
 115 #define X86_VENDOR_INTEL        0
 116 #define X86_VENDOR_CYRIX        1
 117 #define X86_VENDOR_AMD          2
 118 #define X86_VENDOR_UMC          3
 119 #define X86_VENDOR_CENTAUR      5
 120 #define X86_VENDOR_TRANSMETA    7
 121 #define X86_VENDOR_NSC          8
 122 #define X86_VENDOR_NUM          9
 123
 124 #define X86_VENDOR_UNKNOWN      0xff
 125
 126 /*
 127  * capabilities of CPUs
 128  */
 129 extern struct cpuinfo_x86       boot_cpu_data;
 130 extern struct cpuinfo_x86       new_cpu_data;
 131
 132 extern struct tss_struct        doublefault_tss;
 133 extern __u32                    cpu_caps_cleared[NCAPINTS];
 134 extern __u32                    cpu_caps_set[NCAPINTS];
 135
 136 #ifdef CONFIG_SMP
 137 DECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
 138 #define cpu_data(cpu)           per_cpu(cpu_info, cpu)
 139 #else
 140 #define cpu_info                boot_cpu_data
 141 #define cpu_data(cpu)           boot_cpu_data
 142 #endif
 143
 144 extern const struct seq_operations cpuinfo_op;
 145
 146 static inline int hlt_works(int cpu)
 147 {
 148 #ifdef CONFIG_X86_32
 149         return cpu_data(cpu).hlt_works_ok;
 150 #else
 151         return 1;
 152 #endif
 153 }
 154
 155 #define cache_line_size()       (boot_cpu_data.x86_cache_alignment)
 156
 157 extern void cpu_detect(struct cpuinfo_x86 *c);
 158
 159 extern struct pt_regs *idle_regs(struct pt_regs *);
 160
 161 extern void early_cpu_init(void);
 162 extern void identify_boot_cpu(void);
 163 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
 164 extern void print_cpu_info(struct cpuinfo_x86 *);
 165 void print_cpu_msr(struct cpuinfo_x86 *);
 166 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
 167 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
 168 extern unsigned short num_cache_leaves;
 169
 170 extern void detect_extended_topology(struct cpuinfo_x86 *c);
 171 extern void detect_ht(struct cpuinfo_x86 *c);
 172
 173 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
 174                                 unsigned int *ecx, unsigned int *edx)
 175 {
 176         /* ecx is often an input as well as an output. */
 177         asm volatile("cpuid"
 178             : "=a" (*eax),
 179               "=b" (*ebx),
 180               "=c" (*ecx),
 181               "=d" (*edx)
 182             : "0" (*eax), "2" (*ecx)
 183             : "memory");
 184 }
 185
 186 static inline void load_cr3(pgd_t *pgdir)
 187 {
 188         write_cr3(__pa(pgdir));
 189 }
 190
 191 #ifdef CONFIG_X86_32
 192 /* This is the TSS defined by the hardware. */
 193 struct x86_hw_tss {
 194         unsigned short          back_link, __blh;
 195         unsigned long           sp0;
 196         unsigned short          ss0, __ss0h;
 197         unsigned long           sp1;
 198         /* ss1 caches MSR_IA32_SYSENTER_CS: */
 199         unsigned short          ss1, __ss1h;
 200         unsigned long           sp2;
 201         unsigned short          ss2, __ss2h;
 202         unsigned long           __cr3;
 203         unsigned long           ip;
 204         unsigned long           flags;
 205         unsigned long           ax;
 206         unsigned long           cx;
 207         unsigned long           dx;
 208         unsigned long           bx;
 209         unsigned long           sp;
 210         unsigned long           bp;
 211         unsigned long           si;
 212         unsigned long           di;
 213         unsigned short          es, __esh;
 214         unsigned short          cs, __csh;
 215         unsigned short          ss, __ssh;
 216         unsigned short          ds, __dsh;
 217         unsigned short          fs, __fsh;
 218         unsigned short          gs, __gsh;
 219         unsigned short          ldt, __ldth;
 220         unsigned short          trace;
 221         unsigned short          io_bitmap_base;
 222
 223 } __attribute__((packed));
 224 #else
 225 struct x86_hw_tss {
 226         u32                     reserved1;
 227         u64                     sp0;
 228         u64                     sp1;
 229         u64                     sp2;
 230         u64                     reserved2;
 231         u64                     ist[7];
 232         u32                     reserved3;
 233         u32                     reserved4;
 234         u16                     reserved5;
 235         u16                     io_bitmap_base;
 236
 237 } __attribute__((packed)) ____cacheline_aligned;
 238 #endif
 239
 240 /*
 241  * IO-bitmap sizes:
 242  */
 243 #define IO_BITMAP_BITS                  65536
 244 #define IO_BITMAP_BYTES                 (IO_BITMAP_BITS/8)
 245 #define IO_BITMAP_LONGS                 (IO_BITMAP_BYTES/sizeof(long))
 246 #define IO_BITMAP_OFFSET                offsetof(struct tss_struct, io_bitmap)
 247 #define INVALID_IO_BITMAP_OFFSET        0x8000
 248
 249 struct tss_struct {
 250         /*
 251          * The hardware state:
 252          */
 253         struct x86_hw_tss       x86_tss;
 254
 255         /*
 256          * The extra 1 is there because the CPU will access an
 257          * additional byte beyond the end of the IO permission
 258          * bitmap. The extra byte must be all 1 bits, and must
 259          * be within the limit.
 260          */
 261         unsigned long           io_bitmap[IO_BITMAP_LONGS + 1];
 262
 263         /*
 264          * .. and then another 0x100 bytes for the emergency kernel stack:
 265          */
 266         unsigned long           stack[64];
 267
 268 } ____cacheline_aligned;
 269
 270 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss);
 271
 272 /*
 273  * Save the original ist values for checking stack pointers during debugging
 274  */
 275 struct orig_ist {
 276         unsigned long           ist[7];
 277 };
 278
 279 #define MXCSR_DEFAULT           0x1f80
 280
 281 struct i387_fsave_struct {
 282         u32                     cwd;    /* FPU Control Word             */
 283         u32                     swd;    /* FPU Status Word              */
 284         u32                     twd;    /* FPU Tag Word                 */
 285         u32                     fip;    /* FPU IP Offset                */
 286         u32                     fcs;    /* FPU IP Selector              */
 287         u32                     foo;    /* FPU Operand Pointer Offset   */
 288         u32                     fos;    /* FPU Operand Pointer Selector */
 289
 290         /* 8*10 bytes for each FP-reg = 80 bytes:                       */
 291         u32                     st_space[20];
 292
 293         /* Software status information [not touched by FSAVE ]:         */
 294         u32                     status;
 295 };
 296
 297 struct i387_fxsave_struct {
 298         u16                     cwd; /* Control Word                    */
 299         u16                     swd; /* Status Word                     */
 300         u16                     twd; /* Tag Word                        */
 301         u16                     fop; /* Last Instruction Opcode         */
 302         union {
 303                 struct {
 304                         u64     rip; /* Instruction Pointer             */
 305                         u64     rdp; /* Data Pointer                    */
 306                 };
 307                 struct {
 308                         u32     fip; /* FPU IP Offset                   */
 309                         u32     fcs; /* FPU IP Selector                 */
 310                         u32     foo; /* FPU Operand Offset              */
 311                         u32     fos; /* FPU Operand Selector            */
 312                 };
 313         };
 314         u32                     mxcsr;          /* MXCSR Register State */
 315         u32                     mxcsr_mask;     /* MXCSR Mask           */
 316
 317         /* 8*16 bytes for each FP-reg = 128 bytes:                      */
 318         u32                     st_space[32];
 319
 320         /* 16*16 bytes for each XMM-reg = 256 bytes:                    */
 321         u32                     xmm_space[64];
 322
 323         u32                     padding[12];
 324
 325         union {
 326                 u32             padding1[12];
 327                 u32             sw_reserved[12];
 328         };
 329
 330 } __attribute__((aligned(16)));
 331
 332 struct i387_soft_struct {
 333         u32                     cwd;
 334         u32                     swd;
 335         u32                     twd;
 336         u32                     fip;
 337         u32                     fcs;
 338         u32                     foo;
 339         u32                     fos;
 340         /* 8*10 bytes for each FP-reg = 80 bytes: */
 341         u32                     st_space[20];
 342         u8                      ftop;
 343         u8                      changed;
 344         u8                      lookahead;
 345         u8                      no_update;
 346         u8                      rm;
 347         u8                      alimit;
 348         struct math_emu_info    *info;
 349         u32                     entry_eip;
 350 };
 351
 352 struct ymmh_struct {
 353         /* 16 * 16 bytes for each YMMH-reg = 256 bytes */
 354         u32 ymmh_space[64];
 355 };
 356
 357 struct xsave_hdr_struct {
 358         u64 xstate_bv;
 359         u64 reserved1[2];
 360         u64 reserved2[5];
 361 } __attribute__((packed));
 362
 363 struct xsave_struct {
 364         struct i387_fxsave_struct i387;
 365         struct xsave_hdr_struct xsave_hdr;
 366         struct ymmh_struct ymmh;
 367         /* new processor state extensions will go here */
 368 } __attribute__ ((packed, aligned (64)));
 369
 370 union thread_xstate {
 371         struct i387_fsave_struct        fsave;
 372         struct i387_fxsave_struct       fxsave;
 373         struct i387_soft_struct         soft;
 374         struct xsave_struct             xsave;
 375 };
 376
 377 struct fpu {
 378         union thread_xstate *state;
 379 };
 380
 381 #ifdef CONFIG_X86_64
 382 DECLARE_PER_CPU(struct orig_ist, orig_ist);
 383
 384 union irq_stack_union {
 385         char irq_stack[IRQ_STACK_SIZE];
 386         /*
 387          * GCC hardcodes the stack canary as %gs:40.  Since the
 388          * irq_stack is the object at %gs:0, we reserve the bottom
 389          * 48 bytes of the irq stack for the canary.
 390          */
 391         struct {
 392                 char gs_base[40];
 393                 unsigned long stack_canary;
 394         };
 395 };
 396
 397 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union);
 398 DECLARE_INIT_PER_CPU(irq_stack_union);
 399
 400 DECLARE_PER_CPU(char *, irq_stack_ptr);
 401 DECLARE_PER_CPU(unsigned int, irq_count);
 402 extern unsigned long kernel_eflags;
 403 extern asmlinkage void ignore_sysret(void);
 404 #else   /* X86_64 */
 405 #ifdef CONFIG_CC_STACKPROTECTOR
 406 /*
 407  * Make sure stack canary segment base is cached-aligned:
 408  *   "For Intel Atom processors, avoid non zero segment base address
 409  *    that is not aligned to cache line boundary at all cost."
 410  * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
 411  */
 412 struct stack_canary {
 413         char __pad[20];         /* canary at %gs:20 */
 414         unsigned long canary;
 415 };
 416 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
 417 #endif
 418 #endif  /* X86_64 */
 419
 420 extern unsigned int xstate_size;
 421 extern void free_thread_xstate(struct task_struct *);
 422 extern struct kmem_cache *task_xstate_cachep;
 423
 424 struct perf_event;
 425
 426 struct thread_struct {
 427         /* Cached TLS descriptors: */
 428         struct desc_struct      tls_array[GDT_ENTRY_TLS_ENTRIES];
 429         unsigned long           sp0;
 430         unsigned long           sp;
 431 #ifdef CONFIG_X86_32
 432         unsigned long           sysenter_cs;
 433 #else
 434         unsigned long           usersp; /* Copy from PDA */
 435         unsigned short          es;
 436         unsigned short          ds;
 437         unsigned short          fsindex;
 438         unsigned short          gsindex;
 439 #endif
 440 #ifdef CONFIG_X86_32
 441         unsigned long           ip;
 442 #endif
 443 #ifdef CONFIG_X86_64
 444         unsigned long           fs;
 445 #endif
 446         unsigned long           gs;
 447         /* Save middle states of ptrace breakpoints */
 448         struct perf_event       *ptrace_bps[HBP_NUM];
 449         /* Debug status used for traps, single steps, etc... */
 450         unsigned long           debugreg6;
 451         /* Keep track of the exact dr7 value set by the user */
 452         unsigned long           ptrace_dr7;
 453         /* Fault info: */
 454         unsigned long           cr2;
 455         unsigned long           trap_no;
 456         unsigned long           error_code;
 457         /* floating point and extended processor state */
 458         struct fpu              fpu;
 459 #ifdef CONFIG_X86_32
 460         /* Virtual 86 mode info */
 461         struct vm86_struct __user *vm86_info;
 462         unsigned long           screen_bitmap;
 463         unsigned long           v86flags;
 464         unsigned long           v86mask;
 465         unsigned long           saved_sp0;
 466         unsigned int            saved_fs;
 467         unsigned int            saved_gs;
 468 #endif
 469         /* IO permissions: */
 470         unsigned long           *io_bitmap_ptr;
 471         unsigned long           iopl;
 472         /* Max allowed port in the bitmap, in bytes: */
 473         unsigned                io_bitmap_max;
 474 };
 475
 476 static inline unsigned long native_get_debugreg(int regno)
 477 {
 478         unsigned long val = 0;  /* Damn you, gcc! */
 479
 480         switch (regno) {
 481         case 0:
 482                 asm("mov %%db0, %0" :"=r" (val));
 483                 break;
 484         case 1:
 485                 asm("mov %%db1, %0" :"=r" (val));
 486                 break;
 487         case 2:
 488                 asm("mov %%db2, %0" :"=r" (val));
 489                 break;
 490         case 3:
 491                 asm("mov %%db3, %0" :"=r" (val));
 492                 break;
 493         case 6:
 494                 asm("mov %%db6, %0" :"=r" (val));
 495                 break;
 496         case 7:
 497                 asm("mov %%db7, %0" :"=r" (val));
 498                 break;
 499         default:
 500                 BUG();
 501         }
 502         return val;
 503 }
 504
 505 static inline void native_set_debugreg(int regno, unsigned long value)
 506 {
 507         switch (regno) {
 508         case 0:
 509                 asm("mov %0, %%db0"     ::"r" (value));
 510                 break;
 511         case 1:
 512                 asm("mov %0, %%db1"     ::"r" (value));
 513                 break;
 514         case 2:
 515                 asm("mov %0, %%db2"     ::"r" (value));
 516                 break;
 517         case 3:
 518                 asm("mov %0, %%db3"     ::"r" (value));
 519                 break;
 520         case 6:
 521                 asm("mov %0, %%db6"     ::"r" (value));
 522                 break;
 523         case 7:
 524                 asm("mov %0, %%db7"     ::"r" (value));
 525                 break;
 526         default:
 527                 BUG();
 528         }
 529 }
 530
 531 /*
 532  * Set IOPL bits in EFLAGS from given mask
 533  */
 534 static inline void native_set_iopl_mask(unsigned mask)
 535 {
 536 #ifdef CONFIG_X86_32
 537         unsigned int reg;
 538
 539         asm volatile ("pushfl;"
 540                       "popl %0;"
 541                       "andl %1, %0;"
 542                       "orl %2, %0;"
 543                       "pushl %0;"
 544                       "popfl"
 545                       : "=&r" (reg)
 546                       : "i" (~X86_EFLAGS_IOPL), "r" (mask));
 547 #endif
 548 }
 549
 550 static inline void
 551 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
 552 {
 553         tss->x86_tss.sp0 = thread->sp0;
 554 #ifdef CONFIG_X86_32
 555         /* Only happens when SEP is enabled, no need to test "SEP"arately: */
 556         if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
 557                 tss->x86_tss.ss1 = thread->sysenter_cs;
 558                 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
 559         }
 560 #endif
 561 }
 562
 563 static inline void native_swapgs(void)
 564 {
 565 #ifdef CONFIG_X86_64
 566         asm volatile("swapgs" ::: "memory");
 567 #endif
 568 }
 569
 570 #ifdef CONFIG_PARAVIRT
 571 #include <asm/paravirt.h>
 572 #else
 573 #define __cpuid                 native_cpuid
 574 #define paravirt_enabled()      0
 575
 576 /*
 577  * These special macros can be used to get or set a debugging register
 578  */
 579 #define get_debugreg(var, register)                             \
 580         (var) = native_get_debugreg(register)
 581 #define set_debugreg(value, register)                           \
 582         native_set_debugreg(register, value)
 583
 584 static inline void load_sp0(struct tss_struct *tss,
 585                             struct thread_struct *thread)
 586 {
 587         native_load_sp0(tss, thread);
 588 }
 589
 590 #define set_iopl_mask native_set_iopl_mask
 591 #endif /* CONFIG_PARAVIRT */
 592
 593 /*
 594  * Save the cr4 feature set we're using (ie
 595  * Pentium 4MB enable and PPro Global page
 596  * enable), so that any CPU's that boot up
 597  * after us can get the correct flags.
 598  */
 599 extern unsigned long            mmu_cr4_features;
 600
 601 static inline void set_in_cr4(unsigned long mask)
 602 {
 603         unsigned long cr4;
 604
 605         mmu_cr4_features |= mask;
 606         cr4 = read_cr4();
 607         cr4 |= mask;
 608         write_cr4(cr4);
 609 }
 610
 611 static inline void clear_in_cr4(unsigned long mask)
 612 {
 613         unsigned long cr4;
 614
 615         mmu_cr4_features &= ~mask;
 616         cr4 = read_cr4();
 617         cr4 &= ~mask;
 618         write_cr4(cr4);
 619 }
 620
 621 typedef struct {
 622         unsigned long           seg;
 623 } mm_segment_t;
 624
 625
 626 /*
 627  * create a kernel thread without removing it from tasklists
 628  */
 629 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
 630
 631 /* Free all resources held by a thread. */
 632 extern void release_thread(struct task_struct *);
 633
 634 /* Prepare to copy thread state - unlazy all lazy state */
 635 extern void prepare_to_copy(struct task_struct *tsk);
 636
 637 unsigned long get_wchan(struct task_struct *p);
 638
 639 /*
 640  * Generic CPUID function
 641  * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
 642  * resulting in stale register contents being returned.
 643  */
 644 static inline void cpuid(unsigned int op,
 645                          unsigned int *eax, unsigned int *ebx,
 646                          unsigned int *ecx, unsigned int *edx)
 647 {
 648         *eax = op;
 649         *ecx = 0;
 650         __cpuid(eax, ebx, ecx, edx);
 651 }
 652
 653 /* Some CPUID calls want 'count' to be placed in ecx */
 654 static inline void cpuid_count(unsigned int op, int count,
 655                                unsigned int *eax, unsigned int *ebx,
 656                                unsigned int *ecx, unsigned int *edx)
 657 {
 658         *eax = op;
 659         *ecx = count;
 660         __cpuid(eax, ebx, ecx, edx);
 661 }
 662
 663 /*
 664  * CPUID functions returning a single datum
 665  */
 666 static inline unsigned int cpuid_eax(unsigned int op)
 667 {
 668         unsigned int eax, ebx, ecx, edx;
 669
 670         cpuid(op, &eax, &ebx, &ecx, &edx);
 671
 672         return eax;
 673 }
 674
 675 static inline unsigned int cpuid_ebx(unsigned int op)
 676 {
 677         unsigned int eax, ebx, ecx, edx;
 678
 679         cpuid(op, &eax, &ebx, &ecx, &edx);
 680
 681         return ebx;
 682 }
 683
 684 static inline unsigned int cpuid_ecx(unsigned int op)
 685 {
 686         unsigned int eax, ebx, ecx, edx;
 687
 688         cpuid(op, &eax, &ebx, &ecx, &edx);
 689
 690         return ecx;
 691 }
 692
 693 static inline unsigned int cpuid_edx(unsigned int op)
 694 {
 695         unsigned int eax, ebx, ecx, edx;
 696
 697         cpuid(op, &eax, &ebx, &ecx, &edx);
 698
 699         return edx;
 700 }
 701
 702 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
 703 static inline void rep_nop(void)
 704 {
 705         asm volatile("rep; nop" ::: "memory");
 706 }
 707
 708 static inline void cpu_relax(void)
 709 {
 710         rep_nop();
 711 }
 712
 713 /* Stop speculative execution and prefetching of modified code. */
 714 static inline void sync_core(void)
 715 {
 716         int tmp;
 717
 718 #if defined(CONFIG_M386) || defined(CONFIG_M486)
 719         if (boot_cpu_data.x86 < 5)
 720                 /* There is no speculative execution.
 721                  * jmp is a barrier to prefetching. */
 722                 asm volatile("jmp 1f\n1:\n" ::: "memory");
 723         else
 724 #endif
 725                 /* cpuid is a barrier to speculative execution.
 726                  * Prefetched instructions are automatically
 727                  * invalidated when modified. */
 728                 asm volatile("cpuid" : "=a" (tmp) : "0" (1)
 729                              : "ebx", "ecx", "edx", "memory");
 730 }
 731
 732 static inline void __monitor(const void *eax, unsigned long ecx,
 733                              unsigned long edx)
 734 {
 735         /* "monitor %eax, %ecx, %edx;" */
 736         asm volatile(".byte 0x0f, 0x01, 0xc8;"
 737                      :: "a" (eax), "c" (ecx), "d"(edx));
 738 }
 739
 740 static inline void __mwait(unsigned long eax, unsigned long ecx)
 741 {
 742         /* "mwait %eax, %ecx;" */
 743         asm volatile(".byte 0x0f, 0x01, 0xc9;"
 744                      :: "a" (eax), "c" (ecx));
 745 }
 746
 747 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
 748 {
 749         trace_hardirqs_on();
 750         /* "mwait %eax, %ecx;" */
 751         asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
 752                      :: "a" (eax), "c" (ecx));
 753 }
 754
 755 extern void select_idle_routine(const struct cpuinfo_x86 *c);
 756 extern void init_amd_e400_c1e_mask(void);
 757
 758 extern unsigned long            boot_option_idle_override;
 759 extern bool                     amd_e400_c1e_detected;
 760
 761 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
 762                          IDLE_POLL, IDLE_FORCE_MWAIT};
 763
 764 extern void enable_sep_cpu(void);
 765 extern int sysenter_setup(void);
 766
 767 extern void early_trap_init(void);
 768
 769 /* Defined in head.S */
 770 extern struct desc_ptr          early_gdt_descr;
 771
 772 extern void cpu_set_gdt(int);
 773 extern void switch_to_new_gdt(int);
 774 extern void load_percpu_segment(int);
 775 extern void cpu_init(void);
 776
 777 static inline unsigned long get_debugctlmsr(void)
 778 {
 779         unsigned long debugctlmsr = 0;
 780
 781 #ifndef CONFIG_X86_DEBUGCTLMSR
 782         if (boot_cpu_data.x86 < 6)
 783                 return 0;
 784 #endif
 785         rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
 786
 787         return debugctlmsr;
 788 }
 789
 790 static inline void update_debugctlmsr(unsigned long debugctlmsr)
 791 {
 792 #ifndef CONFIG_X86_DEBUGCTLMSR
 793         if (boot_cpu_data.x86 < 6)
 794                 return;
 795 #endif
 796         wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
 797 }
 798
 799 /*
 800  * from system description table in BIOS. Mostly for MCA use, but
 801  * others may find it useful:
 802  */
 803 extern unsigned int             machine_id;
 804 extern unsigned int             machine_submodel_id;
 805 extern unsigned int             BIOS_revision;
 806
 807 /* Boot loader type from the setup header: */
 808 extern int                      bootloader_type;
 809 extern int                      bootloader_version;
 810
 811 extern char                     ignore_fpu_irq;
 812
 813 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
 814 #define ARCH_HAS_PREFETCHW
 815 #define ARCH_HAS_SPINLOCK_PREFETCH
 816
 817 #ifdef CONFIG_X86_32
 818 # define BASE_PREFETCH          ASM_NOP4
 819 # define ARCH_HAS_PREFETCH
 820 #else
 821 # define BASE_PREFETCH          "prefetcht0 (%1)"
 822 #endif
 823
 824 /*
 825  * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
 826  *
 827  * It's not worth to care about 3dnow prefetches for the K6
 828  * because they are microcoded there and very slow.
 829  */
 830 static inline void prefetch(const void *x)
 831 {
 832         alternative_input(BASE_PREFETCH,
 833                           "prefetchnta (%1)",
 834                           X86_FEATURE_XMM,
 835                           "r" (x));
 836 }
 837
 838 /*
 839  * 3dnow prefetch to get an exclusive cache line.
 840  * Useful for spinlocks to avoid one state transition in the
 841  * cache coherency protocol:
 842  */
 843 static inline void prefetchw(const void *x)
 844 {
 845         alternative_input(BASE_PREFETCH,
 846                           "prefetchw (%1)",
 847                           X86_FEATURE_3DNOW,
 848                           "r" (x));
 849 }
 850
 851 static inline void spin_lock_prefetch(const void *x)
 852 {
 853         prefetchw(x);
 854 }
 855
 856 #ifdef CONFIG_X86_32
 857 /*
 858  * User space process size: 3GB (default).
 859  */
 860 #define TASK_SIZE               PAGE_OFFSET
 861 #define TASK_SIZE_MAX           TASK_SIZE
 862 #define STACK_TOP               TASK_SIZE
 863 #define STACK_TOP_MAX           STACK_TOP
 864
 865 #define INIT_THREAD  {                                                    \
 866         .sp0                    = sizeof(init_stack) + (long)&init_stack, \
 867         .vm86_info              = NULL,                                   \
 868         .sysenter_cs            = __KERNEL_CS,                            \
 869         .io_bitmap_ptr          = NULL,                                   \
 870 }
 871
 872 /*
 873  * Note that the .io_bitmap member must be extra-big. This is because
 874  * the CPU will access an additional byte beyond the end of the IO
 875  * permission bitmap. The extra byte must be all 1 bits, and must
 876  * be within the limit.
 877  */
 878 #define INIT_TSS  {                                                       \
 879         .x86_tss = {                                                      \
 880                 .sp0            = sizeof(init_stack) + (long)&init_stack, \
 881                 .ss0            = __KERNEL_DS,                            \
 882                 .ss1            = __KERNEL_CS,                            \
 883                 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,               \
 884          },                                                               \
 885         .io_bitmap              = { [0 ... IO_BITMAP_LONGS] = ~0 },       \
 886 }
 887
 888 extern unsigned long thread_saved_pc(struct task_struct *tsk);
 889
 890 #define THREAD_SIZE_LONGS      (THREAD_SIZE/sizeof(unsigned long))
 891 #define KSTK_TOP(info)                                                 \
 892 ({                                                                     \
 893        unsigned long *__ptr = (unsigned long *)(info);                 \
 894        (unsigned long)(&__ptr[THREAD_SIZE_LONGS]);                     \
 895 })
 896
 897 /*
 898  * The below -8 is to reserve 8 bytes on top of the ring0 stack.
 899  * This is necessary to guarantee that the entire "struct pt_regs"
 900  * is accessible even if the CPU haven't stored the SS/ESP registers
 901  * on the stack (interrupt gate does not save these registers
 902  * when switching to the same priv ring).
 903  * Therefore beware: accessing the ss/esp fields of the
 904  * "struct pt_regs" is possible, but they may contain the
 905  * completely wrong values.
 906  */
 907 #define task_pt_regs(task)                                             \
 908 ({                                                                     \
 909        struct pt_regs *__regs__;                                       \
 910        __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
 911        __regs__ - 1;                                                   \
 912 })
 913
 914 #define KSTK_ESP(task)          (task_pt_regs(task)->sp)
 915
 916 #else
 917 /*
 918  * User space process size. 47bits minus one guard page.
 919  */
 920 #define TASK_SIZE_MAX   ((1UL << 47) - PAGE_SIZE)
 921
 922 /* This decides where the kernel will search for a free chunk of vm
 923  * space during mmap's.
 924  */
 925 #define IA32_PAGE_OFFSET        ((current->personality & ADDR_LIMIT_3GB) ? \
 926                                         0xc0000000 : 0xFFFFe000)
 927
 928 #define TASK_SIZE               (test_thread_flag(TIF_IA32) ? \
 929                                         IA32_PAGE_OFFSET : TASK_SIZE_MAX)
 930 #define TASK_SIZE_OF(child)     ((test_tsk_thread_flag(child, TIF_IA32)) ? \
 931                                         IA32_PAGE_OFFSET : TASK_SIZE_MAX)
 932
 933 #define STACK_TOP               TASK_SIZE
 934 #define STACK_TOP_MAX           TASK_SIZE_MAX
 935
 936 #define INIT_THREAD  { \
 937         .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
 938 }
 939
 940 #define INIT_TSS  { \
 941         .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
 942 }
 943
 944 /*
 945  * Return saved PC of a blocked thread.
 946  * What is this good for? it will be always the scheduler or ret_from_fork.
 947  */
 948 #define thread_saved_pc(t)      (*(unsigned long *)((t)->thread.sp - 8))
 949
 950 #define task_pt_regs(tsk)       ((struct pt_regs *)(tsk)->thread.sp0 - 1)
 951 extern unsigned long KSTK_ESP(struct task_struct *task);
 952 #endif /* CONFIG_X86_64 */
 953
 954 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
 955                                                unsigned long new_sp);
 956
 957 /*
 958  * This decides where the kernel will search for a free chunk of vm
 959  * space during mmap's.
 960  */
 961 #define TASK_UNMAPPED_BASE      (PAGE_ALIGN(TASK_SIZE / 3))
 962
 963 #define KSTK_EIP(task)          (task_pt_regs(task)->ip)
 964
 965 /* Get/set a process' ability to use the timestamp counter instruction */
 966 #define GET_TSC_CTL(adr)        get_tsc_mode((adr))
 967 #define SET_TSC_CTL(val)        set_tsc_mode((val))
 968
 969 extern int get_tsc_mode(unsigned long adr);
 970 extern int set_tsc_mode(unsigned int val);
 971
 972 extern int amd_get_nb_id(int cpu);
 973
 974 struct aperfmperf {
 975         u64 aperf, mperf;
 976 };
 977
 978 static inline void get_aperfmperf(struct aperfmperf *am)
 979 {
 980         WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_APERFMPERF));
 981
 982         rdmsrl(MSR_IA32_APERF, am->aperf);
 983         rdmsrl(MSR_IA32_MPERF, am->mperf);
 984 }
 985
 986 #define APERFMPERF_SHIFT 10
 987
 988 static inline
 989 unsigned long calc_aperfmperf_ratio(struct aperfmperf *old,
 990                                     struct aperfmperf *new)
 991 {
 992         u64 aperf = new->aperf - old->aperf;
 993         u64 mperf = new->mperf - old->mperf;
 994         unsigned long ratio = aperf;
 995
 996         mperf >>= APERFMPERF_SHIFT;
 997         if (mperf)
 998                 ratio = div64_u64(aperf, mperf);
 999
1000         return ratio;
1001 }
1002
1003 /*
1004  * AMD errata checking
1005  */
1006 #ifdef CONFIG_CPU_SUP_AMD
1007 extern const int amd_erratum_383[];
1008 extern const int amd_erratum_400[];
1009 extern bool cpu_has_amd_erratum(const int *);
1010
1011 #define AMD_LEGACY_ERRATUM(...)         { -1, __VA_ARGS__, 0 }
1012 #define AMD_OSVW_ERRATUM(osvw_id, ...)  { osvw_id, __VA_ARGS__, 0 }
1013 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
1014         ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
1015 #define AMD_MODEL_RANGE_FAMILY(range)   (((range) >> 24) & 0xff)
1016 #define AMD_MODEL_RANGE_START(range)    (((range) >> 12) & 0xfff)
1017 #define AMD_MODEL_RANGE_END(range)      ((range) & 0xfff)
1018
1019 #else
1020 #define cpu_has_amd_erratum(x)  (false)
1021 #endif /* CONFIG_CPU_SUP_AMD */
1022
1023 #endif /* _ASM_X86_PROCESSOR_H */